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Searched refs:GPRC (Results 1 – 10 of 10) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZc.td106 : RVInst16CLB<funct6, 0b00, (outs GPRC:$rd),
116 : RVInst16CLH<funct6, funct1, 0b00, (outs GPRC:$rd),
127 (ins GPRC:$rs2, GPRCMem:$rs1, uimm2:$imm),
137 (ins GPRC:$rs2, GPRCMem:$rs1, uimm2_lsb0:$imm),
146 RVInst16CU<0b100111, funct5, 0b01, (outs GPRC:$rd_wb), (ins GPRC:$rd),
187 def C_MUL : CA_ALU<0b100111, 0b10, "c.mul", GPRC>,
274 def : CompressPat<(MUL GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
275 (C_MUL GPRC:$rs1, GPRC:$rs2)>;
277 def : CompressPat<(MUL GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
278 (C_MUL GPRC:$rs1, GPRC:$rs2)>;
[all …]
H A DRISCVInstrInfoXwch.td82 def QK_C_LBU : RVInst16CL<0b001, 0b00, (outs GPRC:$rd),
93 (ins GPRC:$rs2, GPRCMem:$rs1,
104 def QK_C_LHU : RVInst16CL<0b001, 0b10, (outs GPRC:$rd),
114 (ins GPRC:$rs2, GPRCMem:$rs1, uimm6_lsb0:$imm),
123 def QK_C_LBUSP : QKStackInst<0b00, (outs GPRC:$rd_rs2),
132 (ins GPRC:$rd_rs2, SPMem:$rs1,
141 def QK_C_LHUSP : QKStackInst<0b01, (outs GPRC:$rd_rs2),
151 (ins GPRC:$rd_rs2, SPMem:$rs1, uimm5_lsb0:$imm),
167 def : InstAlias<"qk.c.lbu $rd, (${rs1})", (QK_C_LBU GPRC:$rd, GPRCMem:$rs1, 0)>;
168 def : InstAlias<"qk.c.sb $rs2, (${rs1})", (QK_C_SB GPRC:$rs2, GPRCMem:$rs1, 0)>;
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H A DRISCVInstrInfoC.td307 def C_ADDI4SPN : RVInst16CIW<0b000, 0b00, (outs GPRC:$rd),
326 def C_LW : CLoad_ri<0b010, "c.lw", GPRC, uimm7_lsb00>,
345 def C_LD : CLoad_ri<0b011, "c.ld", GPRC, uimm8_lsb000>,
360 def C_SW : CStore_rri<0b110, "c.sw", GPRC, uimm7_lsb00>,
379 def C_SD : CStore_rri<0b111, "c.sd", GPRC, uimm8_lsb000>,
456 def C_SRLI : Shift_right<0b00, "c.srli", GPRC, uimmlog2xlennonzero>,
458 def C_SRAI : Shift_right<0b01, "c.srai", GPRC, uimmlog2xlennonzero>,
462 def C_ANDI : RVInst16CB<0b100, 0b01, (outs GPRC:$rs1_wb), (ins GPRC:$rs1, simm6:$imm),
471 def C_SUB : CA_ALU<0b100011, 0b00, "c.sub", GPRC>,
473 def C_XOR : CA_ALU<0b100011, 0b01, "c.xor", GPRC>,
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H A DRISCVRegisterInfo.td79 // are not part of GPRC, the most restrictive register class used by the
180 def GPRC : GPRRegisterClass<(add (sequence "X%u", 10, 15),
H A DRISCVInstrInfo.td140 def GPRCMem : MemOperand<GPRC>;
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp758 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerDynamicAlloc() local
759 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerDynamicAlloc()
824 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in prepareDynamicAlloca() local
865 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in prepareDynamicAlloca()
873 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in prepareDynamicAlloca()
967 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRSpilling() local
969 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
981 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
1012 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRRestore() local
1014 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRRestore()
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H A DPPCRegisterInfo.td334 def GPRC : RegisterClass<"PPC", [i32,f32], 32, (add (sequence "R%u", 2, 12),
342 let AltOrders = [(add (sub GPRC, R2), R2),
366 def GPRC_NOR0 : RegisterClass<"PPC", [i32,f32], 32, (add (sub GPRC, R0), ZERO)> {
534 def gprc : RegisterOperand<GPRC> {
612 def spe4rc : RegisterOperand<GPRC> {
H A DPPCISelLowering.cpp12265 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in EmitPartwordAtomicBinary() local
12268 Register Shift1Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
12270 isLittleEndian ? Shift1Reg : RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
12271 Register Incr2Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
12272 Register MaskReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
12273 Register Mask2Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
12274 Register Mask3Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
12275 Register Tmp2Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
12276 Register Tmp3Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
12277 Register Tmp4Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
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H A DPPCFrameLowering.cpp2304 const TargetRegisterClass &GPRC = PPC::GPRCRegClass; in addScavengingSpillSlot() local
2306 const TargetRegisterClass &RC = Subtarget.isPPC64() ? G8RC : GPRC; in addScavengingSpillSlot()
H A DPPCInstrVSX.td2671 (COPY_TO_REGCLASS (XVTDIVDP $A, $B), GPRC)>;
2673 (COPY_TO_REGCLASS (XVTDIVSP $A, $B), GPRC)>;
2675 (COPY_TO_REGCLASS (XVTSQRTDP $A), GPRC)>;
2677 (COPY_TO_REGCLASS (XVTSQRTSP $A), GPRC)>;