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Searched refs:FP8 (Results 1 – 22 of 22) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64Features.td487 def FeatureFP8 : ExtensionWithMArch<"fp8", "FP8", "FEAT_FP8",
488 "Enable FP8 instructions", [FeatureNEON]>;
491 "Enable Armv9.5-A FP8 multiply-add instructions", [FeatureFP8]>;
494 "Enable SVE2 FP8 multiply-add instructions", [FeatureSME2, FeatureFP8]>;
497 "Enable FP8 4-way dot instructions", [FeatureFP8]>;
500 "Enable FP8 2-way dot instructions", [FeatureFP8]>;
503 "Enable SVE2 FP8 4-way dot product instructions", [FeatureSME2, FeatureFP8]>;
506 "Enable SVE2 FP8 2-way dot product instructions", [FeatureSME2, FeatureFP8]>;
534 "Enable Armv9.6-A FP8 to Single-Precision Matrix Multiplication", [FeatureNEON, FeatureFP8]>;
537 "Enable Armv9.6-A FP8 to Half-Precision Matrix Multiplication", [FeatureNEON, FeatureFP8]>;
H A DAArch64SVEInstrInfo.td4579 // SVE2 FP8 instructions
4582 // FP8 upconvert
4592 // FP8 downconvert
4609 // FP8 Widening Multiply-Add Long - Indexed Group
4612 // FP8 Widening Multiply-Add Long Group
4615 // FP8 Widening Multiply-Add Long Long - Indexed Group
4620 // FP8 Widening Multiply-Add Long Long Group
4636 // FP8 Widening Dot-Product - Indexed Group
4638 // FP8 Widening Dot-Product - Group
4644 // FP8 Widening Dot-Product - Indexed Group
[all …]
H A DSMEInstrFormats.td2561 // SME2 multi-vec FP8 down convert two registers
2600 // SME2 multi-vec FP8 up convert two registers
2634 //SME2 multi-vec FP8 down convert four registers
2846 // SME2 multi-vec indexed FP8 two-way dot product to FP16 two registers
2862 // SME2 multi-vec indexed FP8 two-way vertical dot product to single precision
2968 // SME2.1 multi-vec ternary indexed four registers 16-bit (FP8)
3053 // FMLAL (multiple and indexed vector, FP8 to FP16)
3112 // FMLAL (single and indexed vector, FP8 to FP16)
6123 // FP8 SME FDOT instructions
H A DSVEInstrFormats.td10900 // SVE2 FP8 Instructions
10903 // FP8 upconvert
10929 // FP8 downconvert
10984 // FP8 Widening Multiply-Add Long - Indexed Group
11015 // FP8 Widening Multiply-Add (Long)/(Long Long) Group
11045 // FP8 Widening Multiply-Add Long Long - Indexed Group
11076 // FP8 Matrix Multiply-accumulate Group
11125 // FP8 Widening Dot-Product - Indexed Group
11147 // FP8 Look up table
11166 // FP8 Look up table read with 2-bit indices
[all …]
H A DAArch64InstrFormats.td6533 // FP8 assembly/disassembly classes
6536 // FP8 Advanced SIMD three-register extension
6562 // FCVTN (FP16 to FP8)
6574 // FCVTN, FCVTN2 (FP32 to FP8)
7051 // FP8 Advanced SIMD two-register miscellaneous
9224 // FP8 Advanced SIMD vector x indexed element
H A DAArch64SystemOperands.td2259 // AArch64 Floating-point Mode Register controls behaviors of the FP8
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.h194 return Reg == PPC::FP || Reg == PPC::FP8; in isVirtualFrameRegister()
H A DPPCRegisterInfo.td238 def FP8 : GP8<FP, "**FRAME POINTER**">;
352 X31, X13, X0, X1, FP8, BP8)> {
357 (sequence "X%u", 31, 13), X0, X1, FP8, BP8)];
382 (sequence "X%u", 31, 13), X1, FP8, BP8, ZERO8)];
H A DPPCFrameLowering.cpp410 case PPC::FP8: in replaceFPWithRealFP()
H A DPPCISelLowering.cpp18029 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP; in LowerFRAMEADDR()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAArch64.td556 // FP8 fscale
997 // Neon FP8 intrinsics
4022 // FP8 Intrinsics
4153 // CVT from FP8 to half-precision/BFloat16 multi-vector
4159 // CVT from FP8 to deinterleaved half-precision/BFloat16 multi-vector
4165 // CVT to FP8 from half-precision/BFloat16/single-precision multi-vector
4175 // FP8 outer product
4207 // FP8 FDOT intrinsics
H A DIntrinsicsX86.td5490 // AMX-FP8
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.h62 enum class FPType { None, FP4, FP8 }; enumerator
H A DAMDGPUBaseInfo.cpp739 return FPType::FP8; in getFPDstSelType()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrAMX.td271 // AMX-FP8
H A DX86.td269 "Support AMX-FP8 instructions",
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Darm_sme.td325 // SME2 - FP8 FMOP4A, FMOP4S
872 // SME2 FP8 instructions
H A Darm_sve.td2304 // Convert from FP8 to half-precision/BFloat16 multi-vector
2308 // Convert from FP8 to deinterleaved half-precision/BFloat16 multi-vector
2312 // Convert from single/half/bfloat multivector to FP8
2334 // SVE FP8 widening conversions
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNHazardRecognizer.cpp909 if (IsFP4OrFP8ConvOpc == AMDGPU::FPType::FP8 && in getDstSelForwardingOperand()
H A DAMDGPU.td843 "FP8/BF8 VOP1 form of conversion to F32 is unreliable",
H A DVOPInstructions.td1766 // FIXME-TRUE16 support FP8 instructions properly
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.td597 // FP8 conversions.