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Searched refs:FMSUB (Results 1 – 14 of 14) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCSchedPredicates.td47 FMSUB,
H A DP10InstrResources.td206 FMSUB,
H A DP9InstrResources.td418 (instregex "FMSUB(S)?$"),
H A DPPCInstrInfo.td3016 defm FMSUB : AForm_1r<63, 28,
3445 (FMSUB $A, $B, $C)>;
3461 def : Pat<(int_ppc_fmsub f64:$A, f64:$B, f64:$C), (FMSUB $A, $B, $C)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.cpp2462 : RISCVMachineCombinerPattern::FMSUB); in getFPFusedMultiplyPatterns()
2578 case RISCVMachineCombinerPattern::FMSUB: in getCombinerObjective()
2611 return Pattern == RISCVMachineCombinerPattern::FMSUB ? RISCV::FMSUB_H in getFPFusedMultiplyOpcode()
2614 return Pattern == RISCVMachineCombinerPattern::FMSUB ? RISCV::FMSUB_S in getFPFusedMultiplyOpcode()
2617 return Pattern == RISCVMachineCombinerPattern::FMSUB ? RISCV::FMSUB_D in getFPFusedMultiplyOpcode()
2627 case RISCVMachineCombinerPattern::FMSUB: in getAddendOperandIdx()
2751 case RISCVMachineCombinerPattern::FMSUB: { in genAlternativeCodeSequence()
3788 case CASE_VFMA_SPLATS(FMSUB): in findCommutedOpIndices()
3821 case CASE_VFMA_OPCODE_VV(FMSUB): in findCommutedOpIndices()
3973 case CASE_VFMA_SPLATS(FMSUB): in commuteInstructionImpl()
[all …]
H A DRISCVInstrInfo.h56 FMSUB, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstComments.cpp346 CASE_FMA4_PACKED_RR(FMSUB) in printFMAComments()
347 CASE_FMA4_SCALAR_RR(FMSUB) in printFMAComments()
350 CASE_FMA4_PACKED_RM(FMSUB) in printFMAComments()
351 CASE_FMA4_SCALAR_RM(FMSUB) in printFMAComments()
356 CASE_FMA4_PACKED_MR(FMSUB) in printFMAComments()
357 CASE_FMA4_SCALAR_MR(FMSUB) in printFMAComments()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h577 FMSUB, enumerator
H A DX86InstrFragmentsSIMD.td571 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFPTernaryOp, [SDNPCommutative]>;
H A DX86ISelLowering.cpp35175 NODE_NAME_CASE(FMSUB) in getTargetNodeName()
43252 if (FMSub.getOpcode() != X86ISD::FMSUB) in combineShuffleToFMAddSub()
43255 if (FMAdd.getOpcode() != ISD::FMA || FMSub.getOpcode() != X86ISD::FMSUB || in combineShuffleToFMAddSub()
54602 case X86ISD::FMSUB: Opcode = X86ISD::FNMSUB; break; in negateFMAOpcode()
54608 case X86ISD::FNMSUB: Opcode = X86ISD::FMSUB; break; in negateFMAOpcode()
54619 case ISD::FMA: Opcode = X86ISD::FMSUB; break; in negateFMAOpcode()
54622 case X86ISD::FMSUB: Opcode = ISD::FMA; break; in negateFMAOpcode()
54646 case X86ISD::FMSUB: Opcode = X86ISD::FNMADD; break; in negateFMAOpcode()
54648 case X86ISD::FNMADD: Opcode = X86ISD::FMSUB; break; in negateFMAOpcode()
54714 case X86ISD::FMSUB: in getNegatedExpression()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedThunderX2T99.td1184 (instregex "^FMADD", "^FMSUB", "^FNMADD", "^FNMSUB")>;
H A DAArch64SchedThunderX3T110.td1292 (instregex "^FMADD", "^FMSUB", "^FNMADD", "^FNMSUB")>;
H A DAArch64SchedNeoverseN3.td838 def : InstRW<[N3Write_4c_1V], (instregex "^(FMADD|FMSUB|FNMADD|FNMSUB)[DHS]rrr$")>;
H A DAArch64InstrInfo.td5528 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
5538 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike