| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VectorCombine.cpp | 105 ExtractElementInst *Ext1,
107 bool isExtractExtractCheap(ExtractElementInst *Ext0, ExtractElementInst *Ext1,
111 void foldExtExtCmp(ExtractElementInst *Ext0, ExtractElementInst *Ext1,
113 void foldExtExtBinop(ExtractElementInst *Ext0, ExtractElementInst *Ext1,
380 ExtractElementInst *Ext0, ExtractElementInst *Ext1, in getShuffleExtract() argument
383 auto *Index1C = dyn_cast<ConstantInt>(Ext1->getIndexOperand()); in getShuffleExtract()
394 assert(VecTy == Ext1->getVectorOperand()->getType() && "Need matching types"); in getShuffleExtract()
398 TTI.getVectorInstrCost(*Ext1, VecTy, CostKind, Index1); in getShuffleExtract()
410 return Ext1; in getShuffleExtract()
415 return Ext1; in getShuffleExtract()
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| H A D | VPlanTransforms.cpp | 2921 VPWidenCastRecipe *Ext1, VPWidenCastRecipe *OuterExt) -> bool { in tryToMatchAndCreateMulAccumulateReduction() argument
2935 if (Ext1) in tryToMatchAndCreateMulAccumulateReduction()
2936 ExtCost += Ext1->computeCost(VF, Ctx); in tryToMatchAndCreateMulAccumulateReduction()
2979 auto *Ext1 = in tryToMatchAndCreateMulAccumulateReduction() local
2981 if ((Ext->getOpcode() == Ext0->getOpcode() || Ext0 == Ext1) && in tryToMatchAndCreateMulAccumulateReduction()
2982 Ext0->getOpcode() == Ext1->getOpcode() && in tryToMatchAndCreateMulAccumulateReduction()
2985 Mul, Ext0, Ext1, Ext)) { in tryToMatchAndCreateMulAccumulateReduction()
2992 if (Ext0 != Ext1) { in tryToMatchAndCreateMulAccumulateReduction()
2993 NewExt1 = new VPWidenCastRecipe(Ext1->getOpcode(), Ext1->getOperand(0), in tryToMatchAndCreateMulAccumulateReduction()
2994 Ext->getResultType(), *Ext1, in tryToMatchAndCreateMulAccumulateReduction()
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| H A D | VPlanRecipes.cpp | 2761 auto *Ext1 = cast<VPWidenCastRecipe>(ExpressionRecipes[1]); in print() local
2762 O << " " << Instruction::getOpcodeName(Ext1->getOpcode()) << " to " in print()
2763 << *Ext1->getResultType() << ")"; in print()
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| H A D | VPlan.h | 2817 VPExpressionRecipe(VPWidenCastRecipe *Ext0, VPWidenCastRecipe *Ext1, in VPExpressionRecipe() argument
2820 {Ext0, Ext1, Mul, Red}) {} in VPExpressionRecipe()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/BinaryFormat/ |
| H A D | MsgPack.def | 94 HANDLE_MP_FIX_LEN(0x01, Ext1)
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| /freebsd/contrib/llvm-project/llvm/lib/BinaryFormat/ |
| H A D | MsgPackWriter.cpp | 179 case FixLen::Ext1: in writeExt()
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| H A D | MsgPackReader.cpp | 122 return createExt(Obj, FixLen::Ext1); in read()
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| /freebsd/contrib/llvm-project/llvm/lib/TargetParser/ |
| H A D | RISCVISAInfo.cpp | 734 static Error getIncompatibleError(StringRef Ext1, StringRef Ext2) { in getIncompatibleError() argument
735 return getError("'" + Ext1 + "' and '" + Ext2 + in getIncompatibleError()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMTargetTransformInfo.cpp | 2752 static bool areExtractExts(Value *Ext1, Value *Ext2) { in areExtractExts() argument
2760 if (!match(Ext1, m_ZExtOrSExt(m_Value())) || in areExtractExts()
2762 !areExtDoubled(cast<Instruction>(Ext1)) || in areExtractExts()
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| H A D | ARMISelLowering.cpp | 9455 SDValue Ext1 = Ext.getValue(1); in LowerVectorExtend() local
9459 Ext1 = DAG.getNode(N->getOpcode(), DL, MVT::v8i32, Ext1); in LowerVectorExtend()
9462 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ToVT, Ext, Ext1); in LowerVectorExtend()
10382 SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0, in LowerVecReduce() local
10388 SDValue Res0 = DAG.getNode(BaseOpcode, dl, EltVT, Ext0, Ext1, Op->getFlags()); in LowerVecReduce()
10394 SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0, in LowerVecReduce() local
10396 Res = DAG.getNode(BaseOpcode, dl, EltVT, Ext0, Ext1, Op->getFlags()); in LowerVecReduce()
13443 SDValue Ext1 = Mul.getOperand(1); in PerformVQDMULHCombine() local
13445 Ext1.getOpcode() != ISD::SIGN_EXTEND) in PerformVQDMULHCombine()
13450 if (Ext1.getOperand(0).getValueType() != VecVT || in PerformVQDMULHCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetTransformInfo.cpp | 6034 static bool areExtractExts(Value *Ext1, Value *Ext2) { in areExtractExts() argument
6040 if (!match(Ext1, m_ZExtOrSExt(m_Value())) || in areExtractExts()
6042 !areExtDoubled(cast<Instruction>(Ext1)) || in areExtractExts()
6278 auto Ext1 = cast<Instruction>(I->getOperand(0)); in isProfitableToSinkOperands() local
6280 if (areExtractShuffleVectors(Ext1->getOperand(0), Ext2->getOperand(0))) { in isProfitableToSinkOperands()
6281 Ops.push_back(&Ext1->getOperandUse(0)); in isProfitableToSinkOperands()
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| H A D | AArch64ISelLowering.cpp | 4335 SDValue Ext1 = in LowerFP_EXTEND() local
4339 {Ext1, Ext1.getValue(1)}); in LowerFP_EXTEND()
18409 SDValue Ext1 = Op1.getOperand(0); in performUADDVAddCombine() local
18411 Ext1.getOpcode() != ISD::EXTRACT_SUBVECTOR || in performUADDVAddCombine()
18412 Ext0.getOperand(0) != Ext1.getOperand(0)) in performUADDVAddCombine()
18420 Ext1.getConstantOperandVal(1) != VT.getVectorNumElements()) && in performUADDVAddCombine()
18421 (Ext1.getConstantOperandVal(1) != 0 || in performUADDVAddCombine()
18457 SDValue Ext1 = Op1.getOperand(0); in performUADDVZextCombine() local
18459 EVT ExtVT1 = Ext1.getValueType(); in performUADDVZextCombine()
18467 DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(A), PairVT, Ext0, Ext1); in performUADDVZextCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCompares.cpp | 3146 Instruction *Ext0, *Ext1; in foldICmpAddConstant() local
3150 m_CombineAnd(m_Instruction(Ext1), in foldICmpAddConstant()
3161 Res += APInt(BW, isa<ZExtInst>(Ext1) ? 1 : -1, /*isSigned=*/true); in foldICmpAddConstant()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 15919 SDValue Ext1 = FirstInput.getOperand(0); in DAGCombineBuildVector() local
15921 if(Ext1.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in DAGCombineBuildVector()
15925 ConstantSDNode *Ext1Op = dyn_cast<ConstantSDNode>(Ext1.getOperand(1)); in DAGCombineBuildVector()
15929 if (Ext1.getOperand(0).getValueType() != MVT::v4i32 || in DAGCombineBuildVector()
15930 Ext1.getOperand(0) != Ext2.getOperand(0)) in DAGCombineBuildVector()
15943 SDValue SrcVec = Ext1.getOperand(0); in DAGCombineBuildVector()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 3809 auto Ext1 = B.buildFPExt(F32, Src1, Flags); in legalizeFPow() local
3812 .addUse(Ext1.getReg(0)) in legalizeFPow()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 13719 SDValue Ext1 = DAG.getNode(Opcode, DL, VT, Op1); in tryToFoldExtendSelectLoad() local
13721 return DAG.getSelect(DL, VT, N0->getOperand(0), Ext1, Ext2); in tryToFoldExtendSelectLoad()
14382 SDValue Ext1 = DAG.getNode(ExtOpcode, DL, VT, N01); in foldSextSetcc() local
14383 return DAG.getSetCC(DL, VT, Ext0, Ext1, CC); in foldSextSetcc()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 46751 SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, OpVT, in scalarizeExtEltFP() local
46753 return DAG.getNode(Vec.getOpcode(), DL, VT, Ext0, Ext1, Vec.getOperand(2)); in scalarizeExtEltFP()
46774 SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, in scalarizeExtEltFP() local
46778 return DAG.getNode(ISD::SELECT, DL, VT, Ext0, Ext1, Ext2); in scalarizeExtEltFP()
59685 SDValue Ext1 = extractSubVector(InVec.getOperand(1), 0, DAG, DL, 128); in combineEXTRACT_SUBVECTOR() local
59687 return DAG.getNode(InOpcode, DL, VT, Ext0, Ext1, Ext2); in combineEXTRACT_SUBVECTOR()
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