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Searched refs:DefaultMode (Results 1 – 20 of 20) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kRegisterInfo.td102 let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<8,16,16>]> in
104 let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<16,16,16>]> in
106 let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<32,32,32>]> in
110 let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<16,16,16>]> in
112 let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<32,32,32>]> in
115 let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<32,32,32>]> in
120 let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<16,16,16>]> in
122 let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<32,32,32>]> in
125 let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<32,32,32>]> in
129 let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<32,32,32>]> in
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DInfoByHwMode.h39 DefaultMode = CodeGenHwModes::DefaultMode, enumerator
50 if (AI != A.end() && AI->first == DefaultMode) { in union_modes()
54 if (BI != B.end() && BI->first == DefaultMode) { in union_modes()
84 Modes.push_back(DefaultMode); in union_modes()
111 return !Map.empty() && Map.begin()->first == DefaultMode; in hasDefault()
130 assert(F != Map.end() && F->first == DefaultMode); in get()
136 return Map.size() == 1 && Map.begin()->first == DefaultMode; in isSimple()
147 Map.try_emplace(DefaultMode, I); in makeSimple()
157 ValueTypeByHwMode(MVT T) { Map.try_emplace(DefaultMode, T); } in ValueTypeByHwMode()
233 Map.try_emplace(DefaultMode, Range); in SubRegRangeByHwMode()
H A DCodeGenHwModes.h46 enum : unsigned { DefaultMode = 0 }; enumerator
56 if (IncludeDefault && Id == CodeGenHwModes::DefaultMode)
H A DCodeGenRegisters.h122 if (M == DefaultMode) in addComposite()
136 SubRegRange &Range = this->Range.get(DefaultMode); in addComposite()
137 SubRegRange &ARange = A->Range.get(DefaultMode); in addComposite()
138 SubRegRange &BRange = B->Range.get(DefaultMode); in addComposite()
H A DInfoByHwMode.cpp26 if (Mode == DefaultMode) in getModeName()
73 if (D != Map.end() && D->first == DefaultMode) in getOrCreateTypeForMode()
H A DCodeGenHwModes.cpp79 return DefaultMode; in getHwModeId()
H A DCodeGenDAGPatterns.cpp126 if (DefaultMode == M) { in insert()
148 if (M == DefaultMode || hasMode(M)) in constrain()
150 Map.try_emplace(M, Map.at(DefaultMode)); in constrain()
855 TypeSetByHwMode::SetType &LegalTypes = LegalCache.getOrCreate(DefaultMode); in getLegalTypes()
1860 if (S.get(DefaultMode).empty()) in setDefaultMode()
4496 if (M == DefaultMode) in ExpandHwModeBasedTypes()
4511 bool HasDefault = Modes.count(DefaultMode); in ExpandHwModeBasedTypes()
4513 AppendPattern(P, DefaultMode, DefaultCheck); in ExpandHwModeBasedTypes()
H A DCodeGenRegisters.cpp63 Range.insertSubRegRangeForMode(DefaultMode, SubRegRange(R)); in CodeGenSubRegIndex()
743 RSI.insertRegSizeForMode(DefaultMode, RI); in CodeGenRegisterClass()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeEmitterGen.cpp73 const CodeGenTarget &Target, unsigned HwMode = DefaultMode);
307 if (ModeId == DefaultMode) { in getInstructionCases()
309 " case " + itostr(DefaultMode) + ": InstBitsByHw = InstBits"; in getInstructionCases()
402 if (HwMode == DefaultMode) in emitInstructionBaseValues()
525 emitInstructionBaseValues(O, NumberedInstructions, Target, DefaultMode); in run()
529 if (HwMode == DefaultMode) in run()
H A DRegisterBankEmitter.cpp272 if (M == DefaultMode) in emitBaseClassImplementation()
H A DDecoderEmitter.cpp2472 if (P.first == DefaultMode) { in collectHwModesReferencedForEncodings()
2483 if (M == DefaultMode) in collectHwModesReferencedForEncodings()
2565 if (ModeId == DefaultMode) { in run()
H A DSubtargetEmitter.cpp1788 if (P.first == DefaultMode) in emitHwModeCheck()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td474 def VecI1: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
476 def VecI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
478 def VecI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
480 def VecI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
482 def VecF16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
484 def VecF32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
487 def VecPI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
489 def VecPI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
491 def VecPI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
493 def VecPF16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIModeRegister.cpp120 unsigned DefaultMode = FP_ROUND_ROUND_TO_NEAREST; member in __anon61d306190111::SIModeRegister
122 Status(FP_ROUND_MODE_DP(0x3), FP_ROUND_MODE_DP(DefaultMode));
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArch.td41 defvar LA32 = DefaultMode;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64Subtarget.cpp424 AArch64HwModeBits Modes = AArch64HwModeBits::DefaultMode; in getHwModeSet()
H A DAArch64RegisterInfo.td988 [DefaultMode, SMEWithZPRPredicateSpills],
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td257 def FP16RI : RegInfoByHwMode<[DefaultMode, NoVecHwMode],
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTarget.td39 def DefaultMode : HwMode<"", []>;
107 // If the HwModes provided for SubRegRanges does not include the DefaultMode,
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVFeatures.td1662 defvar RV32 = DefaultMode;