Searched refs:ComputeLoop (Results 1 – 2 of 2) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUAtomicOptimizer.cpp | 87 BasicBlock *ComputeLoop, BasicBlock *ComputeEnd) const; 543 Instruction &I, BasicBlock *ComputeLoop, BasicBlock *ComputeEnd) const { in buildScanIteratively() argument 553 B.SetInsertPoint(ComputeLoop); in buildScanIteratively() 581 OldValuePhi->addIncoming(OldValue, ComputeLoop); in buildScanIteratively() 586 Accumulator->addIncoming(NewAccumulator, ComputeLoop); in buildScanIteratively() 594 ActiveBits->addIncoming(NewActiveBits, ComputeLoop); in buildScanIteratively() 598 B.CreateCondBr(IsEnd, ComputeEnd, ComputeLoop); in buildScanIteratively() 729 BasicBlock *ComputeLoop = nullptr; in optimizeAtomic() local 759 ComputeLoop = BasicBlock::Create(C, "ComputeLoop", F); in optimizeAtomic() 762 ComputeLoop, ComputeEnd); in optimizeAtomic() [all …]
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| H A D | SIISelLowering.cpp | 5193 auto [ComputeLoop, ComputeEnd] = splitBlockForLoop(MI, BB, true); in lowerWaveReduce() 5222 .addMBB(ComputeLoop); in lowerWaveReduce() 5226 I = ComputeLoop->end(); in lowerWaveReduce() 5228 BuildMI(*ComputeLoop, I, DL, TII->get(AMDGPU::PHI), AccumulatorReg) in lowerWaveReduce() 5232 BuildMI(*ComputeLoop, I, DL, TII->get(AMDGPU::PHI), ActiveBitsReg) in lowerWaveReduce() 5238 auto FF1 = BuildMI(*ComputeLoop, I, DL, TII->get(SFFOpc), FF1Reg) in lowerWaveReduce() 5240 auto LaneValue = BuildMI(*ComputeLoop, I, DL, in lowerWaveReduce() 5244 auto NewAccumulator = BuildMI(*ComputeLoop, I, DL, TII->get(Opc), DstReg) in lowerWaveReduce() 5252 BuildMI(*ComputeLoop, I, DL, TII->get(BITSETOpc), NewActiveBitsReg) in lowerWaveReduce() 5258 .addMBB(ComputeLoop); in lowerWaveReduce() [all …]
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