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Searched refs:CONCAT_VECTORS (Results 1 – 25 of 27) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp777 case ISD::CONCAT_VECTORS: in ScalarizeVectorOperand()
1132 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break; in SplitVectorResult()
1639 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps); in SplitVecRes_CONCAT_VECTORS()
1642 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps); in SplitVecRes_CONCAT_VECTORS()
1975 ISD::CONCAT_VECTORS, dl, OtherVT, in SplitVecRes_OverflowOp()
2688 DAG.getNode(ISD::CONCAT_VECTORS, dl, OtherVT, SDValue(LoNode, OtherNo), in SplitVecRes_UnaryOpWithTwoResults()
2868 if (Inputs[SrcRegIdx].getOpcode() == ISD::CONCAT_VECTORS && in SplitVecRes_VECTOR_SHUFFLE()
2909 ISD::CONCAT_VECTORS, DL, in SplitVecRes_VECTOR_SHUFFLE()
3416 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break; in SplitVectorOperand()
3607 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect); in SplitVecOp_VSELECT()
[all …]
H A DDAGCombiner.cpp2020 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); in visit()
12400 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
12401 RHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
12441 ISD::CONCAT_VECTORS, DL, VT, in ConvertSelectToConcatVector()
13430 if (N1.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
13431 N2.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
13973 SDValue NewValue = DAG.getNode(ISD::CONCAT_VECTORS, DL, DstVT, Loads); in CombineExtLoad()
15789 if (!Src.hasOneUse() || Src.getOpcode() != ISD::CONCAT_VECTORS) in foldExtendVectorInregToExtendOfSubvector()
16171 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) { in visitTRUNCATE()
16208 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds); in visitTRUNCATE()
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H A DSelectionDAGDumper.cpp343 case ISD::CONCAT_VECTORS: return "concat_vectors"; in getOperationName()
H A DSelectionDAG.cpp3524 case ISD::CONCAT_VECTORS: { in computeKnownBits()
5210 case ISD::CONCAT_VECTORS: { in ComputeNumSignBits()
5538 case ISD::CONCAT_VECTORS: in canCreateUndefOrPoison()
6364 case ISD::CONCAT_VECTORS: in getNode()
6795 if (Opcode >= ISD::BUILTIN_OP_END || Opcode == ISD::CONCAT_VECTORS) in FoldConstantArithmetic()
7457 case ISD::CONCAT_VECTORS: { in getNode()
7716 if (N2C && N1.getOpcode() == ISD::CONCAT_VECTORS && in getNode()
7833 if (N1.getOpcode() == ISD::CONCAT_VECTORS && in getNode()
7984 case ISD::CONCAT_VECTORS: { in getNode()
10605 case ISD::CONCAT_VECTORS: in getNode()
H A DLegalizeDAG.cpp1552 assert(Node->getOpcode() == ISD::CONCAT_VECTORS && "Unexpected opcode!"); in ExpandConcatVectors()
1574 Node->getOpcode() == ISD::CONCAT_VECTORS) && in ExpandVectorBuildThroughStack()
3532 case ISD::CONCAT_VECTORS: in ExpandNode()
5877 DAG.getNode(MidVT == NewEltVT ? ISD::BUILD_VECTOR : ISD::CONCAT_VECTORS, in PromoteNode()
6000 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewElts); in PromoteNode()
H A DSelectionDAGBuilder.cpp403 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS in getCopyFromPartsVector()
4139 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps)); in visitShuffleVector()
4157 Src1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps1); in visitShuffleVector()
4158 Src2 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps2); in visitShuffleVector()
6056 case ISD::CONCAT_VECTORS: in getUnderlyingArgRegs()
12630 SDValue V = DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, InVecs); in visitVectorInterleave()
12644 Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Results); in visitVectorInterleave()
H A DLegalizeIntegerTypes.cpp151 case ISD::CONCAT_VECTORS: in PromoteIntegerResult()
1718 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2); in PromoteIntRes_TRUNCATE()
1972 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break; in PromoteIntegerOperand()
6198 DAG.getNode(ISD::CONCAT_VECTORS, dl, in PromoteIntRes_CONCAT_VECTORS()
H A DTargetLowering.cpp1380 case ISD::CONCAT_VECTORS: { in SimplifyDemandedBits()
3413 case ISD::CONCAT_VECTORS: { in SimplifyDemandedVectorElts()
12299 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, SplitOpLo, SplitOpHi); in expandVectorNaryOpBySplitting()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp179 setOperationAction(ISD::CONCAT_VECTORS, P, Custom); in initializeHVXLowering()
235 setOperationAction(ISD::CONCAT_VECTORS, T, Custom); in initializeHVXLowering()
279 setOperationAction(ISD::CONCAT_VECTORS, T, Custom); in initializeHVXLowering()
398 setOperationAction(ISD::CONCAT_VECTORS, BoolV, Custom); in initializeHVXLowering()
449 setTargetDAGCombine({ISD::CONCAT_VECTORS, ISD::TRUNCATE, ISD::VSELECT}); in initializeHVXLowering()
560 return DAG.getNode(ISD::CONCAT_VECTORS, dl, typeJoin(ty(Ops)), in opJoin()
1406 SDValue InLo = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {SubV, V1}); in insertHvxSubvectorReg()
1407 SDValue InHi = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {V0, SubV}); in insertHvxSubvectorReg()
1453 SDValue InLo = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {SingleV, V1}); in insertHvxSubvectorReg()
1454 SDValue InHi = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {V0, SingleV}); in insertHvxSubvectorReg()
[all …]
H A DHexagonISelLowering.cpp1735 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE, in HexagonTargetLowering()
1789 setOperationAction(ISD::CONCAT_VECTORS, NativeVT, Custom); in HexagonTargetLowering()
2217 return Op.getOpcode() == ISD::CONCAT_VECTORS || in isTargetCanonicalConstantNode()
2479 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, in LowerVECTOR_SHIFT()
2940 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, Concats); in appendUndef()
3386 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); in LowerOperation()
H A DHexagonISelDAGToDAGHVX.cpp1904 LV = DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, {L0, L1}); in scalarizeShuffle()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h571 CONCAT_VECTORS, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp1675 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in X86TargetLowering()
1777 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in X86TargetLowering()
2037 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in X86TargetLowering()
2207 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in X86TargetLowering()
2340 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32f16, Custom); in X86TargetLowering()
2386 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f16, Custom); in X86TargetLowering()
2429 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in X86TargetLowering()
2452 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32bf16, Custom); in X86TargetLowering()
2641 ISD::CONCAT_VECTORS, in X86TargetLowering()
4255 if (N->getOpcode() == ISD::CONCAT_VECTORS) { in collectConcatOps()
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H A DX86ISelLoweringCall.cpp1069 return DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v64i1, Lo, Hi); in getv64i1Argument()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp211 ISD::FP_ROUND, ISD::CONCAT_VECTORS}); in WebAssemblyTargetLowering()
3013 if (N->getOpcode() == ISD::CONCAT_VECTORS) { in performVectorTruncZeroCombine()
3182 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, PackedVT, Lo, Hi); in truncateVectorWithNARROW()
3251 if (Concat.getOpcode() != ISD::CONCAT_VECTORS) in performBitcastCombine()
3489 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, SubVectors); in performMulCombine()
3497 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi); in performMulCombine()
3523 case ISD::CONCAT_VECTORS: in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVECustomDAG.cpp253 case ISD::CONCAT_VECTORS: in getIdiomaticVectorType()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1143 ISD::SIGN_EXTEND_INREG, ISD::CONCAT_VECTORS, in AArch64TargetLowering()
1610 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in AArch64TargetLowering()
1677 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in AArch64TargetLowering()
1753 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in AArch64TargetLowering()
2045 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal); in addTypeForNEON()
2280 setOperationAction(ISD::CONCAT_VECTORS, VT, Default); in addTypeForFixedLengthSVE()
4687 return DAG.getNode(ISD::CONCAT_VECTORS, DL, DstVT, Res, Res2); in LowerVectorFP_TO_INT_SAT()
4724 Sat = DAG.getNode(ISD::CONCAT_VECTORS, DL, in LowerVectorFP_TO_INT_SAT()
4872 Op->user_begin()->getOpcode() == ISD::CONCAT_VECTORS) { in LowerVectorINT_TO_FP()
6706 SDValue TruncExt = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i16, in LowerTruncateVectorStore()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp799 setOperationAction({ISD::TRUNCATE, ISD::CONCAT_VECTORS, in RISCVTargetLowering()
928 setOperationAction({ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR, in RISCVTargetLowering()
1109 setOperationAction({ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR, in RISCVTargetLowering()
1159 setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::CONCAT_VECTORS, in RISCVTargetLowering()
1266 {ISD::BUILD_VECTOR, ISD::CONCAT_VECTORS, ISD::VECTOR_REVERSE}, VT, in RISCVTargetLowering()
1425 ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR, in RISCVTargetLowering()
1652 ISD::SPLAT_VECTOR, ISD::BUILD_VECTOR, ISD::CONCAT_VECTORS, in RISCVTargetLowering()
5727 if (V.getOpcode() == ISD::CONCAT_VECTORS) { in lowerVECTOR_SHUFFLE()
5858 DAG.getNode(ISD::CONCAT_VECTORS, DL, in lowerVECTOR_SHUFFLE()
5901 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, DL, ConcatVT, V1, V2); in lowerVECTOR_SHUFFLE()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp202 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal); in addTypeForNEON()
467 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in addMVEVectorTypes()
8197 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lower, Upper); in LowerBUILD_VECTOR()
8335 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8977 if (ST->hasNEON() && V1->getOpcode() == ISD::CONCAT_VECTORS && V2->isUndef()) { in LowerVECTOR_SHUFFLE()
8995 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Res.getValue(0), in LowerVECTOR_SHUFFLE()
9462 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ToVT, Ext, Ext1); in LowerVectorExtend()
9850 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerSDIV()
9887 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerUDIV()
10682 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG, Subtarget); in LowerOperation()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp356 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in LoongArchTargetLowering()
504 case ISD::CONCAT_VECTORS: in LowerOperation()
2569 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, DL, HalfVT, in lowerCONCAT_VECTORS()
2571 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, DL, HalfVT, in lowerCONCAT_VECTORS()
2573 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); in lowerCONCAT_VECTORS()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp792 setOperationAction({ISD::FGETSIGN, ISD::CONCAT_VECTORS, in initActions()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp342 case ISD::CONCAT_VECTORS: in SITargetLowering()
652 case ISD::CONCAT_VECTORS: in SITargetLowering()
6041 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi); in splitUnaryVectorOp()
6067 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi); in splitBinaryVectorOp()
6097 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi); in splitTernaryVectorOp()
6632 return DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, Pieces); in lowerLaneOp()
7038 return DAG.getNode(ISD::CONCAT_VECTORS, DL, DstVT, OpLo, OpHi); in splitFP_ROUNDVectorOp()
8047 return DAG.getNode(ISD::CONCAT_VECTORS, SL, ResultVT, Pieces); in lowerVECTOR_SHUFFLE()
8945 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Loads); in lowerSBuffer()
H A DAMDGPUISelLowering.cpp451 setOperationAction(ISD::CONCAT_VECTORS, in AMDGPUTargetLowering()
1434 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); in LowerOperation()
1868 Join = DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad); in SplitVectorLoad()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td845 def concat_vectors : SDNode<"ISD::CONCAT_VECTORS",
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2904 case ISD::CONCAT_VECTORS: in LowerOperation()

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