1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 MediaTek Inc. 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/spmi/spmi.h> 8#include "mt8195.dtsi" 9#include "mt6359.dtsi" 10 11/ { 12 aliases { 13 i2c0 = &i2c0; 14 i2c1 = &i2c1; 15 i2c2 = &i2c2; 16 i2c3 = &i2c3; 17 i2c4 = &i2c4; 18 i2c5 = &i2c5; 19 i2c7 = &i2c7; 20 mmc0 = &mmc0; 21 mmc1 = &mmc1; 22 serial0 = &uart0; 23 }; 24 25 backlight_lcd0: backlight-lcd0 { 26 compatible = "pwm-backlight"; 27 brightness-levels = <0 1023>; 28 default-brightness-level = <576>; 29 enable-gpios = <&pio 82 GPIO_ACTIVE_HIGH>; 30 num-interpolated-steps = <1023>; 31 pwms = <&disp_pwm0 0 500000>; 32 power-supply = <&ppvar_sys>; 33 }; 34 35 chosen { 36 stdout-path = "serial0:115200n8"; 37 }; 38 39 dmic-codec { 40 compatible = "dmic-codec"; 41 num-channels = <2>; 42 wakeup-delay-ms = <50>; 43 }; 44 45 memory@40000000 { 46 device_type = "memory"; 47 reg = <0 0x40000000 0 0x80000000>; 48 }; 49 50 pp3300_disp_x: regulator-pp3300-disp-x { 51 compatible = "regulator-fixed"; 52 regulator-name = "pp3300_disp_x"; 53 regulator-min-microvolt = <3300000>; 54 regulator-max-microvolt = <3300000>; 55 regulator-enable-ramp-delay = <2500>; 56 enable-active-high; 57 gpio = <&pio 55 GPIO_ACTIVE_HIGH>; 58 pinctrl-names = "default"; 59 pinctrl-0 = <&panel_fixed_pins>; 60 vin-supply = <&pp3300_z2>; 61 }; 62 63 /* system wide LDO 3.3V power rail */ 64 pp3300_z5: regulator-pp3300-ldo-z5 { 65 compatible = "regulator-fixed"; 66 regulator-name = "pp3300_ldo_z5"; 67 regulator-always-on; 68 regulator-boot-on; 69 regulator-min-microvolt = <3300000>; 70 regulator-max-microvolt = <3300000>; 71 vin-supply = <&ppvar_sys>; 72 }; 73 74 /* separately switched 3.3V power rail */ 75 pp3300_s3: regulator-pp3300-s3 { 76 compatible = "regulator-fixed"; 77 regulator-name = "pp3300_s3"; 78 /* automatically sequenced by PMIC EXT_PMIC_EN2 */ 79 regulator-always-on; 80 regulator-boot-on; 81 regulator-min-microvolt = <3300000>; 82 regulator-max-microvolt = <3300000>; 83 vin-supply = <&pp3300_z2>; 84 }; 85 86 /* system wide 3.3V power rail */ 87 pp3300_z2: regulator-pp3300-z2 { 88 compatible = "regulator-fixed"; 89 regulator-name = "pp3300_z2"; 90 /* EN pin tied to pp4200_z2, which is controlled by EC */ 91 regulator-always-on; 92 regulator-boot-on; 93 regulator-min-microvolt = <3300000>; 94 regulator-max-microvolt = <3300000>; 95 vin-supply = <&ppvar_sys>; 96 }; 97 98 /* system wide 4.2V power rail */ 99 pp4200_z2: regulator-pp4200-z2 { 100 compatible = "regulator-fixed"; 101 regulator-name = "pp4200_z2"; 102 /* controlled by EC */ 103 regulator-always-on; 104 regulator-boot-on; 105 regulator-min-microvolt = <4200000>; 106 regulator-max-microvolt = <4200000>; 107 vin-supply = <&ppvar_sys>; 108 }; 109 110 /* system wide switching 5.0V power rail */ 111 pp5000_s5: regulator-pp5000-s5 { 112 compatible = "regulator-fixed"; 113 regulator-name = "pp5000_s5"; 114 /* controlled by EC */ 115 regulator-always-on; 116 regulator-boot-on; 117 regulator-min-microvolt = <5000000>; 118 regulator-max-microvolt = <5000000>; 119 vin-supply = <&ppvar_sys>; 120 }; 121 122 /* system wide semi-regulated power rail from battery or USB */ 123 ppvar_sys: regulator-ppvar-sys { 124 compatible = "regulator-fixed"; 125 regulator-name = "ppvar_sys"; 126 regulator-always-on; 127 regulator-boot-on; 128 }; 129 130 /* Murata NCP03WF104F05RL */ 131 tboard_thermistor1: thermal-sensor-t1 { 132 compatible = "generic-adc-thermal"; 133 #thermal-sensor-cells = <0>; 134 io-channels = <&auxadc 0>; 135 io-channel-names = "sensor-channel"; 136 temperature-lookup-table = < (-10000) 1553 137 (-5000) 1485 138 0 1406 139 5000 1317 140 10000 1219 141 15000 1115 142 20000 1007 143 25000 900 144 30000 796 145 35000 697 146 40000 605 147 45000 523 148 50000 449 149 55000 384 150 60000 327 151 65000 279 152 70000 237 153 75000 202 154 80000 172 155 85000 147 156 90000 125 157 95000 107 158 100000 92 159 105000 79 160 110000 68 161 115000 59 162 120000 51 163 125000 44>; 164 }; 165 166 tboard_thermistor2: thermal-sensor-t2 { 167 compatible = "generic-adc-thermal"; 168 #thermal-sensor-cells = <0>; 169 io-channels = <&auxadc 1>; 170 io-channel-names = "sensor-channel"; 171 temperature-lookup-table = < (-10000) 1553 172 (-5000) 1485 173 0 1406 174 5000 1317 175 10000 1219 176 15000 1115 177 20000 1007 178 25000 900 179 30000 796 180 35000 697 181 40000 605 182 45000 523 183 50000 449 184 55000 384 185 60000 327 186 65000 279 187 70000 237 188 75000 202 189 80000 172 190 85000 147 191 90000 125 192 95000 107 193 100000 92 194 105000 79 195 110000 68 196 115000 59 197 120000 51 198 125000 44>; 199 }; 200 201 usb_vbus: regulator-5v0-usb-vbus { 202 compatible = "regulator-fixed"; 203 regulator-name = "usb-vbus"; 204 regulator-min-microvolt = <5000000>; 205 regulator-max-microvolt = <5000000>; 206 enable-active-high; 207 regulator-always-on; 208 }; 209 210 reserved_memory: reserved-memory { 211 #address-cells = <2>; 212 #size-cells = <2>; 213 ranges; 214 215 scp_mem: memory@50000000 { 216 compatible = "shared-dma-pool"; 217 reg = <0 0x50000000 0 0x2900000>; 218 no-map; 219 }; 220 221 adsp_mem: memory@60000000 { 222 compatible = "shared-dma-pool"; 223 reg = <0 0x60000000 0 0xd80000>; 224 no-map; 225 }; 226 227 afe_mem: memory@60d80000 { 228 compatible = "shared-dma-pool"; 229 reg = <0 0x60d80000 0 0x100000>; 230 no-map; 231 }; 232 233 adsp_device_mem: memory@60e80000 { 234 compatible = "shared-dma-pool"; 235 reg = <0 0x60e80000 0 0x280000>; 236 no-map; 237 }; 238 }; 239 240 spk_amplifier: rt1019p { 241 compatible = "realtek,rt1019p"; 242 label = "rt1019p"; 243 #sound-dai-cells = <0>; 244 pinctrl-names = "default"; 245 pinctrl-0 = <&rt1019p_pins_default>; 246 sdb-gpios = <&pio 100 GPIO_ACTIVE_HIGH>; 247 }; 248}; 249 250&adsp { 251 status = "okay"; 252 253 memory-region = <&adsp_device_mem>, <&adsp_mem>; 254}; 255 256&afe { 257 status = "okay"; 258 259 mediatek,etdm-in2-cowork-source = <2>; 260 mediatek,etdm-out2-cowork-source = <0>; 261 memory-region = <&afe_mem>; 262}; 263 264&auxadc { 265 status = "okay"; 266}; 267 268&cpu0 { 269 cpu-supply = <&mt6359_vcore_buck_reg>; 270}; 271 272&cpu1 { 273 cpu-supply = <&mt6359_vcore_buck_reg>; 274}; 275 276&cpu2 { 277 cpu-supply = <&mt6359_vcore_buck_reg>; 278}; 279 280&cpu3 { 281 cpu-supply = <&mt6359_vcore_buck_reg>; 282}; 283 284&cpu4 { 285 cpu-supply = <&mt6315_6_vbuck1>; 286}; 287 288&cpu5 { 289 cpu-supply = <&mt6315_6_vbuck1>; 290}; 291 292&cpu6 { 293 cpu-supply = <&mt6315_6_vbuck1>; 294}; 295 296&cpu7 { 297 cpu-supply = <&mt6315_6_vbuck1>; 298}; 299 300&dither0_out { 301 remote-endpoint = <&dsc0_in>; 302}; 303 304&dp_intf0 { 305 status = "okay"; 306 307 ports { 308 #address-cells = <1>; 309 #size-cells = <0>; 310 311 port@0 { 312 reg = <0>; 313 dp_intf0_in: endpoint { 314 remote-endpoint = <&merge0_out>; 315 }; 316 }; 317 318 port@1 { 319 reg = <1>; 320 dp_intf0_out: endpoint { 321 remote-endpoint = <&edp_in>; 322 }; 323 }; 324 }; 325}; 326 327&dp_intf1 { 328 status = "okay"; 329 330 ports { 331 #address-cells = <1>; 332 #size-cells = <0>; 333 334 port@0 { 335 #address-cells = <1>; 336 #size-cells = <0>; 337 reg = <0>; 338 339 dp_intf1_in: endpoint@1 { 340 reg = <1>; 341 remote-endpoint = <&merge5_out>; 342 }; 343 }; 344 345 port@1 { 346 #address-cells = <1>; 347 #size-cells = <0>; 348 reg = <1>; 349 350 dp_intf1_out: endpoint@1 { 351 reg = <1>; 352 remote-endpoint = <&dptx_in>; 353 }; 354 }; 355 }; 356}; 357 358&dsc0 { 359 ports { 360 #address-cells = <1>; 361 #size-cells = <0>; 362 363 port@0 { 364 reg = <0>; 365 dsc0_in: endpoint { 366 remote-endpoint = <&dither0_out>; 367 }; 368 }; 369 370 port@1 { 371 reg = <1>; 372 dsc0_out: endpoint { 373 remote-endpoint = <&merge0_in>; 374 }; 375 }; 376 }; 377}; 378 379&edp_tx { 380 status = "okay"; 381 382 pinctrl-names = "default"; 383 pinctrl-0 = <&edptx_pins_default>; 384 385 ports { 386 #address-cells = <1>; 387 #size-cells = <0>; 388 389 port@0 { 390 reg = <0>; 391 edp_in: endpoint { 392 remote-endpoint = <&dp_intf0_out>; 393 }; 394 }; 395 396 port@1 { 397 reg = <1>; 398 edp_out: endpoint { 399 data-lanes = <0 1 2 3>; 400 remote-endpoint = <&panel_in>; 401 }; 402 }; 403 }; 404 405 aux-bus { 406 panel { 407 compatible = "edp-panel"; 408 power-supply = <&pp3300_disp_x>; 409 backlight = <&backlight_lcd0>; 410 port { 411 panel_in: endpoint { 412 remote-endpoint = <&edp_out>; 413 }; 414 }; 415 }; 416 }; 417}; 418 419ðdr0 { 420 ports { 421 #address-cells = <1>; 422 #size-cells = <0>; 423 424 port@0 { 425 #address-cells = <1>; 426 #size-cells = <0>; 427 reg = <0>; 428 429 ethdr0_in: endpoint@1 { 430 reg = <1>; 431 remote-endpoint = <&vdosys1_ep_ext>; 432 }; 433 }; 434 435 port@1 { 436 #address-cells = <1>; 437 #size-cells = <0>; 438 reg = <1>; 439 440 ethdr0_out: endpoint@1 { 441 reg = <1>; 442 remote-endpoint = <&merge5_in>; 443 }; 444 }; 445 }; 446}; 447 448&disp_pwm0 { 449 status = "okay"; 450 451 pinctrl-names = "default"; 452 pinctrl-0 = <&disp_pwm0_pin_default>; 453}; 454 455&dp_tx { 456 status = "okay"; 457 458 #sound-dai-cells = <0>; 459 pinctrl-names = "default"; 460 pinctrl-0 = <&dptx_pin>; 461 462 ports { 463 #address-cells = <1>; 464 #size-cells = <0>; 465 466 port@0 { 467 #address-cells = <1>; 468 #size-cells = <0>; 469 reg = <0>; 470 471 dptx_in: endpoint@1 { 472 reg = <1>; 473 remote-endpoint = <&dp_intf1_out>; 474 }; 475 }; 476 477 port@1 { 478 reg = <1>; 479 dptx_out: endpoint { 480 data-lanes = <0 1 2 3>; 481 }; 482 }; 483 }; 484}; 485 486&gic { 487 mediatek,broken-save-restore-fw; 488}; 489 490&gpu { 491 status = "okay"; 492 mali-supply = <&mt6315_7_vbuck1>; 493}; 494 495&i2c0 { 496 status = "okay"; 497 498 clock-frequency = <400000>; 499 pinctrl-names = "default"; 500 pinctrl-0 = <&i2c0_pins>; 501}; 502 503&i2c1 { 504 status = "okay"; 505 506 clock-frequency = <400000>; 507 i2c-scl-internal-delay-ns = <12500>; 508 pinctrl-names = "default"; 509 pinctrl-0 = <&i2c1_pins>; 510 511 trackpad@15 { 512 compatible = "elan,ekth3000"; 513 reg = <0x15>; 514 interrupts-extended = <&pio 6 IRQ_TYPE_LEVEL_LOW>; 515 pinctrl-names = "default"; 516 pinctrl-0 = <&trackpad_pins>; 517 vcc-supply = <&pp3300_s3>; 518 wakeup-source; 519 }; 520}; 521 522&i2c2 { 523 status = "okay"; 524 525 clock-frequency = <400000>; 526 pinctrl-names = "default"; 527 pinctrl-0 = <&i2c2_pins>; 528 529 audio_codec: codec@1a { 530 /* Realtek RT5682i or RT5682s, sharing the same configuration */ 531 reg = <0x1a>; 532 interrupts-extended = <&pio 89 IRQ_TYPE_EDGE_BOTH>; 533 #sound-dai-cells = <1>; 534 realtek,jd-src = <1>; 535 536 AVDD-supply = <&mt6359_vio18_ldo_reg>; 537 MICVDD-supply = <&pp3300_z2>; 538 VBAT-supply = <&pp3300_z5>; 539 }; 540}; 541 542&i2c3 { 543 status = "okay"; 544 545 clock-frequency = <400000>; 546 pinctrl-names = "default"; 547 pinctrl-0 = <&i2c3_pins>; 548 549 tpm@50 { 550 compatible = "google,cr50"; 551 reg = <0x50>; 552 interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>; 553 pinctrl-names = "default"; 554 pinctrl-0 = <&cr50_int>; 555 }; 556}; 557 558&i2c4 { 559 status = "okay"; 560 561 clock-frequency = <400000>; 562 pinctrl-names = "default"; 563 pinctrl-0 = <&i2c4_pins>; 564 565 ts_10: touchscreen@10 { 566 compatible = "hid-over-i2c"; 567 reg = <0x10>; 568 hid-descr-addr = <0x0001>; 569 interrupts-extended = <&pio 92 IRQ_TYPE_LEVEL_LOW>; 570 pinctrl-names = "default"; 571 pinctrl-0 = <&touchscreen_pins>; 572 post-power-on-delay-ms = <10>; 573 vdd-supply = <&pp3300_s3>; 574 status = "disabled"; 575 }; 576}; 577 578&i2c5 { 579 status = "okay"; 580 581 clock-frequency = <400000>; 582 pinctrl-names = "default"; 583 pinctrl-0 = <&i2c5_pins>; 584}; 585 586&i2c7 { 587 status = "okay"; 588 589 clock-frequency = <400000>; 590 pinctrl-names = "default"; 591 pinctrl-0 = <&i2c7_pins>; 592 593 pmic@34 { 594 #interrupt-cells = <2>; 595 compatible = "mediatek,mt6360"; 596 reg = <0x34>; 597 interrupt-controller; 598 interrupts-extended = <&pio 130 IRQ_TYPE_EDGE_FALLING>; 599 interrupt-names = "IRQB"; 600 pinctrl-names = "default"; 601 pinctrl-0 = <&subpmic_default>; 602 wakeup-source; 603 }; 604}; 605 606&merge0 { 607 ports { 608 #address-cells = <1>; 609 #size-cells = <0>; 610 611 port@0 { 612 reg = <0>; 613 merge0_in: endpoint { 614 remote-endpoint = <&dsc0_out>; 615 }; 616 }; 617 618 port@1 { 619 reg = <1>; 620 merge0_out: endpoint { 621 remote-endpoint = <&dp_intf0_in>; 622 }; 623 }; 624 }; 625}; 626 627&merge5 { 628 ports { 629 #address-cells = <1>; 630 #size-cells = <0>; 631 632 port@0 { 633 #address-cells = <1>; 634 #size-cells = <0>; 635 reg = <0>; 636 637 merge5_in: endpoint@1 { 638 reg = <1>; 639 remote-endpoint = <ðdr0_out>; 640 }; 641 }; 642 643 port@1 { 644 #address-cells = <1>; 645 #size-cells = <0>; 646 reg = <1>; 647 648 merge5_out: endpoint@1 { 649 reg = <1>; 650 remote-endpoint = <&dp_intf1_in>; 651 }; 652 }; 653 }; 654}; 655 656&mfg0 { 657 domain-supply = <&mt6315_7_vbuck1>; 658}; 659 660&mfg1 { 661 domain-supply = <&mt6359_vsram_others_ldo_reg>; 662}; 663 664&mmc0 { 665 status = "okay"; 666 667 bus-width = <8>; 668 cap-mmc-highspeed; 669 cap-mmc-hw-reset; 670 hs400-ds-delay = <0x14c11>; 671 max-frequency = <200000000>; 672 mmc-hs200-1_8v; 673 mmc-hs400-1_8v; 674 no-sdio; 675 no-sd; 676 non-removable; 677 pinctrl-names = "default", "state_uhs"; 678 pinctrl-0 = <&mmc0_pins_default>; 679 pinctrl-1 = <&mmc0_pins_uhs>; 680 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 681 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 682}; 683 684&mmc1 { 685 status = "okay"; 686 687 bus-width = <4>; 688 cap-sd-highspeed; 689 cd-gpios = <&pio 54 GPIO_ACTIVE_LOW>; 690 max-frequency = <200000000>; 691 no-mmc; 692 no-sdio; 693 pinctrl-names = "default", "state_uhs"; 694 pinctrl-0 = <&mmc1_pins_default>, <&mmc1_pins_detect>; 695 pinctrl-1 = <&mmc1_pins_default>; 696 sd-uhs-sdr50; 697 sd-uhs-sdr104; 698 vmmc-supply = <&mt_pmic_vmch_ldo_reg>; 699 vqmmc-supply = <&mt_pmic_vmc_ldo_reg>; 700}; 701 702&mt6359codec { 703 mediatek,dmic-mode = <1>; /* one-wire */ 704 mediatek,mic-type-0 = <2>; /* DMIC */ 705}; 706 707/* for CPU-L */ 708&mt6359_vcore_buck_reg { 709 regulator-always-on; 710}; 711 712/* for CORE */ 713&mt6359_vgpu11_buck_reg { 714 regulator-always-on; 715}; 716 717&mt6359_vgpu11_sshub_buck_reg { 718 regulator-always-on; 719 regulator-min-microvolt = <550000>; 720 regulator-max-microvolt = <550000>; 721}; 722 723/* for CORE SRAM */ 724&mt6359_vpu_buck_reg { 725 regulator-always-on; 726}; 727 728&mt6359_vrf12_ldo_reg { 729 regulator-always-on; 730}; 731 732/* for GPU SRAM */ 733&mt6359_vsram_others_ldo_reg { 734 regulator-min-microvolt = <750000>; 735 regulator-max-microvolt = <750000>; 736}; 737 738&mt6359_vufs_ldo_reg { 739 regulator-always-on; 740}; 741 742&nor_flash { 743 status = "okay"; 744 745 pinctrl-names = "default"; 746 pinctrl-0 = <&nor_pins_default>; 747 748 flash@0 { 749 compatible = "jedec,spi-nor"; 750 reg = <0>; 751 spi-max-frequency = <52000000>; 752 spi-rx-bus-width = <2>; 753 spi-tx-bus-width = <2>; 754 }; 755}; 756 757&ovl0_in { 758 remote-endpoint = <&vdosys0_ep_main>; 759}; 760 761&pcie1 { 762 status = "okay"; 763 764 pinctrl-names = "default"; 765 pinctrl-0 = <&pcie1_pins_default>; 766}; 767 768&pio { 769 mediatek,rsel-resistance-in-si-unit; 770 pinctrl-names = "default"; 771 pinctrl-0 = <&pio_default>; 772 773 /* 144 lines */ 774 gpio-line-names = 775 "I2S_SPKR_MCLK", 776 "I2S_SPKR_DATAIN", 777 "I2S_SPKR_LRCK", 778 "I2S_SPKR_BCLK", 779 "EC_AP_INT_ODL", 780 /* 781 * AP_FLASH_WP_L is crossystem ABI. Schematics 782 * call it AP_FLASH_WP_ODL. 783 */ 784 "AP_FLASH_WP_L", 785 "TCHPAD_INT_ODL", 786 "EDP_HPD_1V8", 787 "AP_I2C_CAM_SDA", 788 "AP_I2C_CAM_SCL", 789 "AP_I2C_TCHPAD_SDA_1V8", 790 "AP_I2C_TCHPAD_SCL_1V8", 791 "AP_I2C_AUD_SDA", 792 "AP_I2C_AUD_SCL", 793 "AP_I2C_TPM_SDA_1V8", 794 "AP_I2C_TPM_SCL_1V8", 795 "AP_I2C_TCHSCR_SDA_1V8", 796 "AP_I2C_TCHSCR_SCL_1V8", 797 "EC_AP_HPD_OD", 798 "", 799 "PCIE_NVME_RST_L", 800 "PCIE_NVME_CLKREQ_ODL", 801 "PCIE_RST_1V8_L", 802 "PCIE_CLKREQ_1V8_ODL", 803 "PCIE_WAKE_1V8_ODL", 804 "CLK_24M_CAM0", 805 "CAM1_SEN_EN", 806 "AP_I2C_PWR_SCL_1V8", 807 "AP_I2C_PWR_SDA_1V8", 808 "AP_I2C_MISC_SCL", 809 "AP_I2C_MISC_SDA", 810 "EN_PP5000_HDMI_X", 811 "AP_HDMITX_HTPLG", 812 "", 813 "AP_HDMITX_SCL_1V8", 814 "AP_HDMITX_SDA_1V8", 815 "AP_RTC_CLK32K", 816 "AP_EC_WATCHDOG_L", 817 "SRCLKENA0", 818 "SRCLKENA1", 819 "PWRAP_SPI0_CS_L", 820 "PWRAP_SPI0_CK", 821 "PWRAP_SPI0_MOSI", 822 "PWRAP_SPI0_MISO", 823 "SPMI_SCL", 824 "SPMI_SDA", 825 "", 826 "", 827 "", 828 "I2S_HP_DATAIN", 829 "I2S_HP_MCLK", 830 "I2S_HP_BCK", 831 "I2S_HP_LRCK", 832 "I2S_HP_DATAOUT", 833 "SD_CD_ODL", 834 "EN_PP3300_DISP_X", 835 "TCHSCR_RST_1V8_L", 836 "TCHSCR_REPORT_DISABLE", 837 "EN_PP3300_WLAN_X", 838 "BT_KILL_1V8_L", 839 "I2S_SPKR_DATAOUT", 840 "WIFI_KILL_1V8_L", 841 "BEEP_ON", 842 "SCP_I2C_SENSOR_SCL_1V8", 843 "SCP_I2C_SENSOR_SDA_1V8", 844 "", 845 "", 846 "", 847 "", 848 "AUD_CLK_MOSI", 849 "AUD_SYNC_MOSI", 850 "AUD_DAT_MOSI0", 851 "AUD_DAT_MOSI1", 852 "AUD_DAT_MISO0", 853 "AUD_DAT_MISO1", 854 "AUD_DAT_MISO2", 855 "SCP_VREQ_VAO", 856 "AP_SPI_GSC_TPM_CLK", 857 "AP_SPI_GSC_TPM_MOSI", 858 "AP_SPI_GSC_TPM_CS_L", 859 "AP_SPI_GSC_TPM_MISO", 860 "EN_PP1000_CAM_X", 861 "AP_EDP_BKLTEN", 862 "", 863 "USB3_HUB_RST_L", 864 "", 865 "WLAN_ALERT_ODL", 866 "EC_IN_RW_ODL", 867 "GSC_AP_INT_ODL", 868 "HP_INT_ODL", 869 "CAM0_RST_L", 870 "CAM1_RST_L", 871 "TCHSCR_INT_1V8_L", 872 "CAM1_DET_L", 873 "RST_ALC1011_L", 874 "", 875 "", 876 "BL_PWM_1V8", 877 "UART_AP_TX_DBG_RX", 878 "UART_DBG_TX_AP_RX", 879 "EN_SPKR", 880 "AP_EC_WARM_RST_REQ", 881 "UART_SCP_TX_DBGCON_RX", 882 "UART_DBGCON_TX_SCP_RX", 883 "", 884 "", 885 "KPCOL0", 886 "", 887 "MT6315_GPU_INT", 888 "MT6315_PROC_BC_INT", 889 "SD_CMD", 890 "SD_CLK", 891 "SD_DAT0", 892 "SD_DAT1", 893 "SD_DAT2", 894 "SD_DAT3", 895 "EMMC_DAT7", 896 "EMMC_DAT6", 897 "EMMC_DAT5", 898 "EMMC_DAT4", 899 "EMMC_RSTB", 900 "EMMC_CMD", 901 "EMMC_CLK", 902 "EMMC_DAT3", 903 "EMMC_DAT2", 904 "EMMC_DAT1", 905 "EMMC_DAT0", 906 "EMMC_DSL", 907 "", 908 "", 909 "MT6360_INT_ODL", 910 "SCP_JTAG0_TRSTN", 911 "AP_SPI_EC_CS_L", 912 "AP_SPI_EC_CLK", 913 "AP_SPI_EC_MOSI", 914 "AP_SPI_EC_MISO", 915 "SCP_JTAG0_TMS", 916 "SCP_JTAG0_TCK", 917 "SCP_JTAG0_TDO", 918 "SCP_JTAG0_TDI", 919 "AP_SPI_FLASH_CS_L", 920 "AP_SPI_FLASH_CLK", 921 "AP_SPI_FLASH_MOSI", 922 "AP_SPI_FLASH_MISO"; 923 924 aud_pins_default: audio-default-pins { 925 pins-cmd-dat { 926 pinmux = <PINMUX_GPIO69__FUNC_AUD_CLK_MOSI>, 927 <PINMUX_GPIO70__FUNC_AUD_SYNC_MOSI>, 928 <PINMUX_GPIO71__FUNC_AUD_DAT_MOSI0>, 929 <PINMUX_GPIO72__FUNC_AUD_DAT_MOSI1>, 930 <PINMUX_GPIO73__FUNC_AUD_DAT_MISO0>, 931 <PINMUX_GPIO74__FUNC_AUD_DAT_MISO1>, 932 <PINMUX_GPIO75__FUNC_AUD_DAT_MISO2>, 933 <PINMUX_GPIO0__FUNC_TDMIN_MCK>, 934 <PINMUX_GPIO1__FUNC_TDMIN_DI>, 935 <PINMUX_GPIO2__FUNC_TDMIN_LRCK>, 936 <PINMUX_GPIO3__FUNC_TDMIN_BCK>, 937 <PINMUX_GPIO60__FUNC_I2SO2_D0>, 938 <PINMUX_GPIO49__FUNC_I2SIN_D0>, 939 <PINMUX_GPIO50__FUNC_I2SO1_MCK>, 940 <PINMUX_GPIO51__FUNC_I2SO1_BCK>, 941 <PINMUX_GPIO52__FUNC_I2SO1_WS>, 942 <PINMUX_GPIO53__FUNC_I2SO1_D0>; 943 }; 944 945 pins-hp-jack-int-odl { 946 pinmux = <PINMUX_GPIO89__FUNC_GPIO89>; 947 input-enable; 948 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 949 }; 950 }; 951 952 cr50_int: cr50-irq-default-pins { 953 pins-gsc-ap-int-odl { 954 pinmux = <PINMUX_GPIO88__FUNC_GPIO88>; 955 input-enable; 956 }; 957 }; 958 959 cros_ec_int: cros-ec-irq-default-pins { 960 pins-ec-ap-int-odl { 961 pinmux = <PINMUX_GPIO4__FUNC_GPIO4>; 962 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 963 input-enable; 964 }; 965 }; 966 967 edptx_pins_default: edptx-default-pins { 968 pins-cmd-dat { 969 pinmux = <PINMUX_GPIO7__FUNC_EDP_TX_HPD>; 970 bias-pull-up; 971 }; 972 }; 973 974 disp_pwm0_pin_default: disp-pwm0-default-pins { 975 pins-disp-pwm { 976 pinmux = <PINMUX_GPIO82__FUNC_GPIO82>, 977 <PINMUX_GPIO97__FUNC_DISP_PWM0>; 978 }; 979 }; 980 981 dptx_pin: dptx-default-pins { 982 pins-cmd-dat { 983 pinmux = <PINMUX_GPIO18__FUNC_DP_TX_HPD>; 984 bias-pull-up; 985 }; 986 }; 987 988 i2c0_pins: i2c0-default-pins { 989 pins-bus { 990 pinmux = <PINMUX_GPIO8__FUNC_SDA0>, 991 <PINMUX_GPIO9__FUNC_SCL0>; 992 bias-disable; 993 drive-strength-microamp = <1000>; 994 }; 995 }; 996 997 i2c1_pins: i2c1-default-pins { 998 pins-bus { 999 pinmux = <PINMUX_GPIO10__FUNC_SDA1>, 1000 <PINMUX_GPIO11__FUNC_SCL1>; 1001 bias-pull-up = <1000>; 1002 drive-strength-microamp = <1000>; 1003 }; 1004 }; 1005 1006 i2c2_pins: i2c2-default-pins { 1007 pins-bus { 1008 pinmux = <PINMUX_GPIO12__FUNC_SDA2>, 1009 <PINMUX_GPIO13__FUNC_SCL2>; 1010 bias-disable; 1011 drive-strength-microamp = <1000>; 1012 }; 1013 }; 1014 1015 i2c3_pins: i2c3-default-pins { 1016 pins-bus { 1017 pinmux = <PINMUX_GPIO14__FUNC_SDA3>, 1018 <PINMUX_GPIO15__FUNC_SCL3>; 1019 bias-pull-up = <1000>; 1020 drive-strength-microamp = <1000>; 1021 }; 1022 }; 1023 1024 i2c4_pins: i2c4-default-pins { 1025 pins-bus { 1026 pinmux = <PINMUX_GPIO16__FUNC_SDA4>, 1027 <PINMUX_GPIO17__FUNC_SCL4>; 1028 bias-pull-up = <1000>; 1029 drive-strength = <4>; 1030 }; 1031 }; 1032 1033 i2c5_pins: i2c5-default-pins { 1034 pins-bus { 1035 pinmux = <PINMUX_GPIO29__FUNC_SCL5>, 1036 <PINMUX_GPIO30__FUNC_SDA5>; 1037 bias-disable; 1038 drive-strength-microamp = <1000>; 1039 }; 1040 }; 1041 1042 i2c7_pins: i2c7-default-pins { 1043 pins-bus { 1044 pinmux = <PINMUX_GPIO27__FUNC_SCL7>, 1045 <PINMUX_GPIO28__FUNC_SDA7>; 1046 bias-disable; 1047 }; 1048 }; 1049 1050 mmc0_pins_default: mmc0-default-pins { 1051 pins-cmd-dat { 1052 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 1053 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 1054 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 1055 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 1056 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 1057 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 1058 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 1059 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 1060 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 1061 input-enable; 1062 drive-strength = <6>; 1063 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1064 }; 1065 1066 pins-clk { 1067 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 1068 drive-strength = <6>; 1069 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1070 }; 1071 1072 pins-rst { 1073 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 1074 drive-strength = <6>; 1075 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1076 }; 1077 }; 1078 1079 mmc0_pins_uhs: mmc0-uhs-pins { 1080 pins-cmd-dat { 1081 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 1082 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 1083 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 1084 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 1085 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 1086 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 1087 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 1088 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 1089 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 1090 input-enable; 1091 drive-strength = <8>; 1092 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1093 }; 1094 1095 pins-clk { 1096 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 1097 drive-strength = <8>; 1098 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1099 }; 1100 1101 pins-ds { 1102 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; 1103 drive-strength = <8>; 1104 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1105 }; 1106 1107 pins-rst { 1108 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 1109 drive-strength = <8>; 1110 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1111 }; 1112 }; 1113 1114 mmc1_pins_detect: mmc1-detect-pins { 1115 pins-insert { 1116 pinmux = <PINMUX_GPIO54__FUNC_GPIO54>; 1117 bias-pull-up; 1118 }; 1119 }; 1120 1121 mmc1_pins_default: mmc1-default-pins { 1122 pins-cmd-dat { 1123 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>, 1124 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>, 1125 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>, 1126 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, 1127 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; 1128 input-enable; 1129 drive-strength = <8>; 1130 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1131 }; 1132 1133 pins-clk { 1134 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; 1135 drive-strength = <8>; 1136 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1137 }; 1138 }; 1139 1140 nor_pins_default: nor-default-pins { 1141 pins-ck-io { 1142 pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>, 1143 <PINMUX_GPIO141__FUNC_SPINOR_CK>, 1144 <PINMUX_GPIO143__FUNC_SPINOR_IO1>; 1145 drive-strength = <6>; 1146 bias-pull-down; 1147 }; 1148 1149 pins-cs { 1150 pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>; 1151 drive-strength = <6>; 1152 bias-pull-up; 1153 }; 1154 }; 1155 1156 pcie0_pins_default: pcie0-default-pins { 1157 pins-bus { 1158 pinmux = <PINMUX_GPIO19__FUNC_WAKEN>, 1159 <PINMUX_GPIO20__FUNC_PERSTN>, 1160 <PINMUX_GPIO21__FUNC_CLKREQN>; 1161 bias-pull-up; 1162 }; 1163 }; 1164 1165 pcie1_pins_default: pcie1-default-pins { 1166 pins-bus { 1167 pinmux = <PINMUX_GPIO22__FUNC_PERSTN_1>, 1168 <PINMUX_GPIO23__FUNC_CLKREQN_1>, 1169 <PINMUX_GPIO24__FUNC_WAKEN_1>; 1170 bias-pull-up; 1171 }; 1172 }; 1173 1174 panel_fixed_pins: panel-pwr-default-pins { 1175 pins-vreg-en { 1176 pinmux = <PINMUX_GPIO55__FUNC_GPIO55>; 1177 }; 1178 }; 1179 1180 pio_default: pio-default-pins { 1181 pins-wifi-enable { 1182 pinmux = <PINMUX_GPIO58__FUNC_GPIO58>; 1183 output-high; 1184 drive-strength = <14>; 1185 }; 1186 1187 pins-low-power-pd { 1188 pinmux = <PINMUX_GPIO25__FUNC_GPIO25>, 1189 <PINMUX_GPIO26__FUNC_GPIO26>, 1190 <PINMUX_GPIO46__FUNC_GPIO46>, 1191 <PINMUX_GPIO47__FUNC_GPIO47>, 1192 <PINMUX_GPIO48__FUNC_GPIO48>, 1193 <PINMUX_GPIO65__FUNC_GPIO65>, 1194 <PINMUX_GPIO66__FUNC_GPIO66>, 1195 <PINMUX_GPIO67__FUNC_GPIO67>, 1196 <PINMUX_GPIO68__FUNC_GPIO68>, 1197 <PINMUX_GPIO128__FUNC_GPIO128>, 1198 <PINMUX_GPIO129__FUNC_GPIO129>; 1199 input-enable; 1200 bias-pull-down; 1201 }; 1202 1203 pins-low-power-pupd { 1204 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>, 1205 <PINMUX_GPIO78__FUNC_GPIO78>, 1206 <PINMUX_GPIO79__FUNC_GPIO79>, 1207 <PINMUX_GPIO80__FUNC_GPIO80>, 1208 <PINMUX_GPIO83__FUNC_GPIO83>, 1209 <PINMUX_GPIO85__FUNC_GPIO85>, 1210 <PINMUX_GPIO90__FUNC_GPIO90>, 1211 <PINMUX_GPIO91__FUNC_GPIO91>, 1212 <PINMUX_GPIO93__FUNC_GPIO93>, 1213 <PINMUX_GPIO94__FUNC_GPIO94>, 1214 <PINMUX_GPIO95__FUNC_GPIO95>, 1215 <PINMUX_GPIO96__FUNC_GPIO96>, 1216 <PINMUX_GPIO104__FUNC_GPIO104>, 1217 <PINMUX_GPIO105__FUNC_GPIO105>, 1218 <PINMUX_GPIO107__FUNC_GPIO107>; 1219 input-enable; 1220 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 1221 }; 1222 }; 1223 1224 rt1019p_pins_default: rt1019p-default-pins { 1225 pins-amp-sdb { 1226 pinmux = <PINMUX_GPIO100__FUNC_GPIO100>; 1227 output-low; 1228 }; 1229 }; 1230 1231 scp_pins: scp-default-pins { 1232 pins-vreq { 1233 pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>; 1234 bias-disable; 1235 input-enable; 1236 }; 1237 }; 1238 1239 spi0_pins: spi0-default-pins { 1240 pins-cs-mosi-clk { 1241 pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>, 1242 <PINMUX_GPIO134__FUNC_SPIM0_MO>, 1243 <PINMUX_GPIO133__FUNC_SPIM0_CLK>; 1244 bias-disable; 1245 }; 1246 1247 pins-miso { 1248 pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>; 1249 bias-pull-down; 1250 }; 1251 }; 1252 1253 subpmic_default: subpmic-default-pins { 1254 subpmic_pin_irq: pins-subpmic-int-n { 1255 pinmux = <PINMUX_GPIO130__FUNC_GPIO130>; 1256 input-enable; 1257 bias-pull-up; 1258 }; 1259 }; 1260 1261 trackpad_pins: trackpad-default-pins { 1262 pins-int-n { 1263 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; 1264 input-enable; 1265 bias-pull-up; 1266 }; 1267 }; 1268 1269 touchscreen_pins: touchscreen-default-pins { 1270 pins-int-n { 1271 pinmux = <PINMUX_GPIO92__FUNC_GPIO92>; 1272 input-enable; 1273 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1274 }; 1275 pins-rst { 1276 pinmux = <PINMUX_GPIO56__FUNC_GPIO56>; 1277 output-high; 1278 }; 1279 pins-report-sw { 1280 pinmux = <PINMUX_GPIO57__FUNC_GPIO57>; 1281 output-low; 1282 }; 1283 }; 1284}; 1285 1286&pmic { 1287 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; 1288}; 1289 1290&scp { 1291 status = "okay"; 1292 1293 firmware-name = "mediatek/mt8195/scp.img"; 1294 memory-region = <&scp_mem>; 1295 pinctrl-names = "default"; 1296 pinctrl-0 = <&scp_pins>; 1297 1298 cros-ec-rpmsg { 1299 compatible = "google,cros-ec-rpmsg"; 1300 mediatek,rpmsg-name = "cros-ec-rpmsg"; 1301 }; 1302}; 1303 1304&sound { 1305 status = "okay"; 1306 1307 mediatek,adsp = <&adsp>; 1308 mediatek,dai-link = 1309 "DL10_FE", "DPTX_BE", "ETDM1_IN_BE", "ETDM2_IN_BE", 1310 "ETDM1_OUT_BE", "ETDM2_OUT_BE","UL_SRC1_BE", 1311 "AFE_SOF_DL2", "AFE_SOF_DL3", "AFE_SOF_UL4", "AFE_SOF_UL5"; 1312 pinctrl-names = "default"; 1313 pinctrl-0 = <&aud_pins_default>; 1314 1315 audio-routing = 1316 "Headphone", "HPOL", 1317 "Headphone", "HPOR", 1318 "IN1P", "Headset Mic", 1319 "Ext Spk", "Speaker"; 1320 1321 mm-dai-link { 1322 link-name = "ETDM1_IN_BE"; 1323 mediatek,clk-provider = "cpu"; 1324 }; 1325 1326 hs-playback-dai-link { 1327 link-name = "ETDM1_OUT_BE"; 1328 mediatek,clk-provider = "cpu"; 1329 codec { 1330 sound-dai = <&audio_codec 0>; 1331 }; 1332 }; 1333 1334 hs-capture-dai-link { 1335 link-name = "ETDM2_IN_BE"; 1336 mediatek,clk-provider = "cpu"; 1337 codec { 1338 sound-dai = <&audio_codec 0>; 1339 }; 1340 }; 1341 1342 spk-playback-dai-link { 1343 link-name = "ETDM2_OUT_BE"; 1344 mediatek,clk-provider = "cpu"; 1345 codec { 1346 sound-dai = <&spk_amplifier>; 1347 }; 1348 }; 1349 1350 displayport-dai-link { 1351 link-name = "DPTX_BE"; 1352 codec { 1353 sound-dai = <&dp_tx>; 1354 }; 1355 }; 1356}; 1357 1358&spi0 { 1359 status = "okay"; 1360 1361 pinctrl-names = "default"; 1362 pinctrl-0 = <&spi0_pins>; 1363 mediatek,pad-select = <0>; 1364 1365 cros_ec: ec@0 { 1366 #address-cells = <1>; 1367 #size-cells = <0>; 1368 1369 compatible = "google,cros-ec-spi"; 1370 reg = <0>; 1371 interrupts-extended = <&pio 4 IRQ_TYPE_LEVEL_LOW>; 1372 pinctrl-names = "default"; 1373 pinctrl-0 = <&cros_ec_int>; 1374 spi-max-frequency = <3000000>; 1375 wakeup-source; 1376 1377 i2c_tunnel: i2c-tunnel { 1378 compatible = "google,cros-ec-i2c-tunnel"; 1379 google,remote-bus = <0>; 1380 #address-cells = <1>; 1381 #size-cells = <0>; 1382 }; 1383 1384 mt_pmic_vmc_ldo_reg: regulator@0 { 1385 compatible = "google,cros-ec-regulator"; 1386 reg = <0>; 1387 regulator-name = "mt_pmic_vmc_ldo"; 1388 regulator-min-microvolt = <1200000>; 1389 regulator-max-microvolt = <3600000>; 1390 }; 1391 1392 mt_pmic_vmch_ldo_reg: regulator@1 { 1393 compatible = "google,cros-ec-regulator"; 1394 reg = <1>; 1395 regulator-name = "mt_pmic_vmch_ldo"; 1396 regulator-min-microvolt = <2700000>; 1397 regulator-max-microvolt = <3600000>; 1398 }; 1399 1400 typec { 1401 compatible = "google,cros-ec-typec"; 1402 #address-cells = <1>; 1403 #size-cells = <0>; 1404 1405 usb_c0: connector@0 { 1406 compatible = "usb-c-connector"; 1407 reg = <0>; 1408 power-role = "dual"; 1409 data-role = "host"; 1410 try-power-role = "source"; 1411 }; 1412 1413 usb_c1: connector@1 { 1414 compatible = "usb-c-connector"; 1415 reg = <1>; 1416 power-role = "dual"; 1417 data-role = "host"; 1418 try-power-role = "source"; 1419 }; 1420 }; 1421 }; 1422}; 1423 1424&spmi { 1425 #address-cells = <2>; 1426 #size-cells = <0>; 1427 1428 mt6315@6 { 1429 compatible = "mediatek,mt6315-regulator"; 1430 reg = <0x6 SPMI_USID>; 1431 1432 regulators { 1433 mt6315_6_vbuck1: vbuck1 { 1434 regulator-name = "Vbcpu"; 1435 regulator-min-microvolt = <400000>; 1436 regulator-max-microvolt = <1193750>; 1437 regulator-enable-ramp-delay = <256>; 1438 regulator-ramp-delay = <6250>; 1439 regulator-allowed-modes = <0 1 2>; 1440 regulator-always-on; 1441 }; 1442 }; 1443 }; 1444 1445 mt6315@7 { 1446 compatible = "mediatek,mt6315-regulator"; 1447 reg = <0x7 SPMI_USID>; 1448 1449 regulators { 1450 mt6315_7_vbuck1: vbuck1 { 1451 regulator-name = "Vgpu"; 1452 regulator-min-microvolt = <400000>; 1453 regulator-max-microvolt = <1193750>; 1454 regulator-enable-ramp-delay = <256>; 1455 regulator-ramp-delay = <6250>; 1456 regulator-allowed-modes = <0 1 2>; 1457 }; 1458 }; 1459 }; 1460}; 1461 1462&thermal_zones { 1463 soc-area-thermal { 1464 polling-delay = <1000>; 1465 polling-delay-passive = <250>; 1466 thermal-sensors = <&tboard_thermistor1>; 1467 1468 trips { 1469 trip-crit { 1470 temperature = <84000>; 1471 hysteresis = <1000>; 1472 type = "critical"; 1473 }; 1474 }; 1475 }; 1476 1477 pmic-area-thermal { 1478 polling-delay = <1000>; 1479 polling-delay-passive = <0>; 1480 thermal-sensors = <&tboard_thermistor2>; 1481 1482 trips { 1483 trip-crit { 1484 temperature = <84000>; 1485 hysteresis = <1000>; 1486 type = "critical"; 1487 }; 1488 }; 1489 }; 1490}; 1491 1492&u3phy0 { 1493 status = "okay"; 1494}; 1495 1496&u3phy1 { 1497 status = "okay"; 1498}; 1499 1500&u3phy2 { 1501 status = "okay"; 1502}; 1503 1504&u3phy3 { 1505 status = "okay"; 1506}; 1507 1508&uart0 { 1509 status = "okay"; 1510}; 1511 1512&vdosys0 { 1513 port { 1514 #address-cells = <1>; 1515 #size-cells = <0>; 1516 1517 vdosys0_ep_main: endpoint@0 { 1518 reg = <0>; 1519 remote-endpoint = <&ovl0_in>; 1520 }; 1521 }; 1522}; 1523 1524/* 1525 * For the USB Type-C ports the role and alternate modes switching is 1526 * done by the EC so we set dr_mode to host to avoid interfering. 1527 */ 1528&ssusb0 { 1529 dr_mode = "host"; 1530 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1531 status = "okay"; 1532}; 1533 1534&ssusb2 { 1535 dr_mode = "host"; 1536 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1537 status = "okay"; 1538}; 1539 1540&ssusb3 { 1541 dr_mode = "host"; 1542 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1543 status = "okay"; 1544}; 1545 1546&vdosys1 { 1547 port { 1548 #address-cells = <1>; 1549 #size-cells = <0>; 1550 1551 vdosys1_ep_ext: endpoint@1 { 1552 reg = <1>; 1553 remote-endpoint = <ðdr0_in>; 1554 }; 1555 }; 1556}; 1557 1558&xhci0 { 1559 status = "okay"; 1560 1561 rx-fifo-depth = <3072>; 1562 vbus-supply = <&usb_vbus>; 1563}; 1564 1565&xhci1 { 1566 status = "okay"; 1567 1568 phys = <&u2port1 PHY_TYPE_USB2>; 1569 rx-fifo-depth = <3072>; 1570 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1571 vbus-supply = <&usb_vbus>; 1572 mediatek,u3p-dis-msk = <1>; 1573}; 1574 1575&xhci2 { 1576 status = "okay"; 1577 vbus-supply = <&usb_vbus>; 1578}; 1579 1580&xhci3 { 1581 status = "okay"; 1582 1583 /* MT7921's USB Bluetooth has issues with USB2 LPM */ 1584 usb2-lpm-disable; 1585 vbus-supply = <&usb_vbus>; 1586}; 1587 1588#include <arm/cros-ec-keyboard.dtsi> 1589#include <arm/cros-ec-sbs.dtsi> 1590 1591&keyboard_controller { 1592 function-row-physmap = < 1593 MATRIX_KEY(0x00, 0x02, 0) /* T1 */ 1594 MATRIX_KEY(0x03, 0x02, 0) /* T2 */ 1595 MATRIX_KEY(0x02, 0x02, 0) /* T3 */ 1596 MATRIX_KEY(0x01, 0x02, 0) /* T4 */ 1597 MATRIX_KEY(0x03, 0x04, 0) /* T5 */ 1598 MATRIX_KEY(0x02, 0x04, 0) /* T6 */ 1599 MATRIX_KEY(0x01, 0x04, 0) /* T7 */ 1600 MATRIX_KEY(0x02, 0x09, 0) /* T8 */ 1601 MATRIX_KEY(0x01, 0x09, 0) /* T9 */ 1602 MATRIX_KEY(0x00, 0x04, 0) /* T10 */ 1603 1604 /* T11 to T13 are present only on Dojo */ 1605 MATRIX_KEY(0x00, 0x01, 0) /* T11 */ 1606 MATRIX_KEY(0x01, 0x05, 0) /* T12 */ 1607 MATRIX_KEY(0x03, 0x05, 0) /* T13 */ 1608 >; 1609 1610 linux,keymap = < 1611 MATRIX_KEY(0x00, 0x02, KEY_BACK) 1612 MATRIX_KEY(0x03, 0x02, KEY_REFRESH) 1613 MATRIX_KEY(0x02, 0x02, KEY_ZOOM) 1614 MATRIX_KEY(0x01, 0x02, KEY_SCALE) 1615 MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) 1616 MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) 1617 MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) 1618 MATRIX_KEY(0x02, 0x09, KEY_MUTE) 1619 MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) 1620 MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) 1621 1622 CROS_STD_MAIN_KEYMAP 1623 >; 1624}; 1625