1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012-2015 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7 #ifndef __ARM64_KVM_HYP_SYSREG_SR_H__
8 #define __ARM64_KVM_HYP_SYSREG_SR_H__
9
10 #include <linux/compiler.h>
11 #include <linux/kvm_host.h>
12
13 #include <asm/kprobes.h>
14 #include <asm/kvm_asm.h>
15 #include <asm/kvm_emulate.h>
16 #include <asm/kvm_hyp.h>
17 #include <asm/kvm_mmu.h>
18
19 static inline bool ctxt_has_s1poe(struct kvm_cpu_context *ctxt);
20
ctxt_to_vcpu(struct kvm_cpu_context * ctxt)21 static inline struct kvm_vcpu *ctxt_to_vcpu(struct kvm_cpu_context *ctxt)
22 {
23 struct kvm_vcpu *vcpu = ctxt->__hyp_running_vcpu;
24
25 if (!vcpu)
26 vcpu = container_of(ctxt, struct kvm_vcpu, arch.ctxt);
27
28 return vcpu;
29 }
30
ctxt_is_guest(struct kvm_cpu_context * ctxt)31 static inline bool ctxt_is_guest(struct kvm_cpu_context *ctxt)
32 {
33 return host_data_ptr(host_ctxt) != ctxt;
34 }
35
ctxt_mdscr_el1(struct kvm_cpu_context * ctxt)36 static inline u64 *ctxt_mdscr_el1(struct kvm_cpu_context *ctxt)
37 {
38 struct kvm_vcpu *vcpu = ctxt_to_vcpu(ctxt);
39
40 if (ctxt_is_guest(ctxt) && kvm_host_owns_debug_regs(vcpu))
41 return &vcpu->arch.external_mdscr_el1;
42
43 return &ctxt_sys_reg(ctxt, MDSCR_EL1);
44 }
45
ctxt_midr_el1(struct kvm_cpu_context * ctxt)46 static inline u64 ctxt_midr_el1(struct kvm_cpu_context *ctxt)
47 {
48 struct kvm *kvm = kern_hyp_va(ctxt_to_vcpu(ctxt)->kvm);
49
50 if (!(ctxt_is_guest(ctxt) &&
51 test_bit(KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS, &kvm->arch.flags)))
52 return read_cpuid_id();
53
54 return kvm_read_vm_id_reg(kvm, SYS_MIDR_EL1);
55 }
56
__sysreg_save_common_state(struct kvm_cpu_context * ctxt)57 static inline void __sysreg_save_common_state(struct kvm_cpu_context *ctxt)
58 {
59 *ctxt_mdscr_el1(ctxt) = read_sysreg(mdscr_el1);
60
61 // POR_EL0 can affect uaccess, so must be saved/restored early.
62 if (ctxt_has_s1poe(ctxt))
63 ctxt_sys_reg(ctxt, POR_EL0) = read_sysreg_s(SYS_POR_EL0);
64 }
65
__sysreg_save_user_state(struct kvm_cpu_context * ctxt)66 static inline void __sysreg_save_user_state(struct kvm_cpu_context *ctxt)
67 {
68 ctxt_sys_reg(ctxt, TPIDR_EL0) = read_sysreg(tpidr_el0);
69 ctxt_sys_reg(ctxt, TPIDRRO_EL0) = read_sysreg(tpidrro_el0);
70 }
71
ctxt_has_mte(struct kvm_cpu_context * ctxt)72 static inline bool ctxt_has_mte(struct kvm_cpu_context *ctxt)
73 {
74 struct kvm_vcpu *vcpu = ctxt_to_vcpu(ctxt);
75
76 return kvm_has_mte(kern_hyp_va(vcpu->kvm));
77 }
78
ctxt_has_s1pie(struct kvm_cpu_context * ctxt)79 static inline bool ctxt_has_s1pie(struct kvm_cpu_context *ctxt)
80 {
81 struct kvm_vcpu *vcpu;
82
83 if (!cpus_have_final_cap(ARM64_HAS_S1PIE))
84 return false;
85
86 vcpu = ctxt_to_vcpu(ctxt);
87 return kvm_has_s1pie(kern_hyp_va(vcpu->kvm));
88 }
89
ctxt_has_tcrx(struct kvm_cpu_context * ctxt)90 static inline bool ctxt_has_tcrx(struct kvm_cpu_context *ctxt)
91 {
92 struct kvm_vcpu *vcpu;
93
94 if (!cpus_have_final_cap(ARM64_HAS_TCR2))
95 return false;
96
97 vcpu = ctxt_to_vcpu(ctxt);
98 return kvm_has_tcr2(kern_hyp_va(vcpu->kvm));
99 }
100
ctxt_has_s1poe(struct kvm_cpu_context * ctxt)101 static inline bool ctxt_has_s1poe(struct kvm_cpu_context *ctxt)
102 {
103 struct kvm_vcpu *vcpu;
104
105 if (!system_supports_poe())
106 return false;
107
108 vcpu = ctxt_to_vcpu(ctxt);
109 return kvm_has_s1poe(kern_hyp_va(vcpu->kvm));
110 }
111
ctxt_has_ras(struct kvm_cpu_context * ctxt)112 static inline bool ctxt_has_ras(struct kvm_cpu_context *ctxt)
113 {
114 struct kvm_vcpu *vcpu;
115
116 if (!cpus_have_final_cap(ARM64_HAS_RAS_EXTN))
117 return false;
118
119 vcpu = ctxt_to_vcpu(ctxt);
120 return kvm_has_ras(kern_hyp_va(vcpu->kvm));
121 }
122
ctxt_has_sctlr2(struct kvm_cpu_context * ctxt)123 static inline bool ctxt_has_sctlr2(struct kvm_cpu_context *ctxt)
124 {
125 struct kvm_vcpu *vcpu;
126
127 if (!cpus_have_final_cap(ARM64_HAS_SCTLR2))
128 return false;
129
130 vcpu = ctxt_to_vcpu(ctxt);
131 return kvm_has_sctlr2(kern_hyp_va(vcpu->kvm));
132 }
133
__sysreg_save_el1_state(struct kvm_cpu_context * ctxt)134 static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt)
135 {
136 ctxt_sys_reg(ctxt, SCTLR_EL1) = read_sysreg_el1(SYS_SCTLR);
137 ctxt_sys_reg(ctxt, CPACR_EL1) = read_sysreg_el1(SYS_CPACR);
138 ctxt_sys_reg(ctxt, TTBR0_EL1) = read_sysreg_el1(SYS_TTBR0);
139 ctxt_sys_reg(ctxt, TTBR1_EL1) = read_sysreg_el1(SYS_TTBR1);
140 ctxt_sys_reg(ctxt, TCR_EL1) = read_sysreg_el1(SYS_TCR);
141 if (ctxt_has_tcrx(ctxt)) {
142 ctxt_sys_reg(ctxt, TCR2_EL1) = read_sysreg_el1(SYS_TCR2);
143
144 if (ctxt_has_s1pie(ctxt)) {
145 ctxt_sys_reg(ctxt, PIR_EL1) = read_sysreg_el1(SYS_PIR);
146 ctxt_sys_reg(ctxt, PIRE0_EL1) = read_sysreg_el1(SYS_PIRE0);
147 }
148
149 if (ctxt_has_s1poe(ctxt))
150 ctxt_sys_reg(ctxt, POR_EL1) = read_sysreg_el1(SYS_POR);
151 }
152 ctxt_sys_reg(ctxt, ESR_EL1) = read_sysreg_el1(SYS_ESR);
153 ctxt_sys_reg(ctxt, AFSR0_EL1) = read_sysreg_el1(SYS_AFSR0);
154 ctxt_sys_reg(ctxt, AFSR1_EL1) = read_sysreg_el1(SYS_AFSR1);
155 ctxt_sys_reg(ctxt, FAR_EL1) = read_sysreg_el1(SYS_FAR);
156 ctxt_sys_reg(ctxt, MAIR_EL1) = read_sysreg_el1(SYS_MAIR);
157 ctxt_sys_reg(ctxt, VBAR_EL1) = read_sysreg_el1(SYS_VBAR);
158 ctxt_sys_reg(ctxt, CONTEXTIDR_EL1) = read_sysreg_el1(SYS_CONTEXTIDR);
159 ctxt_sys_reg(ctxt, AMAIR_EL1) = read_sysreg_el1(SYS_AMAIR);
160 ctxt_sys_reg(ctxt, CNTKCTL_EL1) = read_sysreg_el1(SYS_CNTKCTL);
161 ctxt_sys_reg(ctxt, PAR_EL1) = read_sysreg_par();
162 ctxt_sys_reg(ctxt, TPIDR_EL1) = read_sysreg(tpidr_el1);
163
164 if (ctxt_has_mte(ctxt)) {
165 ctxt_sys_reg(ctxt, TFSR_EL1) = read_sysreg_el1(SYS_TFSR);
166 ctxt_sys_reg(ctxt, TFSRE0_EL1) = read_sysreg_s(SYS_TFSRE0_EL1);
167 }
168
169 ctxt_sys_reg(ctxt, SP_EL1) = read_sysreg(sp_el1);
170 ctxt_sys_reg(ctxt, ELR_EL1) = read_sysreg_el1(SYS_ELR);
171 ctxt_sys_reg(ctxt, SPSR_EL1) = read_sysreg_el1(SYS_SPSR);
172
173 if (ctxt_has_sctlr2(ctxt))
174 ctxt_sys_reg(ctxt, SCTLR2_EL1) = read_sysreg_el1(SYS_SCTLR2);
175 }
176
__sysreg_save_el2_return_state(struct kvm_cpu_context * ctxt)177 static inline void __sysreg_save_el2_return_state(struct kvm_cpu_context *ctxt)
178 {
179 ctxt->regs.pc = read_sysreg_el2(SYS_ELR);
180 /*
181 * Guest PSTATE gets saved at guest fixup time in all
182 * cases. We still need to handle the nVHE host side here.
183 */
184 if (!has_vhe() && ctxt->__hyp_running_vcpu)
185 ctxt->regs.pstate = read_sysreg_el2(SYS_SPSR);
186
187 if (!cpus_have_final_cap(ARM64_HAS_RAS_EXTN))
188 return;
189
190 if (!vserror_state_is_nested(ctxt_to_vcpu(ctxt)))
191 ctxt_sys_reg(ctxt, DISR_EL1) = read_sysreg_s(SYS_VDISR_EL2);
192 else if (ctxt_has_ras(ctxt))
193 ctxt_sys_reg(ctxt, VDISR_EL2) = read_sysreg_s(SYS_VDISR_EL2);
194 }
195
__sysreg_restore_common_state(struct kvm_cpu_context * ctxt)196 static inline void __sysreg_restore_common_state(struct kvm_cpu_context *ctxt)
197 {
198 write_sysreg(*ctxt_mdscr_el1(ctxt), mdscr_el1);
199
200 // POR_EL0 can affect uaccess, so must be saved/restored early.
201 if (ctxt_has_s1poe(ctxt))
202 write_sysreg_s(ctxt_sys_reg(ctxt, POR_EL0), SYS_POR_EL0);
203 }
204
__sysreg_restore_user_state(struct kvm_cpu_context * ctxt)205 static inline void __sysreg_restore_user_state(struct kvm_cpu_context *ctxt)
206 {
207 write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL0), tpidr_el0);
208 write_sysreg(ctxt_sys_reg(ctxt, TPIDRRO_EL0), tpidrro_el0);
209 }
210
__sysreg_restore_el1_state(struct kvm_cpu_context * ctxt,u64 midr,u64 mpidr)211 static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt,
212 u64 midr, u64 mpidr)
213 {
214 write_sysreg(midr, vpidr_el2);
215 write_sysreg(mpidr, vmpidr_el2);
216
217 if (has_vhe() ||
218 !cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) {
219 write_sysreg_el1(ctxt_sys_reg(ctxt, SCTLR_EL1), SYS_SCTLR);
220 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR);
221 } else if (!ctxt->__hyp_running_vcpu) {
222 /*
223 * Must only be done for guest registers, hence the context
224 * test. We're coming from the host, so SCTLR.M is already
225 * set. Pairs with nVHE's __activate_traps().
226 */
227 write_sysreg_el1((ctxt_sys_reg(ctxt, TCR_EL1) |
228 TCR_EPD1_MASK | TCR_EPD0_MASK),
229 SYS_TCR);
230 isb();
231 }
232
233 write_sysreg_el1(ctxt_sys_reg(ctxt, CPACR_EL1), SYS_CPACR);
234 write_sysreg_el1(ctxt_sys_reg(ctxt, TTBR0_EL1), SYS_TTBR0);
235 write_sysreg_el1(ctxt_sys_reg(ctxt, TTBR1_EL1), SYS_TTBR1);
236 if (ctxt_has_tcrx(ctxt)) {
237 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR2_EL1), SYS_TCR2);
238
239 if (ctxt_has_s1pie(ctxt)) {
240 write_sysreg_el1(ctxt_sys_reg(ctxt, PIR_EL1), SYS_PIR);
241 write_sysreg_el1(ctxt_sys_reg(ctxt, PIRE0_EL1), SYS_PIRE0);
242 }
243
244 if (ctxt_has_s1poe(ctxt))
245 write_sysreg_el1(ctxt_sys_reg(ctxt, POR_EL1), SYS_POR);
246 }
247 write_sysreg_el1(ctxt_sys_reg(ctxt, ESR_EL1), SYS_ESR);
248 write_sysreg_el1(ctxt_sys_reg(ctxt, AFSR0_EL1), SYS_AFSR0);
249 write_sysreg_el1(ctxt_sys_reg(ctxt, AFSR1_EL1), SYS_AFSR1);
250 write_sysreg_el1(ctxt_sys_reg(ctxt, FAR_EL1), SYS_FAR);
251 write_sysreg_el1(ctxt_sys_reg(ctxt, MAIR_EL1), SYS_MAIR);
252 write_sysreg_el1(ctxt_sys_reg(ctxt, VBAR_EL1), SYS_VBAR);
253 write_sysreg_el1(ctxt_sys_reg(ctxt, CONTEXTIDR_EL1), SYS_CONTEXTIDR);
254 write_sysreg_el1(ctxt_sys_reg(ctxt, AMAIR_EL1), SYS_AMAIR);
255 write_sysreg_el1(ctxt_sys_reg(ctxt, CNTKCTL_EL1), SYS_CNTKCTL);
256 write_sysreg(ctxt_sys_reg(ctxt, PAR_EL1), par_el1);
257 write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL1), tpidr_el1);
258
259 if (ctxt_has_mte(ctxt)) {
260 write_sysreg_el1(ctxt_sys_reg(ctxt, TFSR_EL1), SYS_TFSR);
261 write_sysreg_s(ctxt_sys_reg(ctxt, TFSRE0_EL1), SYS_TFSRE0_EL1);
262 }
263
264 if (!has_vhe() &&
265 cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT) &&
266 ctxt->__hyp_running_vcpu) {
267 /*
268 * Must only be done for host registers, hence the context
269 * test. Pairs with nVHE's __deactivate_traps().
270 */
271 isb();
272 /*
273 * At this stage, and thanks to the above isb(), S2 is
274 * deconfigured and disabled. We can now restore the host's
275 * S1 configuration: SCTLR, and only then TCR.
276 */
277 write_sysreg_el1(ctxt_sys_reg(ctxt, SCTLR_EL1), SYS_SCTLR);
278 isb();
279 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR);
280 }
281
282 write_sysreg(ctxt_sys_reg(ctxt, SP_EL1), sp_el1);
283 write_sysreg_el1(ctxt_sys_reg(ctxt, ELR_EL1), SYS_ELR);
284 write_sysreg_el1(ctxt_sys_reg(ctxt, SPSR_EL1), SYS_SPSR);
285
286 if (ctxt_has_sctlr2(ctxt))
287 write_sysreg_el1(ctxt_sys_reg(ctxt, SCTLR2_EL1), SYS_SCTLR2);
288 }
289
290 /* Read the VCPU state's PSTATE, but translate (v)EL2 to EL1. */
to_hw_pstate(const struct kvm_cpu_context * ctxt)291 static inline u64 to_hw_pstate(const struct kvm_cpu_context *ctxt)
292 {
293 u64 mode = ctxt->regs.pstate & (PSR_MODE_MASK | PSR_MODE32_BIT);
294
295 switch (mode) {
296 case PSR_MODE_EL2t:
297 mode = PSR_MODE_EL1t;
298 break;
299 case PSR_MODE_EL2h:
300 mode = PSR_MODE_EL1h;
301 break;
302 }
303
304 return (ctxt->regs.pstate & ~(PSR_MODE_MASK | PSR_MODE32_BIT)) | mode;
305 }
306
__sysreg_restore_el2_return_state(struct kvm_cpu_context * ctxt)307 static inline void __sysreg_restore_el2_return_state(struct kvm_cpu_context *ctxt)
308 {
309 u64 pstate = to_hw_pstate(ctxt);
310 u64 mode = pstate & PSR_AA32_MODE_MASK;
311 u64 vdisr;
312
313 /*
314 * Safety check to ensure we're setting the CPU up to enter the guest
315 * in a less privileged mode.
316 *
317 * If we are attempting a return to EL2 or higher in AArch64 state,
318 * program SPSR_EL2 with M=EL2h and the IL bit set which ensures that
319 * we'll take an illegal exception state exception immediately after
320 * the ERET to the guest. Attempts to return to AArch32 Hyp will
321 * result in an illegal exception return because EL2's execution state
322 * is determined by SCR_EL3.RW.
323 */
324 if (!(mode & PSR_MODE32_BIT) && mode >= PSR_MODE_EL2t)
325 pstate = PSR_MODE_EL2h | PSR_IL_BIT;
326
327 write_sysreg_el2(ctxt->regs.pc, SYS_ELR);
328 write_sysreg_el2(pstate, SYS_SPSR);
329
330 if (!cpus_have_final_cap(ARM64_HAS_RAS_EXTN))
331 return;
332
333 if (!vserror_state_is_nested(ctxt_to_vcpu(ctxt)))
334 vdisr = ctxt_sys_reg(ctxt, DISR_EL1);
335 else if (ctxt_has_ras(ctxt))
336 vdisr = ctxt_sys_reg(ctxt, VDISR_EL2);
337 else
338 vdisr = 0;
339
340 write_sysreg_s(vdisr, SYS_VDISR_EL2);
341 }
342
__sysreg32_save_state(struct kvm_vcpu * vcpu)343 static inline void __sysreg32_save_state(struct kvm_vcpu *vcpu)
344 {
345 if (!vcpu_el1_is_32bit(vcpu))
346 return;
347
348 vcpu->arch.ctxt.spsr_abt = read_sysreg(spsr_abt);
349 vcpu->arch.ctxt.spsr_und = read_sysreg(spsr_und);
350 vcpu->arch.ctxt.spsr_irq = read_sysreg(spsr_irq);
351 vcpu->arch.ctxt.spsr_fiq = read_sysreg(spsr_fiq);
352
353 __vcpu_assign_sys_reg(vcpu, DACR32_EL2, read_sysreg(dacr32_el2));
354 __vcpu_assign_sys_reg(vcpu, IFSR32_EL2, read_sysreg(ifsr32_el2));
355
356 if (has_vhe() || kvm_debug_regs_in_use(vcpu))
357 __vcpu_assign_sys_reg(vcpu, DBGVCR32_EL2, read_sysreg(dbgvcr32_el2));
358 }
359
__sysreg32_restore_state(struct kvm_vcpu * vcpu)360 static inline void __sysreg32_restore_state(struct kvm_vcpu *vcpu)
361 {
362 if (!vcpu_el1_is_32bit(vcpu))
363 return;
364
365 write_sysreg(vcpu->arch.ctxt.spsr_abt, spsr_abt);
366 write_sysreg(vcpu->arch.ctxt.spsr_und, spsr_und);
367 write_sysreg(vcpu->arch.ctxt.spsr_irq, spsr_irq);
368 write_sysreg(vcpu->arch.ctxt.spsr_fiq, spsr_fiq);
369
370 write_sysreg(__vcpu_sys_reg(vcpu, DACR32_EL2), dacr32_el2);
371 write_sysreg(__vcpu_sys_reg(vcpu, IFSR32_EL2), ifsr32_el2);
372
373 if (has_vhe() || kvm_debug_regs_in_use(vcpu))
374 write_sysreg(__vcpu_sys_reg(vcpu, DBGVCR32_EL2), dbgvcr32_el2);
375 }
376
377 #endif /* __ARM64_KVM_HYP_SYSREG_SR_H__ */
378