1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7 #ifndef __ARM64_KVM_HYP_SWITCH_H__
8 #define __ARM64_KVM_HYP_SWITCH_H__
9
10 #include <hyp/adjust_pc.h>
11 #include <hyp/fault.h>
12
13 #include <linux/arm-smccc.h>
14 #include <linux/kvm_host.h>
15 #include <linux/types.h>
16 #include <linux/jump_label.h>
17 #include <uapi/linux/psci.h>
18
19 #include <kvm/arm_psci.h>
20
21 #include <asm/barrier.h>
22 #include <asm/cpufeature.h>
23 #include <asm/extable.h>
24 #include <asm/kprobes.h>
25 #include <asm/kvm_asm.h>
26 #include <asm/kvm_emulate.h>
27 #include <asm/kvm_hyp.h>
28 #include <asm/kvm_mmu.h>
29 #include <asm/kvm_nested.h>
30 #include <asm/fpsimd.h>
31 #include <asm/debug-monitors.h>
32 #include <asm/processor.h>
33 #include <asm/traps.h>
34
35 struct kvm_exception_table_entry {
36 int insn, fixup;
37 };
38
39 extern struct kvm_exception_table_entry __start___kvm_ex_table;
40 extern struct kvm_exception_table_entry __stop___kvm_ex_table;
41
42 /* Save the 32-bit only FPSIMD system register state */
__fpsimd_save_fpexc32(struct kvm_vcpu * vcpu)43 static inline void __fpsimd_save_fpexc32(struct kvm_vcpu *vcpu)
44 {
45 if (!vcpu_el1_is_32bit(vcpu))
46 return;
47
48 __vcpu_assign_sys_reg(vcpu, FPEXC32_EL2, read_sysreg(fpexc32_el2));
49 }
50
__activate_traps_fpsimd32(struct kvm_vcpu * vcpu)51 static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
52 {
53 /*
54 * We are about to set CPTR_EL2.TFP to trap all floating point
55 * register accesses to EL2, however, the ARM ARM clearly states that
56 * traps are only taken to EL2 if the operation would not otherwise
57 * trap to EL1. Therefore, always make sure that for 32-bit guests,
58 * we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit.
59 * If FP/ASIMD is not implemented, FPEXC is UNDEFINED and any access to
60 * it will cause an exception.
61 */
62 if (vcpu_el1_is_32bit(vcpu) && system_supports_fpsimd()) {
63 write_sysreg(1 << 30, fpexc32_el2);
64 isb();
65 }
66 }
67
__activate_cptr_traps_nvhe(struct kvm_vcpu * vcpu)68 static inline void __activate_cptr_traps_nvhe(struct kvm_vcpu *vcpu)
69 {
70 u64 val = CPTR_NVHE_EL2_RES1 | CPTR_EL2_TAM | CPTR_EL2_TTA;
71
72 /*
73 * Always trap SME since it's not supported in KVM.
74 * TSM is RES1 if SME isn't implemented.
75 */
76 val |= CPTR_EL2_TSM;
77
78 if (!vcpu_has_sve(vcpu) || !guest_owns_fp_regs())
79 val |= CPTR_EL2_TZ;
80
81 if (!guest_owns_fp_regs())
82 val |= CPTR_EL2_TFP;
83
84 write_sysreg(val, cptr_el2);
85 }
86
__activate_cptr_traps_vhe(struct kvm_vcpu * vcpu)87 static inline void __activate_cptr_traps_vhe(struct kvm_vcpu *vcpu)
88 {
89 /*
90 * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to
91 * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2,
92 * except for some missing controls, such as TAM.
93 * In this case, CPTR_EL2.TAM has the same position with or without
94 * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM
95 * shift value for trapping the AMU accesses.
96 */
97 u64 val = CPTR_EL2_TAM | CPACR_EL1_TTA;
98 u64 cptr;
99
100 if (guest_owns_fp_regs()) {
101 val |= CPACR_EL1_FPEN;
102 if (vcpu_has_sve(vcpu))
103 val |= CPACR_EL1_ZEN;
104 }
105
106 if (!vcpu_has_nv(vcpu))
107 goto write;
108
109 /*
110 * The architecture is a bit crap (what a surprise): an EL2 guest
111 * writing to CPTR_EL2 via CPACR_EL1 can't set any of TCPAC or TTA,
112 * as they are RES0 in the guest's view. To work around it, trap the
113 * sucker using the very same bit it can't set...
114 */
115 if (vcpu_el2_e2h_is_set(vcpu) && is_hyp_ctxt(vcpu))
116 val |= CPTR_EL2_TCPAC;
117
118 /*
119 * Layer the guest hypervisor's trap configuration on top of our own if
120 * we're in a nested context.
121 */
122 if (is_hyp_ctxt(vcpu))
123 goto write;
124
125 cptr = vcpu_sanitised_cptr_el2(vcpu);
126
127 /*
128 * Pay attention, there's some interesting detail here.
129 *
130 * The CPTR_EL2.xEN fields are 2 bits wide, although there are only two
131 * meaningful trap states when HCR_EL2.TGE = 0 (running a nested guest):
132 *
133 * - CPTR_EL2.xEN = x0, traps are enabled
134 * - CPTR_EL2.xEN = x1, traps are disabled
135 *
136 * In other words, bit[0] determines if guest accesses trap or not. In
137 * the interest of simplicity, clear the entire field if the guest
138 * hypervisor has traps enabled to dispel any illusion of something more
139 * complicated taking place.
140 */
141 if (!(SYS_FIELD_GET(CPACR_EL1, FPEN, cptr) & BIT(0)))
142 val &= ~CPACR_EL1_FPEN;
143 if (!(SYS_FIELD_GET(CPACR_EL1, ZEN, cptr) & BIT(0)))
144 val &= ~CPACR_EL1_ZEN;
145
146 if (kvm_has_feat(vcpu->kvm, ID_AA64MMFR3_EL1, S2POE, IMP))
147 val |= cptr & CPACR_EL1_E0POE;
148
149 val |= cptr & CPTR_EL2_TCPAC;
150
151 write:
152 write_sysreg(val, cpacr_el1);
153 }
154
__activate_cptr_traps(struct kvm_vcpu * vcpu)155 static inline void __activate_cptr_traps(struct kvm_vcpu *vcpu)
156 {
157 if (!guest_owns_fp_regs())
158 __activate_traps_fpsimd32(vcpu);
159
160 if (has_vhe() || has_hvhe())
161 __activate_cptr_traps_vhe(vcpu);
162 else
163 __activate_cptr_traps_nvhe(vcpu);
164 }
165
__deactivate_cptr_traps_nvhe(struct kvm_vcpu * vcpu)166 static inline void __deactivate_cptr_traps_nvhe(struct kvm_vcpu *vcpu)
167 {
168 u64 val = CPTR_NVHE_EL2_RES1;
169
170 if (!cpus_have_final_cap(ARM64_SVE))
171 val |= CPTR_EL2_TZ;
172 if (!cpus_have_final_cap(ARM64_SME))
173 val |= CPTR_EL2_TSM;
174
175 write_sysreg(val, cptr_el2);
176 }
177
__deactivate_cptr_traps_vhe(struct kvm_vcpu * vcpu)178 static inline void __deactivate_cptr_traps_vhe(struct kvm_vcpu *vcpu)
179 {
180 u64 val = CPACR_EL1_FPEN;
181
182 if (cpus_have_final_cap(ARM64_SVE))
183 val |= CPACR_EL1_ZEN;
184 if (cpus_have_final_cap(ARM64_SME))
185 val |= CPACR_EL1_SMEN;
186
187 write_sysreg(val, cpacr_el1);
188 }
189
__deactivate_cptr_traps(struct kvm_vcpu * vcpu)190 static inline void __deactivate_cptr_traps(struct kvm_vcpu *vcpu)
191 {
192 if (has_vhe() || has_hvhe())
193 __deactivate_cptr_traps_vhe(vcpu);
194 else
195 __deactivate_cptr_traps_nvhe(vcpu);
196 }
197
198 #define reg_to_fgt_masks(reg) \
199 ({ \
200 struct fgt_masks *m; \
201 switch(reg) { \
202 case HFGRTR_EL2: \
203 m = &hfgrtr_masks; \
204 break; \
205 case HFGWTR_EL2: \
206 m = &hfgwtr_masks; \
207 break; \
208 case HFGITR_EL2: \
209 m = &hfgitr_masks; \
210 break; \
211 case HDFGRTR_EL2: \
212 m = &hdfgrtr_masks; \
213 break; \
214 case HDFGWTR_EL2: \
215 m = &hdfgwtr_masks; \
216 break; \
217 case HAFGRTR_EL2: \
218 m = &hafgrtr_masks; \
219 break; \
220 case HFGRTR2_EL2: \
221 m = &hfgrtr2_masks; \
222 break; \
223 case HFGWTR2_EL2: \
224 m = &hfgwtr2_masks; \
225 break; \
226 case HFGITR2_EL2: \
227 m = &hfgitr2_masks; \
228 break; \
229 case HDFGRTR2_EL2: \
230 m = &hdfgrtr2_masks; \
231 break; \
232 case HDFGWTR2_EL2: \
233 m = &hdfgwtr2_masks; \
234 break; \
235 default: \
236 BUILD_BUG_ON(1); \
237 } \
238 \
239 m; \
240 })
241
242 #define compute_clr_set(vcpu, reg, clr, set) \
243 do { \
244 u64 hfg = __vcpu_sys_reg(vcpu, reg); \
245 struct fgt_masks *m = reg_to_fgt_masks(reg); \
246 set |= hfg & m->mask; \
247 clr |= ~hfg & m->nmask; \
248 } while(0)
249
250 #define reg_to_fgt_group_id(reg) \
251 ({ \
252 enum fgt_group_id id; \
253 switch(reg) { \
254 case HFGRTR_EL2: \
255 case HFGWTR_EL2: \
256 id = HFGRTR_GROUP; \
257 break; \
258 case HFGITR_EL2: \
259 id = HFGITR_GROUP; \
260 break; \
261 case HDFGRTR_EL2: \
262 case HDFGWTR_EL2: \
263 id = HDFGRTR_GROUP; \
264 break; \
265 case HAFGRTR_EL2: \
266 id = HAFGRTR_GROUP; \
267 break; \
268 case HFGRTR2_EL2: \
269 case HFGWTR2_EL2: \
270 id = HFGRTR2_GROUP; \
271 break; \
272 case HFGITR2_EL2: \
273 id = HFGITR2_GROUP; \
274 break; \
275 case HDFGRTR2_EL2: \
276 case HDFGWTR2_EL2: \
277 id = HDFGRTR2_GROUP; \
278 break; \
279 default: \
280 BUILD_BUG_ON(1); \
281 } \
282 \
283 id; \
284 })
285
286 #define compute_undef_clr_set(vcpu, kvm, reg, clr, set) \
287 do { \
288 u64 hfg = kvm->arch.fgu[reg_to_fgt_group_id(reg)]; \
289 struct fgt_masks *m = reg_to_fgt_masks(reg); \
290 set |= hfg & m->mask; \
291 clr |= hfg & m->nmask; \
292 } while(0)
293
294 #define update_fgt_traps_cs(hctxt, vcpu, kvm, reg, clr, set) \
295 do { \
296 struct fgt_masks *m = reg_to_fgt_masks(reg); \
297 u64 c = clr, s = set; \
298 u64 val; \
299 \
300 ctxt_sys_reg(hctxt, reg) = read_sysreg_s(SYS_ ## reg); \
301 if (is_nested_ctxt(vcpu)) \
302 compute_clr_set(vcpu, reg, c, s); \
303 \
304 compute_undef_clr_set(vcpu, kvm, reg, c, s); \
305 \
306 val = m->nmask; \
307 val |= s; \
308 val &= ~c; \
309 write_sysreg_s(val, SYS_ ## reg); \
310 } while(0)
311
312 #define update_fgt_traps(hctxt, vcpu, kvm, reg) \
313 update_fgt_traps_cs(hctxt, vcpu, kvm, reg, 0, 0)
314
cpu_has_amu(void)315 static inline bool cpu_has_amu(void)
316 {
317 u64 pfr0 = read_sysreg_s(SYS_ID_AA64PFR0_EL1);
318
319 return cpuid_feature_extract_unsigned_field(pfr0,
320 ID_AA64PFR0_EL1_AMU_SHIFT);
321 }
322
__activate_traps_hfgxtr(struct kvm_vcpu * vcpu)323 static inline void __activate_traps_hfgxtr(struct kvm_vcpu *vcpu)
324 {
325 struct kvm_cpu_context *hctxt = host_data_ptr(host_ctxt);
326 struct kvm *kvm = kern_hyp_va(vcpu->kvm);
327
328 if (!cpus_have_final_cap(ARM64_HAS_FGT))
329 return;
330
331 update_fgt_traps(hctxt, vcpu, kvm, HFGRTR_EL2);
332 update_fgt_traps_cs(hctxt, vcpu, kvm, HFGWTR_EL2, 0,
333 cpus_have_final_cap(ARM64_WORKAROUND_AMPERE_AC03_CPU_38) ?
334 HFGWTR_EL2_TCR_EL1_MASK : 0);
335 update_fgt_traps(hctxt, vcpu, kvm, HFGITR_EL2);
336 update_fgt_traps(hctxt, vcpu, kvm, HDFGRTR_EL2);
337 update_fgt_traps(hctxt, vcpu, kvm, HDFGWTR_EL2);
338
339 if (cpu_has_amu())
340 update_fgt_traps(hctxt, vcpu, kvm, HAFGRTR_EL2);
341
342 if (!cpus_have_final_cap(ARM64_HAS_FGT2))
343 return;
344
345 update_fgt_traps(hctxt, vcpu, kvm, HFGRTR2_EL2);
346 update_fgt_traps(hctxt, vcpu, kvm, HFGWTR2_EL2);
347 update_fgt_traps(hctxt, vcpu, kvm, HFGITR2_EL2);
348 update_fgt_traps(hctxt, vcpu, kvm, HDFGRTR2_EL2);
349 update_fgt_traps(hctxt, vcpu, kvm, HDFGWTR2_EL2);
350 }
351
352 #define __deactivate_fgt(htcxt, vcpu, reg) \
353 do { \
354 write_sysreg_s(ctxt_sys_reg(hctxt, reg), \
355 SYS_ ## reg); \
356 } while(0)
357
__deactivate_traps_hfgxtr(struct kvm_vcpu * vcpu)358 static inline void __deactivate_traps_hfgxtr(struct kvm_vcpu *vcpu)
359 {
360 struct kvm_cpu_context *hctxt = host_data_ptr(host_ctxt);
361
362 if (!cpus_have_final_cap(ARM64_HAS_FGT))
363 return;
364
365 __deactivate_fgt(hctxt, vcpu, HFGRTR_EL2);
366 __deactivate_fgt(hctxt, vcpu, HFGWTR_EL2);
367 __deactivate_fgt(hctxt, vcpu, HFGITR_EL2);
368 __deactivate_fgt(hctxt, vcpu, HDFGRTR_EL2);
369 __deactivate_fgt(hctxt, vcpu, HDFGWTR_EL2);
370
371 if (cpu_has_amu())
372 __deactivate_fgt(hctxt, vcpu, HAFGRTR_EL2);
373
374 if (!cpus_have_final_cap(ARM64_HAS_FGT2))
375 return;
376
377 __deactivate_fgt(hctxt, vcpu, HFGRTR2_EL2);
378 __deactivate_fgt(hctxt, vcpu, HFGWTR2_EL2);
379 __deactivate_fgt(hctxt, vcpu, HFGITR2_EL2);
380 __deactivate_fgt(hctxt, vcpu, HDFGRTR2_EL2);
381 __deactivate_fgt(hctxt, vcpu, HDFGWTR2_EL2);
382 }
383
__activate_traps_mpam(struct kvm_vcpu * vcpu)384 static inline void __activate_traps_mpam(struct kvm_vcpu *vcpu)
385 {
386 u64 r = MPAM2_EL2_TRAPMPAM0EL1 | MPAM2_EL2_TRAPMPAM1EL1;
387
388 if (!system_supports_mpam())
389 return;
390
391 /* trap guest access to MPAMIDR_EL1 */
392 if (system_supports_mpam_hcr()) {
393 write_sysreg_s(MPAMHCR_EL2_TRAP_MPAMIDR_EL1, SYS_MPAMHCR_EL2);
394 } else {
395 /* From v1.1 TIDR can trap MPAMIDR, set it unconditionally */
396 r |= MPAM2_EL2_TIDR;
397 }
398
399 write_sysreg_s(r, SYS_MPAM2_EL2);
400 }
401
__deactivate_traps_mpam(void)402 static inline void __deactivate_traps_mpam(void)
403 {
404 if (!system_supports_mpam())
405 return;
406
407 write_sysreg_s(0, SYS_MPAM2_EL2);
408
409 if (system_supports_mpam_hcr())
410 write_sysreg_s(MPAMHCR_HOST_FLAGS, SYS_MPAMHCR_EL2);
411 }
412
__activate_traps_common(struct kvm_vcpu * vcpu)413 static inline void __activate_traps_common(struct kvm_vcpu *vcpu)
414 {
415 struct kvm_cpu_context *hctxt = host_data_ptr(host_ctxt);
416
417 /* Trap on AArch32 cp15 c15 (impdef sysregs) accesses (EL1 or EL0) */
418 write_sysreg(1 << 15, hstr_el2);
419
420 /*
421 * Make sure we trap PMU access from EL0 to EL2. Also sanitize
422 * PMSELR_EL0 to make sure it never contains the cycle
423 * counter, which could make a PMXEVCNTR_EL0 access UNDEF at
424 * EL1 instead of being trapped to EL2.
425 */
426 if (system_supports_pmuv3()) {
427 write_sysreg(0, pmselr_el0);
428
429 ctxt_sys_reg(hctxt, PMUSERENR_EL0) = read_sysreg(pmuserenr_el0);
430 write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);
431 vcpu_set_flag(vcpu, PMUSERENR_ON_CPU);
432 }
433
434 *host_data_ptr(host_debug_state.mdcr_el2) = read_sysreg(mdcr_el2);
435 write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);
436
437 if (cpus_have_final_cap(ARM64_HAS_HCX)) {
438 u64 hcrx = vcpu->arch.hcrx_el2;
439 if (is_nested_ctxt(vcpu)) {
440 u64 val = __vcpu_sys_reg(vcpu, HCRX_EL2);
441 hcrx |= val & __HCRX_EL2_MASK;
442 hcrx &= ~(~val & __HCRX_EL2_nMASK);
443 }
444
445 ctxt_sys_reg(hctxt, HCRX_EL2) = read_sysreg_s(SYS_HCRX_EL2);
446 write_sysreg_s(hcrx, SYS_HCRX_EL2);
447 }
448
449 __activate_traps_hfgxtr(vcpu);
450 __activate_traps_mpam(vcpu);
451 }
452
__deactivate_traps_common(struct kvm_vcpu * vcpu)453 static inline void __deactivate_traps_common(struct kvm_vcpu *vcpu)
454 {
455 struct kvm_cpu_context *hctxt = host_data_ptr(host_ctxt);
456
457 write_sysreg(*host_data_ptr(host_debug_state.mdcr_el2), mdcr_el2);
458
459 write_sysreg(0, hstr_el2);
460 if (system_supports_pmuv3()) {
461 write_sysreg(ctxt_sys_reg(hctxt, PMUSERENR_EL0), pmuserenr_el0);
462 vcpu_clear_flag(vcpu, PMUSERENR_ON_CPU);
463 }
464
465 if (cpus_have_final_cap(ARM64_HAS_HCX))
466 write_sysreg_s(ctxt_sys_reg(hctxt, HCRX_EL2), SYS_HCRX_EL2);
467
468 __deactivate_traps_hfgxtr(vcpu);
469 __deactivate_traps_mpam();
470 }
471
___activate_traps(struct kvm_vcpu * vcpu,u64 hcr)472 static inline void ___activate_traps(struct kvm_vcpu *vcpu, u64 hcr)
473 {
474 if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM))
475 hcr |= HCR_TVM;
476
477 write_sysreg_hcr(hcr);
478
479 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN) && (hcr & HCR_VSE)) {
480 u64 vsesr;
481
482 /*
483 * When HCR_EL2.AMO is set, physical SErrors are taken to EL2
484 * and vSError injection is enabled for EL1. Conveniently, for
485 * NV this means that it is never the case where a 'physical'
486 * SError (injected by KVM or userspace) and vSError are
487 * deliverable to the same context.
488 *
489 * As such, we can trivially select between the host or guest's
490 * VSESR_EL2. Except for the case that FEAT_RAS hasn't been
491 * exposed to the guest, where ESR propagation in hardware
492 * occurs unconditionally.
493 *
494 * Paper over the architectural wart and use an IMPLEMENTATION
495 * DEFINED ESR value in case FEAT_RAS is hidden from the guest.
496 */
497 if (!vserror_state_is_nested(vcpu))
498 vsesr = vcpu->arch.vsesr_el2;
499 else if (kvm_has_ras(kern_hyp_va(vcpu->kvm)))
500 vsesr = __vcpu_sys_reg(vcpu, VSESR_EL2);
501 else
502 vsesr = ESR_ELx_ISV;
503
504 write_sysreg_s(vsesr, SYS_VSESR_EL2);
505 }
506 }
507
___deactivate_traps(struct kvm_vcpu * vcpu)508 static inline void ___deactivate_traps(struct kvm_vcpu *vcpu)
509 {
510 u64 *hcr;
511
512 if (vserror_state_is_nested(vcpu))
513 hcr = __ctxt_sys_reg(&vcpu->arch.ctxt, HCR_EL2);
514 else
515 hcr = &vcpu->arch.hcr_el2;
516
517 /*
518 * If we pended a virtual abort, preserve it until it gets
519 * cleared. See D1.14.3 (Virtual Interrupts) for details, but
520 * the crucial bit is "On taking a vSError interrupt,
521 * HCR_EL2.VSE is cleared to 0."
522 *
523 * Additionally, when in a nested context we need to propagate the
524 * updated state to the guest hypervisor's HCR_EL2.
525 */
526 if (*hcr & HCR_VSE) {
527 *hcr &= ~HCR_VSE;
528 *hcr |= read_sysreg(hcr_el2) & HCR_VSE;
529 }
530 }
531
__populate_fault_info(struct kvm_vcpu * vcpu)532 static inline bool __populate_fault_info(struct kvm_vcpu *vcpu)
533 {
534 return __get_fault_info(vcpu->arch.fault.esr_el2, &vcpu->arch.fault);
535 }
536
kvm_hyp_handle_mops(struct kvm_vcpu * vcpu,u64 * exit_code)537 static inline bool kvm_hyp_handle_mops(struct kvm_vcpu *vcpu, u64 *exit_code)
538 {
539 *vcpu_pc(vcpu) = read_sysreg_el2(SYS_ELR);
540 arm64_mops_reset_regs(vcpu_gp_regs(vcpu), vcpu->arch.fault.esr_el2);
541 write_sysreg_el2(*vcpu_pc(vcpu), SYS_ELR);
542
543 /*
544 * Finish potential single step before executing the prologue
545 * instruction.
546 */
547 *vcpu_cpsr(vcpu) &= ~DBG_SPSR_SS;
548 write_sysreg_el2(*vcpu_cpsr(vcpu), SYS_SPSR);
549
550 return true;
551 }
552
__hyp_sve_restore_guest(struct kvm_vcpu * vcpu)553 static inline void __hyp_sve_restore_guest(struct kvm_vcpu *vcpu)
554 {
555 /*
556 * The vCPU's saved SVE state layout always matches the max VL of the
557 * vCPU. Start off with the max VL so we can load the SVE state.
558 */
559 sve_cond_update_zcr_vq(vcpu_sve_max_vq(vcpu) - 1, SYS_ZCR_EL2);
560 __sve_restore_state(vcpu_sve_pffr(vcpu),
561 &vcpu->arch.ctxt.fp_regs.fpsr,
562 true);
563
564 /*
565 * The effective VL for a VM could differ from the max VL when running a
566 * nested guest, as the guest hypervisor could select a smaller VL. Slap
567 * that into hardware before wrapping up.
568 */
569 if (is_nested_ctxt(vcpu))
570 sve_cond_update_zcr_vq(__vcpu_sys_reg(vcpu, ZCR_EL2), SYS_ZCR_EL2);
571
572 write_sysreg_el1(__vcpu_sys_reg(vcpu, vcpu_sve_zcr_elx(vcpu)), SYS_ZCR);
573 }
574
__hyp_sve_save_host(void)575 static inline void __hyp_sve_save_host(void)
576 {
577 struct cpu_sve_state *sve_state = *host_data_ptr(sve_state);
578
579 sve_state->zcr_el1 = read_sysreg_el1(SYS_ZCR);
580 write_sysreg_s(sve_vq_from_vl(kvm_host_sve_max_vl) - 1, SYS_ZCR_EL2);
581 __sve_save_state(sve_state->sve_regs + sve_ffr_offset(kvm_host_sve_max_vl),
582 &sve_state->fpsr,
583 true);
584 }
585
fpsimd_lazy_switch_to_guest(struct kvm_vcpu * vcpu)586 static inline void fpsimd_lazy_switch_to_guest(struct kvm_vcpu *vcpu)
587 {
588 u64 zcr_el1, zcr_el2;
589
590 if (!guest_owns_fp_regs())
591 return;
592
593 if (vcpu_has_sve(vcpu)) {
594 /* A guest hypervisor may restrict the effective max VL. */
595 if (is_nested_ctxt(vcpu))
596 zcr_el2 = __vcpu_sys_reg(vcpu, ZCR_EL2);
597 else
598 zcr_el2 = vcpu_sve_max_vq(vcpu) - 1;
599
600 write_sysreg_el2(zcr_el2, SYS_ZCR);
601
602 zcr_el1 = __vcpu_sys_reg(vcpu, vcpu_sve_zcr_elx(vcpu));
603 write_sysreg_el1(zcr_el1, SYS_ZCR);
604 }
605 }
606
fpsimd_lazy_switch_to_host(struct kvm_vcpu * vcpu)607 static inline void fpsimd_lazy_switch_to_host(struct kvm_vcpu *vcpu)
608 {
609 u64 zcr_el1, zcr_el2;
610
611 if (!guest_owns_fp_regs())
612 return;
613
614 /*
615 * When the guest owns the FP regs, we know that guest+hyp traps for
616 * any FPSIMD/SVE/SME features exposed to the guest have been disabled
617 * by either fpsimd_lazy_switch_to_guest() or kvm_hyp_handle_fpsimd()
618 * prior to __guest_entry(). As __guest_entry() guarantees a context
619 * synchronization event, we don't need an ISB here to avoid taking
620 * traps for anything that was exposed to the guest.
621 */
622 if (vcpu_has_sve(vcpu)) {
623 zcr_el1 = read_sysreg_el1(SYS_ZCR);
624 __vcpu_assign_sys_reg(vcpu, vcpu_sve_zcr_elx(vcpu), zcr_el1);
625
626 /*
627 * The guest's state is always saved using the guest's max VL.
628 * Ensure that the host has the guest's max VL active such that
629 * the host can save the guest's state lazily, but don't
630 * artificially restrict the host to the guest's max VL.
631 */
632 if (has_vhe()) {
633 zcr_el2 = vcpu_sve_max_vq(vcpu) - 1;
634 write_sysreg_el2(zcr_el2, SYS_ZCR);
635 } else {
636 zcr_el2 = sve_vq_from_vl(kvm_host_sve_max_vl) - 1;
637 write_sysreg_el2(zcr_el2, SYS_ZCR);
638
639 zcr_el1 = vcpu_sve_max_vq(vcpu) - 1;
640 write_sysreg_el1(zcr_el1, SYS_ZCR);
641 }
642 }
643 }
644
kvm_hyp_save_fpsimd_host(struct kvm_vcpu * vcpu)645 static void kvm_hyp_save_fpsimd_host(struct kvm_vcpu *vcpu)
646 {
647 /*
648 * Non-protected kvm relies on the host restoring its sve state.
649 * Protected kvm restores the host's sve state as not to reveal that
650 * fpsimd was used by a guest nor leak upper sve bits.
651 */
652 if (system_supports_sve()) {
653 __hyp_sve_save_host();
654 } else {
655 __fpsimd_save_state(host_data_ptr(host_ctxt.fp_regs));
656 }
657
658 if (kvm_has_fpmr(kern_hyp_va(vcpu->kvm)))
659 *host_data_ptr(fpmr) = read_sysreg_s(SYS_FPMR);
660 }
661
662
663 /*
664 * We trap the first access to the FP/SIMD to save the host context and
665 * restore the guest context lazily.
666 * If FP/SIMD is not implemented, handle the trap and inject an undefined
667 * instruction exception to the guest. Similarly for trapped SVE accesses.
668 */
kvm_hyp_handle_fpsimd(struct kvm_vcpu * vcpu,u64 * exit_code)669 static inline bool kvm_hyp_handle_fpsimd(struct kvm_vcpu *vcpu, u64 *exit_code)
670 {
671 bool sve_guest;
672 u8 esr_ec;
673
674 if (!system_supports_fpsimd())
675 return false;
676
677 sve_guest = vcpu_has_sve(vcpu);
678 esr_ec = kvm_vcpu_trap_get_class(vcpu);
679
680 /* Only handle traps the vCPU can support here: */
681 switch (esr_ec) {
682 case ESR_ELx_EC_FP_ASIMD:
683 /* Forward traps to the guest hypervisor as required */
684 if (guest_hyp_fpsimd_traps_enabled(vcpu))
685 return false;
686 break;
687 case ESR_ELx_EC_SYS64:
688 if (WARN_ON_ONCE(!is_hyp_ctxt(vcpu)))
689 return false;
690 fallthrough;
691 case ESR_ELx_EC_SVE:
692 if (!sve_guest)
693 return false;
694 if (guest_hyp_sve_traps_enabled(vcpu))
695 return false;
696 break;
697 default:
698 return false;
699 }
700
701 /* Valid trap. Switch the context: */
702
703 /* First disable enough traps to allow us to update the registers */
704 __deactivate_cptr_traps(vcpu);
705 isb();
706
707 /* Write out the host state if it's in the registers */
708 if (is_protected_kvm_enabled() && host_owns_fp_regs())
709 kvm_hyp_save_fpsimd_host(vcpu);
710
711 /* Restore the guest state */
712 if (sve_guest)
713 __hyp_sve_restore_guest(vcpu);
714 else
715 __fpsimd_restore_state(&vcpu->arch.ctxt.fp_regs);
716
717 if (kvm_has_fpmr(kern_hyp_va(vcpu->kvm)))
718 write_sysreg_s(__vcpu_sys_reg(vcpu, FPMR), SYS_FPMR);
719
720 /* Skip restoring fpexc32 for AArch64 guests */
721 if (!(read_sysreg(hcr_el2) & HCR_RW))
722 write_sysreg(__vcpu_sys_reg(vcpu, FPEXC32_EL2), fpexc32_el2);
723
724 *host_data_ptr(fp_owner) = FP_STATE_GUEST_OWNED;
725
726 /*
727 * Re-enable traps necessary for the current state of the guest, e.g.
728 * those enabled by a guest hypervisor. The ERET to the guest will
729 * provide the necessary context synchronization.
730 */
731 __activate_cptr_traps(vcpu);
732
733 return true;
734 }
735
handle_tx2_tvm(struct kvm_vcpu * vcpu)736 static inline bool handle_tx2_tvm(struct kvm_vcpu *vcpu)
737 {
738 u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
739 int rt = kvm_vcpu_sys_get_rt(vcpu);
740 u64 val = vcpu_get_reg(vcpu, rt);
741
742 /*
743 * The normal sysreg handling code expects to see the traps,
744 * let's not do anything here.
745 */
746 if (vcpu->arch.hcr_el2 & HCR_TVM)
747 return false;
748
749 switch (sysreg) {
750 case SYS_SCTLR_EL1:
751 write_sysreg_el1(val, SYS_SCTLR);
752 break;
753 case SYS_TTBR0_EL1:
754 write_sysreg_el1(val, SYS_TTBR0);
755 break;
756 case SYS_TTBR1_EL1:
757 write_sysreg_el1(val, SYS_TTBR1);
758 break;
759 case SYS_TCR_EL1:
760 write_sysreg_el1(val, SYS_TCR);
761 break;
762 case SYS_ESR_EL1:
763 write_sysreg_el1(val, SYS_ESR);
764 break;
765 case SYS_FAR_EL1:
766 write_sysreg_el1(val, SYS_FAR);
767 break;
768 case SYS_AFSR0_EL1:
769 write_sysreg_el1(val, SYS_AFSR0);
770 break;
771 case SYS_AFSR1_EL1:
772 write_sysreg_el1(val, SYS_AFSR1);
773 break;
774 case SYS_MAIR_EL1:
775 write_sysreg_el1(val, SYS_MAIR);
776 break;
777 case SYS_AMAIR_EL1:
778 write_sysreg_el1(val, SYS_AMAIR);
779 break;
780 case SYS_CONTEXTIDR_EL1:
781 write_sysreg_el1(val, SYS_CONTEXTIDR);
782 break;
783 default:
784 return false;
785 }
786
787 __kvm_skip_instr(vcpu);
788 return true;
789 }
790
791 /* Open-coded version of timer_get_offset() to allow for kern_hyp_va() */
hyp_timer_get_offset(struct arch_timer_context * ctxt)792 static inline u64 hyp_timer_get_offset(struct arch_timer_context *ctxt)
793 {
794 u64 offset = 0;
795
796 if (ctxt->offset.vm_offset)
797 offset += *kern_hyp_va(ctxt->offset.vm_offset);
798 if (ctxt->offset.vcpu_offset)
799 offset += *kern_hyp_va(ctxt->offset.vcpu_offset);
800
801 return offset;
802 }
803
compute_counter_value(struct arch_timer_context * ctxt)804 static inline u64 compute_counter_value(struct arch_timer_context *ctxt)
805 {
806 return arch_timer_read_cntpct_el0() - hyp_timer_get_offset(ctxt);
807 }
808
kvm_handle_cntxct(struct kvm_vcpu * vcpu)809 static bool kvm_handle_cntxct(struct kvm_vcpu *vcpu)
810 {
811 struct arch_timer_context *ctxt;
812 u32 sysreg;
813 u64 val;
814
815 /*
816 * We only get here for 64bit guests, 32bit guests will hit
817 * the long and winding road all the way to the standard
818 * handling. Yes, it sucks to be irrelevant.
819 *
820 * Also, we only deal with non-hypervisor context here (either
821 * an EL1 guest, or a non-HYP context of an EL2 guest).
822 */
823 if (is_hyp_ctxt(vcpu))
824 return false;
825
826 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
827
828 switch (sysreg) {
829 case SYS_CNTPCT_EL0:
830 case SYS_CNTPCTSS_EL0:
831 if (vcpu_has_nv(vcpu)) {
832 /* Check for guest hypervisor trapping */
833 val = __vcpu_sys_reg(vcpu, CNTHCTL_EL2);
834 if (!vcpu_el2_e2h_is_set(vcpu))
835 val = (val & CNTHCTL_EL1PCTEN) << 10;
836
837 if (!(val & (CNTHCTL_EL1PCTEN << 10)))
838 return false;
839 }
840
841 ctxt = vcpu_ptimer(vcpu);
842 break;
843 case SYS_CNTVCT_EL0:
844 case SYS_CNTVCTSS_EL0:
845 if (vcpu_has_nv(vcpu)) {
846 /* Check for guest hypervisor trapping */
847 val = __vcpu_sys_reg(vcpu, CNTHCTL_EL2);
848
849 if (val & CNTHCTL_EL1TVCT)
850 return false;
851 }
852
853 ctxt = vcpu_vtimer(vcpu);
854 break;
855 default:
856 return false;
857 }
858
859 val = compute_counter_value(ctxt);
860
861 vcpu_set_reg(vcpu, kvm_vcpu_sys_get_rt(vcpu), val);
862 __kvm_skip_instr(vcpu);
863 return true;
864 }
865
handle_ampere1_tcr(struct kvm_vcpu * vcpu)866 static bool handle_ampere1_tcr(struct kvm_vcpu *vcpu)
867 {
868 u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
869 int rt = kvm_vcpu_sys_get_rt(vcpu);
870 u64 val = vcpu_get_reg(vcpu, rt);
871
872 if (sysreg != SYS_TCR_EL1)
873 return false;
874
875 /*
876 * Affected parts do not advertise support for hardware Access Flag /
877 * Dirty state management in ID_AA64MMFR1_EL1.HAFDBS, but the underlying
878 * control bits are still functional. The architecture requires these be
879 * RES0 on systems that do not implement FEAT_HAFDBS.
880 *
881 * Uphold the requirements of the architecture by masking guest writes
882 * to TCR_EL1.{HA,HD} here.
883 */
884 val &= ~(TCR_HD | TCR_HA);
885 write_sysreg_el1(val, SYS_TCR);
886 __kvm_skip_instr(vcpu);
887 return true;
888 }
889
kvm_hyp_handle_sysreg(struct kvm_vcpu * vcpu,u64 * exit_code)890 static inline bool kvm_hyp_handle_sysreg(struct kvm_vcpu *vcpu, u64 *exit_code)
891 {
892 if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM) &&
893 handle_tx2_tvm(vcpu))
894 return true;
895
896 if (cpus_have_final_cap(ARM64_WORKAROUND_AMPERE_AC03_CPU_38) &&
897 handle_ampere1_tcr(vcpu))
898 return true;
899
900 if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
901 __vgic_v3_perform_cpuif_access(vcpu) == 1)
902 return true;
903
904 if (kvm_handle_cntxct(vcpu))
905 return true;
906
907 return false;
908 }
909
kvm_hyp_handle_cp15_32(struct kvm_vcpu * vcpu,u64 * exit_code)910 static inline bool kvm_hyp_handle_cp15_32(struct kvm_vcpu *vcpu, u64 *exit_code)
911 {
912 if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
913 __vgic_v3_perform_cpuif_access(vcpu) == 1)
914 return true;
915
916 return false;
917 }
918
kvm_hyp_handle_memory_fault(struct kvm_vcpu * vcpu,u64 * exit_code)919 static inline bool kvm_hyp_handle_memory_fault(struct kvm_vcpu *vcpu,
920 u64 *exit_code)
921 {
922 if (!__populate_fault_info(vcpu))
923 return true;
924
925 return false;
926 }
927 #define kvm_hyp_handle_iabt_low kvm_hyp_handle_memory_fault
928 #define kvm_hyp_handle_watchpt_low kvm_hyp_handle_memory_fault
929
kvm_hyp_handle_dabt_low(struct kvm_vcpu * vcpu,u64 * exit_code)930 static inline bool kvm_hyp_handle_dabt_low(struct kvm_vcpu *vcpu, u64 *exit_code)
931 {
932 if (kvm_hyp_handle_memory_fault(vcpu, exit_code))
933 return true;
934
935 if (static_branch_unlikely(&vgic_v2_cpuif_trap)) {
936 bool valid;
937
938 valid = kvm_vcpu_trap_is_translation_fault(vcpu) &&
939 kvm_vcpu_dabt_isvalid(vcpu) &&
940 !kvm_vcpu_abt_issea(vcpu) &&
941 !kvm_vcpu_abt_iss1tw(vcpu);
942
943 if (valid) {
944 int ret = __vgic_v2_perform_cpuif_access(vcpu);
945
946 if (ret == 1)
947 return true;
948
949 /* Promote an illegal access to an SError.*/
950 if (ret == -1)
951 *exit_code = ARM_EXCEPTION_EL1_SERROR;
952 }
953 }
954
955 return false;
956 }
957
958 typedef bool (*exit_handler_fn)(struct kvm_vcpu *, u64 *);
959
960 /*
961 * Allow the hypervisor to handle the exit with an exit handler if it has one.
962 *
963 * Returns true if the hypervisor handled the exit, and control should go back
964 * to the guest, or false if it hasn't.
965 */
kvm_hyp_handle_exit(struct kvm_vcpu * vcpu,u64 * exit_code,const exit_handler_fn * handlers)966 static inline bool kvm_hyp_handle_exit(struct kvm_vcpu *vcpu, u64 *exit_code,
967 const exit_handler_fn *handlers)
968 {
969 exit_handler_fn fn = handlers[kvm_vcpu_trap_get_class(vcpu)];
970 if (fn)
971 return fn(vcpu, exit_code);
972
973 return false;
974 }
975
synchronize_vcpu_pstate(struct kvm_vcpu * vcpu,u64 * exit_code)976 static inline void synchronize_vcpu_pstate(struct kvm_vcpu *vcpu, u64 *exit_code)
977 {
978 /*
979 * Check for the conditions of Cortex-A510's #2077057. When these occur
980 * SPSR_EL2 can't be trusted, but isn't needed either as it is
981 * unchanged from the value in vcpu_gp_regs(vcpu)->pstate.
982 * Are we single-stepping the guest, and took a PAC exception from the
983 * active-not-pending state?
984 */
985 if (cpus_have_final_cap(ARM64_WORKAROUND_2077057) &&
986 vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
987 *vcpu_cpsr(vcpu) & DBG_SPSR_SS &&
988 ESR_ELx_EC(read_sysreg_el2(SYS_ESR)) == ESR_ELx_EC_PAC)
989 write_sysreg_el2(*vcpu_cpsr(vcpu), SYS_SPSR);
990
991 vcpu->arch.ctxt.regs.pstate = read_sysreg_el2(SYS_SPSR);
992 }
993
994 /*
995 * Return true when we were able to fixup the guest exit and should return to
996 * the guest, false when we should restore the host state and return to the
997 * main run loop.
998 */
__fixup_guest_exit(struct kvm_vcpu * vcpu,u64 * exit_code,const exit_handler_fn * handlers)999 static inline bool __fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code,
1000 const exit_handler_fn *handlers)
1001 {
1002 if (ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ)
1003 vcpu->arch.fault.esr_el2 = read_sysreg_el2(SYS_ESR);
1004
1005 if (ARM_SERROR_PENDING(*exit_code) &&
1006 ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ) {
1007 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
1008
1009 /*
1010 * HVC already have an adjusted PC, which we need to
1011 * correct in order to return to after having injected
1012 * the SError.
1013 *
1014 * SMC, on the other hand, is *trapped*, meaning its
1015 * preferred return address is the SMC itself.
1016 */
1017 if (esr_ec == ESR_ELx_EC_HVC32 || esr_ec == ESR_ELx_EC_HVC64)
1018 write_sysreg_el2(read_sysreg_el2(SYS_ELR) - 4, SYS_ELR);
1019 }
1020
1021 /*
1022 * We're using the raw exception code in order to only process
1023 * the trap if no SError is pending. We will come back to the
1024 * same PC once the SError has been injected, and replay the
1025 * trapping instruction.
1026 */
1027 if (*exit_code != ARM_EXCEPTION_TRAP)
1028 goto exit;
1029
1030 /* Check if there's an exit handler and allow it to handle the exit. */
1031 if (kvm_hyp_handle_exit(vcpu, exit_code, handlers))
1032 goto guest;
1033 exit:
1034 /* Return to the host kernel and handle the exit */
1035 return false;
1036
1037 guest:
1038 /* Re-enter the guest */
1039 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412));
1040 return true;
1041 }
1042
__kvm_unexpected_el2_exception(void)1043 static inline void __kvm_unexpected_el2_exception(void)
1044 {
1045 extern char __guest_exit_restore_elr_and_panic[];
1046 unsigned long addr, fixup;
1047 struct kvm_exception_table_entry *entry, *end;
1048 unsigned long elr_el2 = read_sysreg(elr_el2);
1049
1050 entry = &__start___kvm_ex_table;
1051 end = &__stop___kvm_ex_table;
1052
1053 while (entry < end) {
1054 addr = (unsigned long)&entry->insn + entry->insn;
1055 fixup = (unsigned long)&entry->fixup + entry->fixup;
1056
1057 if (addr != elr_el2) {
1058 entry++;
1059 continue;
1060 }
1061
1062 write_sysreg(fixup, elr_el2);
1063 return;
1064 }
1065
1066 /* Trigger a panic after restoring the hyp context. */
1067 this_cpu_ptr(&kvm_hyp_ctxt)->sys_regs[ELR_EL2] = elr_el2;
1068 write_sysreg(__guest_exit_restore_elr_and_panic, elr_el2);
1069 }
1070
1071 #endif /* __ARM64_KVM_HYP_SWITCH_H__ */
1072