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/linux/Documentation/devicetree/bindings/usb/
H A Ddwc3-xilinx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx SuperSpeed DWC3 USB SoC controller
10 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
15 - enum:
16 - xlnx,zynqmp-dwc3
17 - xlnx,versal-dwc3
21 "#address-cells":
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/linux/drivers/usb/dwc3/
H A Ddwc3-xilinx.c1 // SPDX-License-Identifier: GPL-2.0
3 * dwc3-xilinx.c - Xilinx DWC3 controller specific glue driver
15 #include <linux/dma-mapping.h>
22 #include <linux/firmware/xlnx-zynqmp.h>
62 reg = readl(priv_data->regs + XLNX_USB_PHY_RST_EN); in dwc3_xlnx_mask_phy_rst()
69 writel(reg, priv_data->regs + XLNX_USB_PHY_RST_EN); in dwc3_xlnx_mask_phy_rst()
74 struct device *dev = priv_data->dev; in dwc3_xlnx_set_coherency()
82 if (of_dma_is_coherent(dev->of_node) || device_iommu_mapped(dev)) { in dwc3_xlnx_set_coherency()
83 reg = readl(priv_data->regs + coherency_offset); in dwc3_xlnx_set_coherency()
85 writel(reg, priv_data->regs + coherency_offset); in dwc3_xlnx_set_coherency()
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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