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Searched full:xe_reg (Results 1 – 20 of 20) sorted by relevance

/linux/drivers/gpu/drm/xe/regs/
H A Dxe_engine_regs.h46 #define ENGINE_ID(base) XE_REG((base) + 0x8c)
50 #define RING_TAIL(base) XE_REG((base) + 0x30)
53 #define RING_HEAD(base) XE_REG((base) + 0x34)
56 #define RING_START(base) XE_REG((base) + 0x38)
58 #define RING_CTL(base) XE_REG((base) + 0x3c)
61 #define RING_START_UDW(base) XE_REG((base) + 0x48)
63 #define RING_PSMI_CTL(base) XE_REG((base) + 0x50, XE_REG_OPTION_MASKED)
68 #define RING_PWRCTX_MAXCNT(base) XE_REG((base) + 0x54)
71 #define RING_ACTHD_UDW(base) XE_REG((base) + 0x5c)
72 #define RING_DMA_FADD_UDW(base) XE_REG((base) + 0x60)
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H A Dxe_gt_regs.h20 #define MTL_MIRROR_TARGET_WP1 XE_REG(0xc60)
26 #define RPM_CONFIG0 XE_REG(0xd00)
34 #define FORCEWAKE_ACK_MEDIA_VDBOX(n) XE_REG(0xd50 + (n) * 4)
35 #define FORCEWAKE_ACK_MEDIA_VEBOX(n) XE_REG(0xd70 + (n) * 4)
36 #define FORCEWAKE_ACK_RENDER XE_REG(0xd84)
38 #define GMD_ID XE_REG(0xd8c)
49 #define FORCEWAKE_ACK_GSC XE_REG(0xdf8)
50 #define FORCEWAKE_ACK_GT_MTL XE_REG(0xdfc)
52 #define STEER_SEMAPHORE XE_REG(0xfd0)
53 #define MTL_MCR_SELECTOR XE_REG(0xfd4)
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H A Dxe_mchbar_regs.h21 #define PCU_CR_PACKAGE_POWER_SKU XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5930)
30 #define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
35 #define PCU_CR_PACKAGE_ENERGY_STATUS XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x593c)
37 #define PCU_CR_PACKAGE_TEMPERATURE XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5978)
40 #define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
/linux/drivers/gpu/drm/xe/
H A Dxe_gt_sriov_vf.h13 struct xe_reg;
35 u32 xe_gt_sriov_vf_read32(struct xe_gt *gt, struct xe_reg reg);
36 void xe_gt_sriov_vf_write32(struct xe_gt *gt, struct xe_reg reg, u32 val);
H A Dxe_gt_sriov_pf_service_types.h11 struct xe_reg;
32 const struct xe_reg *regs;
H A Dxe_hw_engine.h79 void xe_hw_engine_mmio_write32(struct xe_hw_engine *hwe, struct xe_reg reg, u32 val);
80 u32 xe_hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg);
H A Dxe_reg_whitelist.c20 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)
59 XE_RTP_ACTIONS(WHITELIST(XE_REG(0x4400),
62 WHITELIST(XE_REG(0x4500),
H A Dxe_reg_sr.c125 static struct xe_reg_mcr to_xe_reg_mcr(const struct xe_reg reg) in to_xe_reg_mcr()
132 struct xe_reg reg = entry->reg; in apply_one_mmio()
215 static u32 readback_reg(struct xe_gt *gt, struct xe_reg reg) in readback_reg()
H A Dxe_reg_sr_types.h15 struct xe_reg reg;
H A Dxe_gt_throttle.c87 struct xe_reg reg; in xe_gt_throttle_get_limit_reasons()
H A Dxe_tuning.c21 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)
H A Dxe_hw_engine.c296 struct xe_reg reg, u32 val) in xe_hw_engine_mmio_write32()
316 u32 xe_hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg) in xe_hw_engine_mmio_read32()
H A Dxe_guc_ads.c703 struct xe_reg reg, in guc_mmio_regset_write_one()
739 struct xe_reg reg; in guc_mmio_regset_write()
H A Dxe_oa.c64 struct xe_reg addr;
392 struct xe_reg oaheadptr = __oa_regs(stream)->oa_head_ptr; in xe_oa_append_reports()
2123 static const struct xe_reg flex_eu_regs[] = { in xe_oa_is_valid_flex_addr()
2272 oa_regs[i].addr = XE_REG(addr); in xe_oa_alloc_regs()
H A Dxe_ring_ops.c52 __emit_aux_table_inv(u32 *cmd, const struct xe_reg reg, u32 adj_offset) in __emit_aux_table_inv()
H A Dxe_gt_sriov_vf.c1087 u32 xe_gt_sriov_vf_read32(struct xe_gt *gt, struct xe_reg reg) in xe_gt_sriov_vf_read32()
1122 void xe_gt_sriov_vf_write32(struct xe_gt *gt, struct xe_reg reg, u32 val) in xe_gt_sriov_vf_write32()
H A Dxe_gt.c287 struct xe_reg reg = entry->reg; in emit_wa_job()
H A Dxe_wa.c128 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)
H A Dxe_pci.c596 struct xe_reg gmdid_reg = GMD_ID; in read_gmdid()
H A Dxe_guc.c1477 struct xe_reg reply_reg = xe_gt_is_media_type(gt) ? in xe_guc_mmio_send_recv()