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Searched full:xe_reg (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/xe/regs/
H A Dxe_gt_regs.h20 #define MTL_MIRROR_TARGET_WP1 XE_REG(0xc60)
25 #define RPM_CONFIG0 XE_REG(0xd00)
33 #define FORCEWAKE_ACK_MEDIA_VDBOX(n) XE_REG(0xd50 + (n) * 4)
34 #define FORCEWAKE_ACK_MEDIA_VEBOX(n) XE_REG(0xd70 + (n) * 4)
35 #define FORCEWAKE_ACK_RENDER XE_REG(0xd84)
37 #define GMD_ID XE_REG(0xd8c)
48 #define FORCEWAKE_ACK_GSC XE_REG(0xdf8)
49 #define FORCEWAKE_ACK_GT_MTL XE_REG(0xdfc)
51 #define STEER_SEMAPHORE XE_REG(0xfd0)
52 #define MTL_MCR_SELECTOR XE_REG(0xfd4)
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H A Dxe_pcode_regs.h15 #define PVC_GT0_PACKAGE_ENERGY_STATUS XE_REG(0x281004)
16 #define PVC_GT0_PACKAGE_RAPL_LIMIT XE_REG(0x281008)
17 #define PVC_GT0_PACKAGE_POWER_SKU_UNIT XE_REG(0x281068)
18 #define PVC_GT0_PLATFORM_ENERGY_STATUS XE_REG(0x28106c)
19 #define PVC_GT0_PACKAGE_POWER_SKU XE_REG(0x281080)
21 #define BMG_FAN_1_SPEED XE_REG(0x138140)
22 #define BMG_FAN_2_SPEED XE_REG(0x138170)
23 #define BMG_FAN_3_SPEED XE_REG(0x1381a0)
24 #define BMG_VRAM_TEMPERATURE XE_REG(0x1382c0)
25 #define BMG_PACKAGE_TEMPERATURE XE_REG(0x138434)
H A Dxe_mchbar_regs.h21 #define PCU_CR_PACKAGE_POWER_SKU XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5930)
30 #define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
35 #define PCU_CR_PACKAGE_ENERGY_STATUS XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x593c)
37 #define PCU_CR_PACKAGE_TEMPERATURE XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5978)
40 #define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
/linux/drivers/gpu/drm/xe/
H A Dxe_gt_sriov_pf_service_types.h11 struct xe_reg;
32 const struct xe_reg *regs;
H A Dxe_hw_engine.h79 void xe_hw_engine_mmio_write32(struct xe_hw_engine *hwe, struct xe_reg reg, u32 val);
80 u32 xe_hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg);
H A Dxe_reg_sr_types.h15 struct xe_reg reg;
H A Dxe_force_wake.c32 struct xe_reg reg, struct xe_reg ack) in init_domain()
H A Dxe_nvm.c50 return !(xe_mmio_read32(mmio, XE_REG(GEN12_CNTL_PROTECTED_NVM_REG)) & in xe_nvm_non_posted_erase()
H A Dxe_gt_throttle.c87 struct xe_reg reg; in xe_gt_throttle_get_limit_reasons()
H A Dxe_guc_ads.c708 struct xe_reg reg, in guc_mmio_regset_write_one()
744 struct xe_reg reg; in guc_mmio_regset_write()
H A Dxe_oa.c64 struct xe_reg addr;
392 struct xe_reg oaheadptr = __oa_regs(stream)->oa_head_ptr; in xe_oa_append_reports()
2129 static const struct xe_reg flex_eu_regs[] = { in xe_oa_is_valid_flex_addr()
2276 oa_regs[i].addr = XE_REG(addr); in xe_oa_alloc_regs()
H A Dxe_gt_sriov_vf.c965 u32 xe_gt_sriov_vf_read32(struct xe_gt *gt, struct xe_reg reg) in xe_gt_sriov_vf_read32()
1000 void xe_gt_sriov_vf_write32(struct xe_gt *gt, struct xe_reg reg, u32 val) in xe_gt_sriov_vf_write32()
H A Dxe_gt.c238 struct xe_reg reg = entry->reg; in emit_wa_job()
H A Dxe_pci.c517 struct xe_reg gmdid_reg = GMD_ID; in read_gmdid()
H A Dxe_wa.c116 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)