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/linux/drivers/watchdog/
H A Dnpcm_wdt.c1 // SPDX-License-Identifier: GPL-2.0
57 struct npcm_wdt *wdt = to_npcm_wdt(wdd); in npcm_wdt_ping() local
60 val = readl(wdt->reg); in npcm_wdt_ping()
61 writel(val | NPCM_WTR, wdt->reg); in npcm_wdt_ping()
68 struct npcm_wdt *wdt = to_npcm_wdt(wdd); in npcm_wdt_start() local
71 if (wdt->clk) in npcm_wdt_start()
72 clk_prepare_enable(wdt->clk); in npcm_wdt_start()
74 if (wdd->timeout < 2) in npcm_wdt_start()
76 else if (wdd->timeout < 3) in npcm_wdt_start()
78 else if (wdd->timeout < 6) in npcm_wdt_start()
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H A Dkeembay_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Watchdog driver for Intel Keem Bay non-secure watchdog.
8 #include <linux/arm-smccc.h>
20 /* Non-secure watchdog register offsets */
40 static unsigned int timeout = WDT_TIMEOUT; variable
41 module_param(timeout, int, 0);
42 MODULE_PARM_DESC(timeout, "Watchdog timeout period in seconds (default = "
59 static inline u32 keembay_wdt_readl(struct keembay_wdt *wdt, u32 offset) in keembay_wdt_readl() argument
61 return readl(wdt->base + offset); in keembay_wdt_readl()
64 static inline void keembay_wdt_writel(struct keembay_wdt *wdt, u32 offset, u32 val) in keembay_wdt_writel() argument
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H A Dnic7018_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
33 static unsigned int timeout; variable
34 module_param(timeout, uint, 0);
35 MODULE_PARM_DESC(timeout,
36 "Watchdog timeout in seconds. (default="
63 return period * counter - period / 2; in nic7018_timeout()
66 static const struct nic7018_config *nic7018_get_config(u32 timeout, in nic7018_get_config() argument
72 if (timeout < 30 && timeout != 16) { in nic7018_get_config()
74 count = timeout / 2 + 1; in nic7018_get_config()
77 count = DIV_ROUND_UP(timeout + 16, 32); in nic7018_get_config()
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H A Dsl28cpld_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
36 static int timeout; variable
37 module_param(timeout, int, 0);
38 MODULE_PARM_DESC(timeout, "Initial watchdog timeout in seconds");
49 struct sl28cpld_wdt *wdt = watchdog_get_drvdata(wdd); in sl28cpld_wdt_ping() local
51 return regmap_write(wdt->regmap, wdt->offset + WDT_KICK, in sl28cpld_wdt_ping()
57 struct sl28cpld_wdt *wdt = watchdog_get_drvdata(wdd); in sl28cpld_wdt_start() local
61 if (wdt->assert_wdt_timeout) in sl28cpld_wdt_start()
66 return regmap_update_bits(wdt->regmap, wdt->offset + WDT_CTRL, in sl28cpld_wdt_start()
72 struct sl28cpld_wdt *wdt = watchdog_get_drvdata(wdd); in sl28cpld_wdt_stop() local
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H A Dbcm47xx_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2012-2013 Hauke Mehrtens <hauke@hauke-m.de>
31 static int timeout = WDT_DEFAULT_TIME; variable
34 module_param(timeout, int, 0);
35 MODULE_PARM_DESC(timeout, "Watchdog time in seconds. (default="
50 struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd); in bcm47xx_wdt_hard_keepalive() local
52 wdt->timer_set_ms(wdt, wdd->timeout * 1000); in bcm47xx_wdt_hard_keepalive()
64 struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd); in bcm47xx_wdt_hard_stop() local
66 wdt->timer_set(wdt, 0); in bcm47xx_wdt_hard_stop()
74 struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd); in bcm47xx_wdt_hard_set_timeout() local
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H A Dqcom-wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
54 static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg) in wdt_addr() argument
56 return wdt->base + wdt->layout[reg]; in wdt_addr()
76 struct qcom_wdt *wdt = to_qcom_wdt(wdd); in qcom_wdt_start() local
77 unsigned int bark = wdd->timeout - wdd->pretimeout; in qcom_wdt_start()
79 writel(0, wdt_addr(wdt, WDT_EN)); in qcom_wdt_start()
80 writel(1, wdt_addr(wdt, WDT_RST)); in qcom_wdt_start()
81 writel(bark * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME)); in qcom_wdt_start()
82 writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME)); in qcom_wdt_start()
83 writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN)); in qcom_wdt_start()
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H A Dmei_wdt.c1 // SPDX-License-Identifier: GPL-2.0
40 * enum mei_wdt_state - internal watchdog state
79 * struct mei_wdt - mei watchdog driver
88 * @timeout: watchdog current timeout
101 u16 timeout; member
109 * struct mei_mc_hdr - Management Control Command Header
124 * struct mei_wdt_start_request - watchdog start/ping
127 * @timeout: timeout value
132 u16 timeout; member
137 * struct mei_wdt_start_response - watchdog start/ping response
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H A Dda9062_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
26 #define DA9062_TWDSCALE_MAX (ARRAY_SIZE(wdt_timeout) - 1)
29 #define DA9062_WDG_DEFAULT_TIMEOUT wdt_timeout[DA9062_TWDSCALE_MAX-1]
38 static unsigned int da9062_wdt_read_timeout(struct da9062_watchdog *wdt) in da9062_wdt_read_timeout() argument
42 regmap_read(wdt->hw->regmap, DA9062AA_CONTROL_D, &val); in da9062_wdt_read_timeout()
59 static int da9062_reset_watchdog_timer(struct da9062_watchdog *wdt) in da9062_reset_watchdog_timer() argument
61 return regmap_update_bits(wdt->hw->regmap, DA9062AA_CONTROL_F, in da9062_reset_watchdog_timer()
66 static int da9062_wdt_update_timeout_register(struct da9062_watchdog *wdt, in da9062_wdt_update_timeout_register() argument
69 struct da9062 *chip = wdt->hw; in da9062_wdt_update_timeout_register()
71 regmap_update_bits(chip->regmap, in da9062_wdt_update_timeout_register()
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H A Dni903x_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
44 static unsigned int timeout; variable
45 module_param(timeout, uint, 0);
46 MODULE_PARM_DESC(timeout,
47 "Watchdog timeout in seconds. (default="
56 static void ni903x_start(struct ni903x_wdt *wdt) in ni903x_start() argument
58 u8 control = inb(wdt->io_base + NIWD_CONTROL); in ni903x_start()
60 outb(control | NIWD_CONTROL_RESET, wdt->io_base + NIWD_CONTROL); in ni903x_start()
61 outb(control | NIWD_CONTROL_PET, wdt->io_base + NIWD_CONTROL); in ni903x_start()
65 unsigned int timeout) in ni903x_wdd_set_timeout() argument
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H A Dmlx_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
30 * struct mlxreg_wdt - wd private data:
56 static void mlxreg_wdt_check_card_reset(struct mlxreg_wdt *wdt) in mlxreg_wdt_check_card_reset() argument
62 if (wdt->reset_idx == -EINVAL) in mlxreg_wdt_check_card_reset()
65 if (!(wdt->wdd.info->options & WDIOF_CARDRESET)) in mlxreg_wdt_check_card_reset()
68 reg_data = &wdt->pdata->data[wdt->reset_idx]; in mlxreg_wdt_check_card_reset()
69 rc = regmap_read(wdt->regmap, reg_data->reg, &regval); in mlxreg_wdt_check_card_reset()
71 if (regval & ~reg_data->mask) { in mlxreg_wdt_check_card_reset()
72 wdt->wdd.bootstatus = WDIOF_CARDRESET; in mlxreg_wdt_check_card_reset()
73 dev_info(wdt->wdd.parent, in mlxreg_wdt_check_card_reset()
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H A Dts4800_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Watchdog driver for TS-4800 based boards
5 * Copyright (c) 2015 - Savoir-faire Linux
36 * TS-4800 supports the following timeout values:
39 * ---------------------
45 * Keep the regmap/timeout map ordered by timeout
48 const int timeout; member
55 #define MAX_TIMEOUT_INDEX (ARRAY_SIZE(ts4800_wdt_map) - 1)
57 static void ts4800_write_feed(struct ts4800_wdt *wdt, u32 val) in ts4800_write_feed() argument
59 regmap_write(wdt->regmap, wdt->feed_offset, val); in ts4800_write_feed()
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H A Dimx7ulp_wdt.c1 // SPDX-License-Identifier: GPL-2.0
78 return -ETIMEDOUT; in imx7ulp_wdt_wait_ulk()
83 static int imx7ulp_wdt_wait_rcs(struct imx7ulp_wdt_device *wdt) in imx7ulp_wdt_wait_rcs() argument
86 u32 val = readl(wdt->base + WDOG_CS); in imx7ulp_wdt_wait_rcs()
87 u64 timeout = (val & WDOG_CS_PRES) ? in imx7ulp_wdt_wait_rcs() local
93 readl_poll_timeout(wdt->base + WDOG_CS, val, val & WDOG_CS_RCS, 100, in imx7ulp_wdt_wait_rcs()
94 timeout)) in imx7ulp_wdt_wait_rcs()
95 ret = -ETIMEDOUT; in imx7ulp_wdt_wait_rcs()
98 if (wdt->hw->post_rcs_wait) in imx7ulp_wdt_wait_rcs()
104 static int _imx7ulp_wdt_enable(struct imx7ulp_wdt_device *wdt, bool enable) in _imx7ulp_wdt_enable() argument
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H A Dmax63xx_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
47 const struct max63xx_timeout *timeout; member
54 void (*ping)(struct max63xx_wdt *wdt);
55 void (*set)(struct max63xx_wdt *wdt, u8 set);
59 * The timeout values used are actually the absolute minimum the chip
61 * (10s setting ends up with a 25s timeout), and can be up to 3 times
67 * I also decided to remove from the tables any timeout smaller than a
103 while (table->twd) { in max63xx_select_timeout()
104 if (value <= table->twd) { in max63xx_select_timeout()
105 if (nodelay && table->tdelay == 0) in max63xx_select_timeout()
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H A Dlantiq_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
6 * Based on EP93xx wdt driver
33 * The password sequence protects the WDT control register from unintended
34 * write actions, which might cause malfunction of the WDT.
37 * IO access to the WDT core
44 /* Pre-warning limit set to 1/16 of max WDT period */
49 #define LTQ_WDT_CR_MAX_TIMEOUT ((1 << 16) - 1) /* The reload field is 16 bit */
63 struct watchdog_device wdt; member
70 return __raw_readl(priv->membase + offset); in ltq_wdt_r32()
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H A Dsama5d4_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2015-2019 Microchip Technology Inc. and its subsidiaries
21 /* minimum and maximum watchdog timeout, in seconds */
26 #define WDT_SEC2TICKS(s) ((s) ? (((s) << 8) - 1) : 0)
43 "Watchdog timeout in seconds. (default = "
51 #define wdt_enabled (!(wdt->mr & AT91_WDT_WDDIS))
53 #define wdt_read(wdt, field) \ argument
54 readl_relaxed((wdt)->reg_base + (field))
59 static void wdt_write(struct sama5d4_wdt *wdt, u32 field, u32 val) in wdt_write() argument
66 while (time_before(jiffies, wdt->last_ping + WDT_DELAY)) in wdt_write()
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H A Darmada_37xx_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
35 * Counters ID 2 and 3 are enabled by default even before U-Boot loads,
66 static unsigned int timeout; variable
67 module_param(timeout, int, 0);
68 MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds");
76 struct watchdog_device wdt; member
79 u64 timeout; /* in clock ticks */ member
89 * when low is read, high is latched into flip-flops so that it can be in get_counter_value()
92 val = readl(dev->reg + CNTR_COUNT_LOW(id)); in get_counter_value()
93 val |= ((u64)readl(dev->reg + CNTR_COUNT_HIGH(id))) << 32; in get_counter_value()
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H A Dsprd_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2017 Spreadtrum - http://www.spreadtrum.com
84 struct sprd_wdt *wdt = (struct sprd_wdt *)dev_id; in sprd_wdt_isr() local
86 sprd_wdt_unlock(wdt->base); in sprd_wdt_isr()
87 writel_relaxed(SPRD_WDT_INT_CLEAR_BIT, wdt->base + SPRD_WDT_INT_CLR); in sprd_wdt_isr()
88 sprd_wdt_lock(wdt->base); in sprd_wdt_isr()
89 watchdog_notify_pretimeout(&wdt->wdd); in sprd_wdt_isr()
93 static u32 sprd_wdt_get_cnt_value(struct sprd_wdt *wdt) in sprd_wdt_get_cnt_value() argument
97 val = readl_relaxed(wdt->base + SPRD_WDT_CNT_HIGH) << in sprd_wdt_get_cnt_value()
99 val |= readl_relaxed(wdt->base + SPRD_WDT_CNT_LOW) & in sprd_wdt_get_cnt_value()
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H A Ddigicolor_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
30 static unsigned timeout; variable
31 module_param(timeout, uint, 0);
32 MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds");
34 static void dc_wdt_set(struct dc_wdt *wdt, u32 ticks) in dc_wdt_set() argument
38 spin_lock_irqsave(&wdt->lock, flags); in dc_wdt_set()
40 writel_relaxed(0, wdt->base + TIMER_A_CONTROL); in dc_wdt_set()
41 writel_relaxed(ticks, wdt->base + TIMER_A_COUNT); in dc_wdt_set()
43 wdt->base + TIMER_A_CONTROL); in dc_wdt_set()
45 spin_unlock_irqrestore(&wdt->lock, flags); in dc_wdt_set()
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H A Dsp805_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/char/watchdog/sp805-wdt.c
34 /* default timeout in seconds */
37 #define MODULE_NAME "sp805-wdt"
58 * struct sp805_wdt: sp805 wdt device structure
61 * @base: base address of wdt
62 * @clk: (optional) clock structure of wdt
64 * @adev: amba device structure of wdt
65 * @status: current status of wdt
66 * @load_val: load value to be set for current timeout
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H A Dcadence_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence WDT driver - Used by Xilinx Zynq
5 * Copyright (C) 2010 - 2014 Xilinx, Inc.
21 /* Supports 1 - 516 sec */
63 * struct cdns_wdt - Watchdog device structure
85 static inline void cdns_wdt_writereg(struct cdns_wdt *wdt, u32 offset, u32 val) in cdns_wdt_writereg() argument
87 writel_relaxed(val, wdt->regs + offset); in cdns_wdt_writereg()
92 /* Register Offsets for the WDT */
99 * Zero Mode Register - This register controls how the time out is indicated
102 #define CDNS_WDT_ZMR_WDEN_MASK 0x00000001 /* Enable the WDT */
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H A Drn5t618_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #define DRIVER_NAME "rn5t618-wdt"
17 static unsigned int timeout; variable
19 module_param(timeout, uint, 0);
20 MODULE_PARM_DESC(timeout, "Initial watchdog timeout in seconds");
50 struct rn5t618_wdt *wdt = watchdog_get_drvdata(wdt_dev); in rn5t618_wdt_set_timeout() local
59 return -EINVAL; in rn5t618_wdt_set_timeout()
61 ret = regmap_update_bits(wdt->rn5t618->regmap, RN5T618_WATCHDOG, in rn5t618_wdt_set_timeout()
65 wdt_dev->timeout = rn5t618_wdt_map[i].time; in rn5t618_wdt_set_timeout()
72 struct rn5t618_wdt *wdt = watchdog_get_drvdata(wdt_dev); in rn5t618_wdt_start() local
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H A Dbcm7038_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
41 * peripheral registers for CPU-native byte order. in bcm7038_wdt_write()
59 struct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog); in bcm7038_wdt_set_timeout_reg() local
60 u32 timeout; in bcm7038_wdt_set_timeout_reg() local
62 timeout = wdt->rate * wdog->timeout; in bcm7038_wdt_set_timeout_reg()
64 bcm7038_wdt_write(timeout, wdt->base + WDT_TIMEOUT_REG); in bcm7038_wdt_set_timeout_reg()
69 struct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog); in bcm7038_wdt_ping() local
71 bcm7038_wdt_write(WDT_START_1, wdt->base + WDT_CMD_REG); in bcm7038_wdt_ping()
72 bcm7038_wdt_write(WDT_START_2, wdt->base + WDT_CMD_REG); in bcm7038_wdt_ping()
87 struct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog); in bcm7038_wdt_stop() local
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H A Dat91sam9_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2008 Renaud CERRATO r.cerrato@til-technologies.fr
11 * timeout need to be set from Linux, be sure that the bootstrap or the
40 #define wdt_read(wdt, field) \ argument
41 readl_relaxed((wdt)->base + (field))
43 writel_relaxed((val), (wdt)->base + (field))
52 #define secs_to_ticks(s) ((s) ? (((s) << 8) - 1) : 0)
62 /* Hardware timeout in seconds */
68 /* User land timeout */
88 unsigned long heartbeat; /* WDT heartbeat in jiffies */
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H A Dimgpdc_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
11 * -----
12 * The timeout value is rounded to the next power of two clock cycles.
16 * timeout = 2^(delay + 1) clock cycles
22 * guarantees that the actual watchdog timeout will be _at least_ the value
25 * The following table shows how the user-configured timeout relates
26 * to the actual hardware timeout (watchdog clock @ 40000 Hz):
28 * input timeout | WD_DELAY | actual timeout
29 * -----------------------------------
37 * clock rate and achieve a finer timeout granularity.
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/linux/drivers/platform/cznic/
H A Dturris-omnia-mcu-watchdog.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/turris-omnia-mcu-interface.h>
17 #include "turris-omnia-mcu.h"
21 static unsigned int timeout; variable
22 module_param(timeout, int, 0);
23 MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds");
30 static int omnia_wdt_start(struct watchdog_device *wdt) in omnia_wdt_start() argument
32 struct omnia_mcu *mcu = watchdog_get_drvdata(wdt); in omnia_wdt_start()
34 return omnia_cmd_write_u8(mcu->client, OMNIA_CMD_SET_WATCHDOG_STATE, 1); in omnia_wdt_start()
37 static int omnia_wdt_stop(struct watchdog_device *wdt) in omnia_wdt_stop() argument
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