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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoV.td427 // op vd, vs2, vs1, vm
430 (ins VR:$vs2, VR:$vs1, VMaskOp:$vm),
431 opcodestr, "$vd, $vs2, $vs1$vm">;
433 // op vd, vs2, vs1, v0 (without mask, use v0 as carry input)
436 (ins VR:$vs2, VR:$vs1, VMV0:$v0),
437 opcodestr, "$vd, $vs2, $vs1, v0"> {
441 // op vd, vs1, vs2, vm (reverse the order of vs1 and vs2)
445 (ins VR:$vd, VR:$vs1, VR:$vs2, VMaskOp:$vm),
446 opcodestr, "$vd, $vs1, $vs2$vm"> {
451 // op vd, vs2, vs1
[all …]
H A DRISCVInstrFormatsV.td111 bits<5> vs1;
118 let Inst{19-15} = vs1;
186 class RVInstV<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, dag outs,
196 let Inst{19-15} = vs1;
H A DRISCVInstrInfoZvk.td61 // op vd, vs2, vs1
67 // op vd, vs2, vs1
70 (ins VR:$vd, VR:$vs2, VR:$vs1),
71 opcodestr, "$vd, $vs2, $vs1"> {
95 // op vd, vs2 (use vs1 as instruction encoding) where vd is also a source
97 class PALUVs2NoVmBinary<bits<6> funct6, bits<5> vs1, RISCVVFormat opv,
99 : RVInstV<funct6, vs1, opv, (outs VR:$vd_wb), (ins VR:$vd, VR:$vs2),
106 multiclass VAES_MV_V_S<bits<6> funct6_vv, bits<6> funct6_vs, bits<5> vs1,
109 def NAME # _VV : PALUVs2NoVmBinary<funct6_vv, vs1, opv, opcodestr # ".vv">,
112 def NAME # _VS : PALUVs2NoVmBinary<funct6_vs, vs1, opv, opcodestr # ".vs">,
H A DRISCVInstrInfoXTHead.td58 // op vd, vs1, vs2, vm (reverse the order of vs1 and vs2)
62 (ins VR:$vd, VR:$vs1, VR:$vs2, VMaskOp:$vm),
63 opcodestr, "$vd, $vs1, $vs2$vm"> {
/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-pm8941.dtsi224 interrupt-names = "ocp-5vs1", "ocp-5vs2";
233 pm8941_5vs1: 5vs1 {
H A Dqcom-msm8974pro-samsung-klte.dts638 pma8084_5vs1: 5vs1 {};
H A Dqcom-apq8084.dtsi848 pma8084_5vs1: 5vs1 {};
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dqcom,smd-rpm-regulator.yaml55 lvs3, 5vs1, 5vs2
71 l20, l21, l22, l23, l24, l25, l26, l27, lvs1, lvs2, lvs3, lvs4, 5vs1
H A Dqcom,smd-rpm-regulator.txt255 lvs3, 5vs1, 5vs2
270 l21, l22, l23, l24, l25, l26, l27, lvs1, lvs2, lvs3, lvs4, 5vs1
H A Dmediatek,mt6357-regulator.yaml99 mt6357_vs1_reg: buck-vs1 {
100 regulator-name = "vs1";
H A Dqcom,spmi-regulator.yaml280 - const: ocp-5vs1
H A Dqcom,spmi-regulator.txt212 5vs1, 5vs2
H A Dmt6358-regulator.txt100 regulator-name = "vs1";
H A Dmt6359-regulator.yaml108 regulator-name = "vs1";
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt6357.dtsi40 mt6357_vs1_reg: buck-vs1 {
41 regulator-name = "vs1";
H A Dmt6359.dtsi17 regulator-name = "vs1";
H A Dmt6358.dtsi99 regulator-name = "vs1";
/freebsd/sys/contrib/openzfs/module/zfs/
H A Dspa_stats.c410 vdev_get_stats(spa->spa_root_vdev, &ts->vs1); in spa_txg_history_init_io()
438 ts->vs2.vs_bytes[ZIO_TYPE_READ] - ts->vs1.vs_bytes[ZIO_TYPE_READ], in spa_txg_history_fini_io()
439 ts->vs2.vs_bytes[ZIO_TYPE_WRITE] - ts->vs1.vs_bytes[ZIO_TYPE_WRITE], in spa_txg_history_fini_io()
440 ts->vs2.vs_ops[ZIO_TYPE_READ] - ts->vs1.vs_ops[ZIO_TYPE_READ], in spa_txg_history_fini_io()
441 ts->vs2.vs_ops[ZIO_TYPE_WRITE] - ts->vs1.vs_ops[ZIO_TYPE_WRITE], in spa_txg_history_fini_io()
/freebsd/sys/dev/ntb/test/
H A Dntb_tool.c457 bool vs1, vs2, vs3; in parse_mw_buf() local
460 vs1 = vs2 = vs3 = false; in parse_mw_buf()
469 vs1 = true; in parse_mw_buf()
478 if (!vs1 && !strcmp(op2, "offset")) { in parse_mw_buf()
480 vs1 = true; in parse_mw_buf()
489 if (!vs1 && !strcmp(op3, "offset")) { in parse_mw_buf()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCScheduleP7.td
H A DPPCInstrMMA.td1061 $vs1, sub_vsx0));
1083 def : Pat<(v512i1 (PPCAccBuild v4i32:$vs1, v4i32:$vs0, v4i32:$vs3, v4i32:$vs2)),
1085 def : Pat<(v512i1 (int_ppc_mma_assemble_acc v16i8:$vs1, v16i8:$vs0,
1100 def : Pat<(v512i1 (PPCAccBuild v4i32:$vs1, v4i32:$vs0, v4i32:$vs3, v4i32:$vs2)),
1102 def : Pat<(v512i1 (int_ppc_mma_assemble_acc v16i8:$vs1, v16i8:$vs0,
H A DPPCInstrP10.td1138 $vs1, sub_vsx0));
1146 def : Pat<(v256i1 (PPCPairBuild v4i32:$vs1, v4i32:$vs0)),
1148 def : Pat<(v256i1 (int_ppc_vsx_assemble_pair v16i8:$vs1, v16i8:$vs0)),
/freebsd/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DRegisterInfos_ppc64le.h210 DEFINE_VSX(vs1, LLDB_INVALID_REGNUM), \
395 uint32_t vs1[4]; member
/freebsd/contrib/llvm-project/clang/lib/Sema/
H A DSemaRISCV.cpp779 // bit_27_26, bit_11_7, vs2, xs1/vs1 in CheckBuiltinFunctionCall()
794 // bit_27_26, vs2, xs1/vs1 in CheckBuiltinFunctionCall()
803 // bit_27_26, vd, vs2, xs1/vs1 in CheckBuiltinFunctionCall()
/freebsd/contrib/llvm-project/clang/lib/Basic/Targets/
H A DPPC.cpp863 {{"vs0"}, 32}, {{"vs1"}, 33}, {{"vs2"}, 34}, {{"vs3"}, 35},

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