Home
last modified time | relevance | path

Searched +full:tx +full:- +full:threshold (Results 1 – 25 of 175) sorted by relevance

1234567

/illumos-gate/usr/src/uts/common/io/udmf/
H A Ddm9601reg.h15 #define TCR 0x02U /* tx control register */
16 #define TSR1 0x03U /* tx status register 1 */
17 #define TSR2 0x04U /* tx status register 2 */
21 #define BPTR 0x08U /* back pressure threshold regster */
22 #define FCTR 0x09U /* flow control threshold regster */
23 #define FCR 0x0aU /* flow control threshold regster */
37 #define TUSC 0xf2U /* tx packet counter/usb status register */
68 #define NSR_TXFULL 0x10U /* 1:tx fifo full */
69 #define NSR_TX2END 0x08U /* tx packet2 complete status */
70 #define NSR_TX1END 0x04U /* tx packet1 complete status */
[all …]
/illumos-gate/usr/src/uts/common/io/igc/core/
H A Digc_regs.h1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
11 #define IGC_CTRL 0x00000 /* Device Control - RW */
12 #define IGC_STATUS 0x00008 /* Device Status - RO */
13 #define IGC_EECD 0x00010 /* EEPROM/Flash Control - RW */
15 #define IGC_EERD 0x12014 /* EEprom mode read - RW */
16 #define IGC_EEWR 0x12018 /* EEprom mode write - RW */
17 #define IGC_CTRL_EXT 0x00018 /* Extended Device Control - RW */
18 #define IGC_MDIC 0x00020 /* MDI Control - RW */
19 #define IGC_MDICNFG 0x00E04 /* MDI Config - RW */
[all …]
H A Digc_defines.h1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
72 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
89 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */
128 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
129 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
215 #define IGC_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
217 #define IGC_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
279 /* 1000/H is not supported, nor spec-compliant. */
325 #define IGC_TCTL_EN 0x00000002 /* enable Tx */
[all …]
/illumos-gate/usr/src/grub/grub-0.97/netboot/
H A Depic100.h30 LAN0 = 0x40, /* MAC address. (0x40-0x48) */
32 MC0 = 0x50, /* Multicast filter table. (0x50-0x5c) */
38 PRCPTHR= 0xB0, /* PCI Receive Copy Threshold */
40 ETHTHR = 0xDC /* Early Transmit Threshold */
55 #define INTR_RX_THR_STA (0x00400000) /* rx copy threshold status NI */
57 #define INTR_TX_IN_PROG (0x00100000) /* tx copy in progess. NI */
59 #define INTR_TXIDLE (0x00040000) /* tx idle. NI */
67 #define INTR_RX_THR_CROSSED (0x00000400) /* rx copy threshold crossed */
69 #define INTR_TXUNDERRUN (0x00000100) /* tx underrun. */
70 #define INTR_TXEMPTY (0x00000080) /* tx queue empty */
[all …]
H A De1000_hw.h4 Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
291 /* MAC decode size is 128K - This is the size of BAR0 */
309 (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
311 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
330 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
341 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
355 * E1000_RAR_ENTRIES - 1 multicast addresses.
379 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
[all …]
/illumos-gate/usr/src/uts/common/io/e1000api/
H A De1000_regs.h3 Copyright (c) 2001-2015, Intel Corporation
38 #define E1000_CTRL 0x00000 /* Device Control - RW */
39 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
40 #define E1000_STATUS 0x00008 /* Device Status - RO */
41 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
42 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
43 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
44 #define E1000_FLA 0x0001C /* Flash Access - RW */
45 #define E1000_MDIC 0x00020 /* MDI Control - RW */
46 #define E1000_MDICNFG 0x00E04 /* MDI Config - RW */
[all …]
H A De1000_defines.h3 Copyright (c) 2001-2015, Intel Corporation
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
173 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
174 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
263 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
265 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
341 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
342 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
344 /* Constants used to interpret the masked PCI-X bus speed. */
[all …]
H A De1000_82575.h3 Copyright (c) 2001-2015, Intel Corporation
46 * These entries are also used for MAC-based filtering.
193 /* Receive Descriptor - Advanced */
265 #define E1000_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */
281 /* Transmit Descriptor - Advanced */
312 /* 1st & Last TSO-full iSCSI PDU*/
345 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */
346 #define E1000_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wbk flushing */
347 /* Tx Queue Arbitration Priority 0=low, 1=high */
367 #define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
[all …]
/illumos-gate/usr/src/uts/common/io/ral/
H A Dral_rate.h43 * Data-rate adaptation loosely based on "Link Adaptation Strategy
48 /* Buckets for frames 0-128 bytes long, 129-1024, 1025-maximum. */
54 (ral_rssadapt_thresh_denom - ral_rssadapt_thresh_old)
56 (ral_rssadapt_decay_denom - ral_rssadapt_decay_old)
58 (ral_rssadapt_avgrssi_denom - ral_rssadapt_avgrssi_old)
61 /* RSS threshold decay. */
64 /* RSS threshold update. */
75 /* Tx failures in this update interval */
77 /* Tx successes in this update interval */
81 /* RSSI threshold for each Tx rate */
[all …]
/illumos-gate/usr/src/uts/common/sys/
H A Dmac_soft_ring.h60 /* Tx notify callback */
82 * Threshold after which packets get dropped.
91 uint32_t s_ring_hiwat_cnt; /* times blocked for Tx descs */
96 /* Tx notify callback */
131 /* Members for Tx size processing */
136 mac_group_t *st_group; /* TX group for share */
140 * st_max_q_cnt is the queue depth threshold to limit
141 * outstanding packets on the Tx SRS. Once the limit
142 * is reached, Tx SRS will drop packets until the
143 * limit goes below the threshold.
[all …]
/illumos-gate/usr/src/uts/common/io/mxfe/
H A Dmxfe.h15 * 3. Neither the name of the author nor the names of any co-contributors
69 #define PCI_CMD_MWIE 0x0010 /* memory write-invalidate enable */
86 #define CSR_TSTAT 0x60 /* 10Base-T status */
88 #define CSR_TCTL 0x70 /* 10Base-T control */
92 #define CSR_TXBR 0x9c /* Transmit burst counter/time-out register */
101 #define PAR_MWIE 0x01000000U /* PCI memory-write-invalidate */
102 #define PAR_MRLE 0x00800000U /* PCI memory-read-line */
103 #define PAR_MRME 0x00200000U /* PCI memory-read-multiple */
107 #define PAR_TXAUTOPOLL 0x00060000U /* Programmable TX autopoll interval */
131 #define INT_100LINK 0x08000000U /* 100 Base-T link */
[all …]
/illumos-gate/usr/src/uts/common/io/yge/
H A Dyge.h12 * are provided to you under the BSD-type license terms provided
17 * - Redistributions of source code must retain the above copyright
19 * - Redistributions in binary form must reproduce the above
23 * - Neither the name of Marvell nor the names of its contributors
57 * D-Link PCI vendor ID
91 * D-Link gigabit ethernet device ID
133 #define PCI_Y2_PIG_ENA BIT(31) /* Enable Plug-in-Go (YUKON-2) */
134 #define PCI_Y2_DLL_DIS BIT(30) /* Disable PCI DLL (YUKON-2) */
135 #define PCI_Y2_PHY2_COMA BIT(29) /* Set PHY 2 to Coma Mode (YUKON-2) */
136 #define PCI_Y2_PHY1_COMA BIT(28) /* Set PHY 1 to Coma Mode (YUKON-2) */
[all …]
/illumos-gate/usr/src/uts/common/io/igb/
H A Digb_sw.h23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
101 #define IGB_ADAPTER_MSIXTAB 4 /* mapping msi-x table */
103 #define IGB_NO_POLL -1
104 #define IGB_NO_FREE_SLOT -1
113 * these per msi-x vector and it needs to be the maximum of all silicon
233 IOC_INVAL = -1, /* bad, NAK with EINVAL */
240 * For s/w context extraction from a tx frame
243 #define TX_CXT_E_LSO_CSUM (-1)
244 #define TX_CXT_E_ETHER_TYPE (-2)
246 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \
[all …]
/illumos-gate/usr/src/uts/common/io/ixgbe/
H A Dixgbe_sw.h23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
103 #define IXGBE_POLL_NULL -1
108 #define IXGBE_TX_DESC_LIMIT 32 /* tx desc limitation */
217 #define ATTACH_PROGRESS_OVERTEMP_TASKQ 0x10000 /* Over-temp taskq created */
279 /* adapter-specific info for each supported device type */
287 uint32_t max_tx_que_num; /* maximum number of tx queues */
288 uint32_t min_tx_que_num; /* minimum number of tx queues */
289 uint32_t def_tx_que_num; /* default number of tx queues */
306 /* bits representing all interrupt types other than tx & rx */
311 IOC_INVAL = -1, /* bad, NAK with EINVAL */
[all …]
/illumos-gate/usr/src/uts/common/io/efe/
H A Defe.h76 #define CSR_NVCTL 0x10 /* Non-volatile Control Register */
116 #define CSR_PRCPTHR 0xB0 /* PCI Receive Copy Threshold Register */
126 #define CSR_ETXTHR 0xDC /* PCI Early Transmit Threshold Register */
141 #define COMMAND_TXQUEUED (1UL << 2) /* Queue TX Descriptor */
144 #define COMMAND_STOP_TDMA (1UL << 5) /* Stop TX DMA */
159 #define INTSTAT_RCT (1UL << 11) /* Receive Copy Threshold */
169 #define INTSTAT_RCTS (1UL << 22) /* Receive Copy Threshold Status */
187 #define INTMASK_RCT (1UL << 11) /* Receive Copy Threshold */
200 #define GENCTL_RFT_32 (0UL << 8) /* Receive FIFO Threshold (1/4) */
201 #define GENCTL_RFT_64 (1UL << 8) /* Receive FIFO Threshold (1/2) */
[all …]
/illumos-gate/usr/src/uts/common/io/rtw/
H A Drtwreg.h54 #define BITS(m, n) ((BIT(MAX((m), (n)) + 1) - 1) ^ (BIT(MIN((m), (n))) - 1))
59 #define LOWEST_SET_BIT(x) ((((x) - 1) & (x)) ^ (x))
62 * for x a power of two and p a non-negative integer, is x a greater
100 * Auto-loaded from EEPROM. Read by byte, by word, or by double word,
111 * low word, 32b, read-only.
114 #define RTW_TSFTRH 0x1c /* High word, 32b, read-only. */
117 * 32b, 256-byte alignment.
122 * 32b, 256-byte alignment.
127 * 32b, 256-byte alignment.
174 * is active with 1. After power-up, host
[all …]
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/fw/
H A D5710_hsi.h61 …<23) /* BitField agg_vars1Various aggregative variables 0-NOP, 1-EQ, 2-NEQ, 3-GT, 4-GE, 5-LS, 6-LE…
63 … (0x3<<26) /* BitField agg_vars1Various aggregative variables 0-NOP, 1-EQ, 2-NEQ */
65 … (0x3<<28) /* BitField agg_vars1Various aggregative variables 0-NOP, 1-EQ, 2-NEQ */
67 … (0x3<<30) /* BitField agg_vars1Various aggregative variables 0-NOP, 1-EQ, 2-NEQ */
79 u32_t rel_seq_th /* The threshold for the released sequence */;
139 u32_t __rel_seq_threshold /* The threshold for the released sequence */;
189 …/* BitField opcode Whether the source is the PCIe or the GRC. 0- The source is the PCIe 1- The sou…
191 … (0x3<<1) /* BitField opcode The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */
193 … (0x1<<3) /* BitField opcode The destination of the completion: 0-PCIe 1-GRC */
195 …to write a completion word to the completion destination: 0-Do not write a completion word 1-Write…
[all …]
/illumos-gate/usr/src/uts/common/io/xge/hal/include/
H A Dxgehal-config.h21 * Copyright (c) 2002-2006 Neterion, Inc.
27 #include "xge-os-pal.h"
28 #include "xgehal-types.h"
29 #include "xge-queue.h"
33 #define XGE_HAL_DEFAULT_USE_HARDCODE -1
40 * struct xge_hal_tti_config_t - Xframe Tx interrupt configuration.
59 * @timer_ac_en: Enable auto-cancel. That is, reset the timer if utilization
127 * struct xge_hal_rti_config_t - Xframe Rx interrupt configuration.
139 * @timer_ac_en: Enable auto-cancel. That is, reset the timer if utilization
196 * struct xge_hal_fifo_queue_t - Single fifo configuration.
[all …]
H A Dxgehal-types.h21 * Copyright (c) 2002-2006 Neterion, Inc.
27 #include "xge-os-pal.h"
32 * BIT(loc) - set bit at offset
37 * vBIT(val, loc, sz) - set bits at offset
39 #define vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz)))
40 #define vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz)))
43 * bVALx(bits, loc) - Get the value of x bits at location
45 #define bVAL1(bits, loc) ((((u64)bits) >> (64-(loc+1))) & 0x1)
46 #define bVAL2(bits, loc) ((((u64)bits) >> (64-(loc+2))) & 0x3)
47 #define bVAL3(bits, loc) ((((u64)bits) >> (64-(loc+3))) & 0x7)
[all …]
/illumos-gate/usr/src/uts/common/io/igc/
H A Digc.h49 * Maximum number of RX and TX rings that it appears the hardware supports. The
63 * These are the default auto-negotiation values the device supports which is
78 * threshold for rx mostly by surveying others. For tx, we picked 512 as that's
89 * These numbers deal with the tx ring, blocking, recycling, and notification
95 * than 1% of the default ring size. We picked a default recycle threshold
96 * check during tx of 32, which is about 6.25% of the default ring size.
116 * 4-byte aligned.
121 * The buffer sizes that hardware uses for rx and tx are required to be 1 KiB
130 #define IGC_RX_POLL_INTR -1
143 #define IGC_DMA_SYNC(buf, flag) ASSERT0(ddi_dma_sync((buf)->idb_hdl, \
[all …]
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/mcp/
H A Ddev_info.h94 /* Up to 16 bytes of NULL-terminated string */
113 (if multiple found, priority order is: NC-SI, UMP, IPMI) */
118 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
119 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
121 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
122 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
124 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
125 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
128 /* Adjust the PCIe G2 Tx amplitude driver for all Tx lanes. For
255 /* Reserved bits: 226-230 */
[all …]
/illumos-gate/usr/src/uts/common/io/bnxe/
H A Dbnxe.conf35 # All configuration can be specified per-instance. The format used is as
56 # adv_autoneg_cap - advertise autonegotiation mode
57 # - default enabled
58 # - 0 = disabled / 1 = enabled
63 # adv_20000fdx_cap - advertise 20Gbps full duplex
64 # - ignored for serdes devices
65 # - default enabled
66 # - 0 = disable / 1 = enable
71 # adv_10000fdx_cap - advertise 10Gbps full duplex
72 # - ignored for serdes devices
[all …]
/illumos-gate/usr/src/uts/common/io/sfe/
H A Dsfereg.h4 * Copyright (c) 2002-2007 Masayuki Murayama. All rights reserved.
37 * Tx/Rx descriptor
141 #define PMEVT 0xb4 /* Power management wake-up event reg */
142 #define WAKECRC 0xbc /* Wake-up sample frame CRC register */
143 #define WAKEMASK 0xc0 /* Wake-up sample frame mask register */
178 #define CFG_ANEG_SEL 0x0000e000U /* Auto-nego default (83815) */
327 #define TXCFG_FLTH 0x00003f00U /* Tx fill threshold */
329 #define TXCFG_DRTH 0x0000003fU /* Tx drain threshold */
352 #define RXCFG_DRTH 0x0000003eU /* Rx drain threshold */
/illumos-gate/usr/src/uts/common/io/qede/579xx/drivers/ecore/hsi_repository/
H A Dstorage_common.h9 * or http://opensource.org/licenses/CDDL-1.0.
23 * Copyright 2014-2017 Cavium, Inc.
30 * at http://opensource.org/licenses/CDDL-1.0
44 // Each Resource ID is one-one-valued mapped by the driver to a BDQ Resource ID (for instance per p…
103 __le16 cmdq_cons /* CMDQ consumer - updated by driver when CMDQ is consumed */;
130 …_resource_id /* Each function-init Ramrod maps its funciton ID to a BDQ function ID, each BDQ func…
148 …__le16 bdq_xoff_threshold[BDQ_NUM_IDS] /* BDQ XOFF threshold - when number of entries will be belo…
149 …__le16 bdq_xon_threshold[BDQ_NUM_IDS] /* BDQ XON threshold - when number of entries will be above …
150 …__le16 cmdq_xoff_threshold /* CMDQ XOFF threshold - when number of entries will be below that TH, …
151 …__le16 cmdq_xon_threshold /* CMDQ XON threshold - when number of entries will be above that TH, it…
[all …]
/illumos-gate/usr/src/uts/common/io/mwl/
H A Dmwl_reg.h7 * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting
8 * Copyright (c) 2007-2009 Marvell Semiconductor, Inc.
47 #define MWL_MBSS_SUPPORT /* enable multi-bss support */
54 * Define total number of TX queues in the shared memory.
70 #define MAX_TXWCB_QUEUES TOTAL_TX_QUEUES - NUM_ACK_EVENT_QUEUE
80 #define MWL_ANT_INFO_SUPPORT /* per-antenna data in rx descriptor */
209 * @11E-BA@
292 uint8_t rsvd3[3]; /* Reserved - To make word aligned */
296 * Hardware tx/rx descriptors.
298 * NB: tx descriptor size must match f/w expected size
[all …]

1234567