| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_udma_regs_gen.h | 9 found at http://www.gnu.org/licenses/gpl-2.0.html
100 /* [0x0] Target-ID control */
102 /* [0x4] TX queue 0/1 Target-ID */
104 /* [0x8] TX queue 2/3 Target-ID */
106 /* [0xc] RX queue 0/1 Target-ID */
108 /* [0x10] RX queue 2/3 Target-ID */
112 /* [0x0] TX queue 0/1 Target-Address */
114 /* [0x4] TX queue 2/3 Target-Address */
116 /* [0x8] RX queue 0/1 Target-Address */
118 /* [0xc] RX queue 2/3 Target-Address */
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | renesas,rzv2h-gbeth.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/renesas,rzv2h-gbeth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
17 - renesas,r9a09g047-gbeth
18 - renesas,r9a09g056-gbeth
19 - renesas,r9a09g057-gbeth
20 - renesas,rzv2h-gbeth
22 - compatible
[all …]
|
| H A D | renesas,r9a09g057-gbeth.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/renesas,r9a09g057-gbeth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
17 - renesas,r9a09g056-gbeth
18 - renesas,r9a09g057-gbeth
19 - renesas,rzv2h-gbeth
21 - compatible
26 - enum:
[all …]
|
| H A D | keystone-netcp.txt | 6 switch sub-module to send and receive packets. NetCP also includes a packet
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
28 |-> NetCP Devices -> |
[all …]
|
| H A D | snps,dwmac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
26 - snps,dwmac-3.610
[all …]
|
| /freebsd/sys/dev/vge/ |
| H A D | if_vgereg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
15 * 3. All advertising materials mentioning features or use of this software
18 * 4. Neither the name of the author nor the names of any co-contributors
37 * Definitions for the built-in copper PHY can be found in vgphy.h.
41 * using 32-bit I/O cycles, but some of them are less than 32 bits
55 #define VGE_TXCTL 0x07 /* TX control register */
59 #define VGE_CRS3 0x0B /* Global cmd register 3 (w to set) */
63 #define VGE_CRC3 0x0F /* Global cmd register 3 (w to clr) */
81 #define VGE_TXHOSTERR 0x22 /* TX host error status */
[all …]
|
| /freebsd/sys/contrib/dev/iwlwifi/fw/api/ |
| H A D | tx.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2025 Intel Corporation
4 * Copyright (C) 2016-2017 Intel Deutschland GmbH
11 * enum iwl_tx_flags - bitmasks for tx_flags in TX command
12 * @TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame
13 * @TX_CMD_FLG_WRITE_TX_POWER: update current tx power value in the mgmt frame
15 * @TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command.
16 * Otherwise, use rate_n_flags from the TX command
28 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command
29 * @TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU
[all …]
|
| /freebsd/share/man/man4/ |
| H A D | gve.4 | 1 .\" SPDX-License-Identifier: BSD-3-Clause
3 .\" Copyright (c) 2023-2024 Google LLC
15 .\" 3. Neither the name of the copyright holder nor the names of its contributors
39 .Bd -ragged -offset indent
46 .Bd -literal -offset indent
51 It is required to support per-VM Tier-1 networking performance, and for using certain VM shapes on …
57 .Bl -bullet -compact
78 .Bl -bullet -compact
84 Change the TX queue count to 4 for the gve0 interface:
87 Change the RX queue count to 4 for the gve0 interface:
[all …]
|
| H A D | ena.4 | 1 .\" SPDX-License-Identifier: BSD-2-Clause
3 .\" Copyright (c) 2015-2024 Amazon.com, Inc. or its affiliates.
40 .Bd -ragged -offset indent
47 .Bd -literal -offset indent
56 through an Admin Queue.
58 The driver supports a range of ENA devices, is link-speed independent
62 Some ENA devices support SR-IOV.
63 This driver is used for both the SR-IOV Physical Function (PF) and Virtual
67 processing by providing multiple Tx/Rx queue pairs (the maximum number
68 is advertised by the device via the Admin Queue), a dedicated MSI-X
[all …]
|
| /freebsd/sys/dev/cxgbe/firmware/ |
| H A D | t4fw_cfg_uwire.txt | 3 # Copyright (C) 2010-2017 Chelsio Communications. All rights reserved.
6 # THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT
9 # This file provides the default, power-on configuration for 4-port T4-based
22 # 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions
24 # 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a
26 # 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV
28 # same umber of MSI-X Vectors as the base Physical Function.
30 # not, their MSI-X "needs" are counted by the PCI-E implementation.
32 # Functions (PF0-3) must have the same number of configured TotalVFs in
33 # their SR-IOV Capabilities.
[all …]
|
| H A D | t5fw_cfg_uwire.txt | 3 # Copyright (C) 2010-2017 Chelsio Communications. All rights reserved.
6 # WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
10 # This file provides the default, power-on configuration for 4-port T5-based
24 # 3. Egress Queues: 128K.
25 # 4. MSI-X Vectors: 1088.
26 # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
34 # functions for ports 0-3 on PF0-3, FCoE on PF4, iSCSI on PF5, etc.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
46 # 3 application functions (NIC, FCoE, iSCSI) per port *
47 # 8 Ingress Queue/MSI-X Vectors per application function
[all …]
|
| H A D | t6fw_cfg_uwire.txt | 3 # Copyright (C) 2014-2015 Chelsio Communications. All rights reserved.
6 # WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
10 # This file provides the default, power-on configuration for 2-port T6-based
24 # 3. Egress Queues: 128K.
25 # 4. MSI-X Vectors: 1088.
26 # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
34 # functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
46 # 3 application functions (NIC, FCoE, iSCSI) per port *
47 # 16 Ingress Queue/MSI-X Vectors per application function
[all …]
|
| H A D | t5fw_cfg_fpga.txt | 3 # Copyright (C) 2010-2013 Chelsio Communications. All rights reserved.
6 # THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT
9 # This file provides the default, power-on configuration for 4-port T4-based
22 # 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions
24 # 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a
26 # 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV
28 # same umber of MSI-X Vectors as the base Physical Function.
30 # not, their MSI-X "needs" are counted by the PCI-E implementation.
32 # Functions (PF0-3) must have the same number of configured TotalVFs in
33 # their SR-IOV Capabilities.
[all …]
|
| H A D | t6fw_cfg_fpga.txt | 3 # Copyright (C) 2014-2015 Chelsio Communications. All rights reserved.
6 # WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
10 # This file provides the default, power-on configuration for 2-port T6-based
24 # 3. Egress Queues: 128K.
25 # 4. MSI-X Vectors: 1088.
26 # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
34 # functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
46 # 3 application functions (NIC, FCoE, iSCSI) per port *
47 # 16 Ingress Queue/MSI-X Vectors per application function
[all …]
|
| /freebsd/sys/dev/bxe/ |
| H A D | ecore_mfw_req.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
75 uint32_t unused[3];
115 uint32_t promiscuous_mode; /* Promiscuous Mode. non-zero true */
116 uint32_t txq_size; /* TX Descriptors Queue Size */
117 uint32_t rxq_size; /* RX Descriptors Queue Size */
118 /* TX Descriptor Queue Avg Depth. % Avg Queue Depth since last poll */
120 /* RX Descriptors Queue Avg Depth. % Avg Queue Depth since last poll */
122 /* IOV_Offload. 0=none; 1=MultiQueue, 2=VEB 3= VEPA*/
[all …]
|
| /freebsd/sys/contrib/alpine-hal/eth/ |
| H A D | al_hal_eth.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
61 /* *INDENT-OFF* */
65 /* *INDENT-ON* */
84 #define AL_ETH_REV_ID_3 3 /* Alpine V2 advanced */
97 #define AL_ETH_TSO_MSS_MAX_VAL (AL_ETH_MAX_FRAME_LEN - 200)
115 AL_ETH_TUNNEL_WITH_UDP = 3, /* VXLAN */
124 #define AL_ETH_FWD_PBITS_TABLE_NUM (1 << 3)
125 #define AL_ETH_FWD_PRIO_TABLE_NUM (1 << 3)
174 /** Tx to Rx switching decision type */
[all …]
|
| /freebsd/sys/dev/cxgb/ |
| H A D | cxgb_sge.c | 2 SPDX-License-Identifier: BSD-2-Clause
4 Copyright (c) 2007-2009, Chelsio Inc.
44 #include <sys/queue.h>
88 "size of per-queue mbuf ring");
96 #define COALESCE_START_MAX (TX_ETH_Q_SIZE-(TX_ETH_Q_SIZE>>3))
115 "tx cleaning minimum threshold");
118 * XXX don't re-enable this until TOE stops assuming
135 * Period of the Tx buffer reclaim timer. This timer does not need to run
136 * frequently as Tx buffers are usually reclaimed by new Tx packets.
159 struct rsp_desc { /* response queue descriptor */
[all …]
|
| /freebsd/sys/dev/qcom_ess_edma/ |
| H A D | qcom_ess_edma_reg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
5 * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
32 * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
96 #define EDMA_REG_RX_SW_CONS_IDX_Q(x) (0x220 + ((x) << 2)) /* x is the queue id */
98 #define EDMA_REG_TX_SW_CONS_IDX_Q(x) (0x240 + ((x) << 2)) /* x is the queue id */
114 #define EDMA_REG_RX_INT_MASK_Q(x) (0x300 + ((x) << 2)) /* x = queue id */
116 /* TX Interrupt mask register */
117 #define EDMA_REG_TX_INT_MASK_Q(x) (0x340 + ((x) << 2)) /* x = queue id */
138 #define EDMA_REG_TXF_WATER_MARK 0x408 /* In 8-bytes */
[all …]
|
| /freebsd/sys/arm/ti/cpsw/ |
| H A D | if_cpsw.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
36 * and in the TMS320C6452 3 Port Switch Ethernet Subsystem TRM.
39 * a 3-port store-and-forward switch connected to two independent
251 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_SHAREABLE },
252 { -1, 0 }
331 if ((_sc)->debug) { \
341 mtx_assert(&(sc)->rx.lock, MA_NOTOWNED); \
342 mtx_lock(&(sc)->tx.lock); \
345 #define CPSW_TX_UNLOCK(sc) mtx_unlock(&(sc)->tx.lock)
[all …]
|
| /freebsd/sys/dev/neta/ |
| H A D | if_mvnetareg.h | 46 /* XXX: Currently multi-queue can be used on the Tx side only */
53 #if MVNETA_TX_QNUM_MAX & (MVNETA_TX_QNUM_MAX - 1) != 0
56 #if MVNETA_RX_QNUM_MAX & (MVNETA_RX_QNUM_MAX - 1) != 0
62 #define MVNETA_TX_QUEUE_ALL ((1<<MVNETA_TX_QNUM_MAX)-1)
63 #define MVNETA_RX_QUEUE_ALL ((1<<MVNETA_RX_QNUM_MAX)-1)
73 #define MVNETA_BASEADDR(n) (0x2200 + ((n) << 3)) /* Base Address */
74 #define MVNETA_S(n) (0x2204 + ((n) << 3)) /* Size */
121 #define MVNETA_RQC 0x2680 /* Receive Queue Command */
134 /* Rx DMA Wake on LAN Registers 0x3690 - 0x36b8 */
136 /* Tx DMA Miscellaneous Registers */
[all …]
|
| /freebsd/sys/dev/ice/ |
| H A D | ice_iflib.h | 1 /* SPDX-License-Identifier: BSD-3-Clause */
15 * 3. Neither the name of the Intel Corporation nor the names of its
37 * implementation, including the Tx and Rx queue structures and the ice_softc
65 * ASSERT_CTX_LOCKED - Assert that the iflib context lock is held
71 #define ASSERT_CTX_LOCKED(sc) sx_assert((sc)->iflib_ctx_lock, SA_XLOCKED)
74 * IFLIB_CTX_LOCK - lock the iflib context lock
79 #define IFLIB_CTX_LOCK(sc) sx_xlock((sc)->iflib_ctx_lock)
82 * IFLIB_CTX_UNLOCK - unlock the iflib context lock
87 #define IFLIB_CTX_UNLOCK(sc) sx_xunlock((sc)->iflib_ctx_lock)
90 * ASSERT_CFG_LOCKED - Assert that a configuration lock is held
[all …]
|
| /freebsd/sys/dev/msk/ |
| H A D | if_mskreg.h | 17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
62 * 3. All advertising materials mentioning features or use of this software
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
[all …]
|
| /freebsd/sys/contrib/device-tree/src/arm/ti/keystone/ |
| H A D | keystone-k2hk-netcp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 queue-range = <0 0x4000>;
20 #address-cells = <1>;
21 #size-cells = <1>;
24 managed-queues = <0 0x2000>;
[all …]
|
| H A D | keystone-k2e-netcp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 queue-range = <0 0x2000>;
20 #address-cells = <1>;
21 #size-cells = <1>;
24 managed-queues = <0 0x2000>;
[all …]
|
| H A D | keystone-k2l-netcp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 queue-range = <0 0x2000>;
20 #address-cells = <1>;
21 #size-cells = <1>;
24 managed-queues = <0 0x2000>;
[all …]
|