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/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_udma_regs_gen.h9 found at http://www.gnu.org/licenses/gpl-2.0.html
100 /* [0x0] Target-ID control */
102 /* [0x4] TX queue 0/1 Target-ID */
104 /* [0x8] TX queue 2/3 Target-ID */
106 /* [0xc] RX queue 0/1 Target-ID */
108 /* [0x10] RX queue 2/3 Target-ID */
112 /* [0x0] TX queue 0/1 Target-Address */
114 /* [0x4] TX queue 2/3 Target-Address */
116 /* [0x8] RX queue 0/1 Target-Address */
118 /* [0xc] RX queue 2/3 Target-Address */
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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Drenesas,rzv2h-gbeth.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/renesas,rzv2h-gbeth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
17 - renesas,r9a09g047-gbeth
18 - renesas,r9a09g056-gbeth
19 - renesas,r9a09g057-gbeth
20 - renesas,rzv2h-gbeth
22 - compatible
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H A Drenesas,r9a09g057-gbeth.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/renesas,r9a09g057-gbeth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
17 - renesas,r9a09g056-gbeth
18 - renesas,r9a09g057-gbeth
19 - renesas,rzv2h-gbeth
21 - compatible
26 - enum:
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H A Dkeystone-netcp.txt6 switch sub-module to send and receive packets. NetCP also includes a packet
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
28 |-> NetCP Devices -> |
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H A Dsnps,dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
26 - snps,dwmac-3.610
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H A Dintel,ixp4xx-hss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/intel,ixp4xx-hss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Linus Walleij <linus.walleij@linaro.org>
15 Processing Engine) and the IXP4xx Queue Manager to process
20 const: intel,ixp4xx-hss
26 intel,npe-handle:
27 $ref: /schemas/types.yaml#/definitions/phandle-array
30 - description: phandle to the NPE this HSS instance is using
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/freebsd/share/man/man4/
H A Dena.41 .\" SPDX-License-Identifier: BSD-2-Clause
3 .\" Copyright (c) 2015-2024 Amazon.com, Inc. or its affiliates.
13 .\" 2. Redistributions in binary form must reproduce the above copyright
40 .Bd -ragged -offset indent
47 .Bd -literal -offset indent
56 through an Admin Queue.
58 The driver supports a range of ENA devices, is link-speed independent
62 Some ENA devices support SR-IOV.
63 This driver is used for both the SR-IOV Physical Function (PF) and Virtual
67 processing by providing multiple Tx/Rx queue pairs (the maximum number
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H A Dgve.41 .\" SPDX-License-Identifier: BSD-3-Clause
3 .\" Copyright (c) 2023-2024 Google LLC
11 .\" 2. Redistributions in binary form must reproduce the above copyright notice,
39 .Bd -ragged -offset indent
46 .Bd -literal -offset indent
51 It is required to support per-VM Tier-1 networking performance, and for using certain VM shapes on …
57 .Bl -bullet -compact
78 .Bl -bullet -compact
84 Change the TX queue count to 4 for the gve0 interface:
87 Change the RX queue count to 4 for the gve0 interface:
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/freebsd/sys/dev/vge/
H A Dif_vgereg.h1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
12 * 2. Redistributions in binary form must reproduce the above copyright
18 * 4. Neither the name of the author nor the names of any co-contributors
37 * Definitions for the built-in copper PHY can be found in vgphy.h.
41 * using 32-bit I/O cycles, but some of them are less than 32 bits
55 #define VGE_TXCTL 0x07 /* TX control register */
58 #define VGE_CRS2 0x0A /* Global cmd register 2 (w to set) */
62 #define VGE_CRC2 0x0E /* Global cmd register 2 (w to clr) */
81 #define VGE_TXHOSTERR 0x22 /* TX host error status */
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/freebsd/sys/dev/bxe/
H A Decore_mfw_req.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
12 * 2. Redistributions in binary form must reproduce the above copyright
37 #define PORT_MAX 2
38 #define NVM_PATH_MAX 2
80 #define DRV_INFO_CUR_VER 2
97 uint8_t mac_add2[8]; /* Additional Programmed MAC Addr 2. */
103 #define FEATURE_ETH_BOOTMODE_SHIFT 2
104 #define FEATURE_ETH_BOOTMODE_NONE (0x0 << 2)
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/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Dtx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2025 Intel Corporation
4 * Copyright (C) 2016-2017 Intel Deutschland GmbH
11 * enum iwl_tx_flags - bitmasks for tx_flags in TX command
12 * @TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame
13 * @TX_CMD_FLG_WRITE_TX_POWER: update current tx power value in the mgmt frame
15 * @TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command.
16 * Otherwise, use rate_n_flags from the TX command
28 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command
29 * @TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU
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/freebsd/sys/dev/ice/
H A Dice_iflib.h1 /* SPDX-License-Identifier: BSD-3-Clause */
11 * 2. Redistributions in binary form must reproduce the above copyright
37 * implementation, including the Tx and Rx queue structures and the ice_softc
65 * ASSERT_CTX_LOCKED - Assert that the iflib context lock is held
71 #define ASSERT_CTX_LOCKED(sc) sx_assert((sc)->iflib_ctx_lock, SA_XLOCKED)
74 * IFLIB_CTX_LOCK - lock the iflib context lock
79 #define IFLIB_CTX_LOCK(sc) sx_xlock((sc)->iflib_ctx_lock)
82 * IFLIB_CTX_UNLOCK - unlock the iflib context lock
87 #define IFLIB_CTX_UNLOCK(sc) sx_xunlock((sc)->iflib_ctx_lock)
90 * ASSERT_CFG_LOCKED - Assert that a configuration lock is held
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/freebsd/sys/dev/cxgbe/firmware/
H A Dt6fw_cfg_uwire.txt3 # Copyright (C) 2014-2015 Chelsio Communications. All rights reserved.
6 # WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
10 # This file provides the default, power-on configuration for 2-port T6-based
23 # 2. Ingress Queues with Free Lists: 1024.
25 # 4. MSI-X Vectors: 1088.
26 # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
34 # functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
45 # 2 ports *
47 # 16 Ingress Queue/MSI-X Vectors per application function
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H A Dt5fw_cfg_uwire.txt3 # Copyright (C) 2010-2017 Chelsio Communications. All rights reserved.
6 # WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
10 # This file provides the default, power-on configuration for 4-port T5-based
23 # 2. Ingress Queues with Free Lists: 1024.
25 # 4. MSI-X Vectors: 1088.
26 # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
34 # functions for ports 0-3 on PF0-3, FCoE on PF4, iSCSI on PF5, etc.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 8 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
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H A Dt4fw_cfg_uwire.txt3 # Copyright (C) 2010-2017 Chelsio Communications. All rights reserved.
6 # THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT
9 # This file provides the default, power-on configuration for 4-port T4-based
22 # 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions
23 # must use a power of 2 Ingress Queues.
24 # 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a
25 # power of 2 Egress Queues.
26 # 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV
28 # same umber of MSI-X Vectors as the base Physical Function.
30 # not, their MSI-X "needs" are counted by the PCI-E implementation.
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H A Dt5fw_cfg_fpga.txt3 # Copyright (C) 2010-2013 Chelsio Communications. All rights reserved.
6 # THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT
9 # This file provides the default, power-on configuration for 4-port T4-based
22 # 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions
23 # must use a power of 2 Ingress Queues.
24 # 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a
25 # power of 2 Egress Queues.
26 # 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV
28 # same umber of MSI-X Vectors as the base Physical Function.
30 # not, their MSI-X "needs" are counted by the PCI-E implementation.
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/freebsd/sys/dev/dpaa2/
H A Ddpaa2_types.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright © 2021-2023 Dmitry Salychev
11 * 2. Redistributions in binary form must reproduce the above copyright
76 * @brief Tx ring.
78 * fq: Parent (TxConf) frame queue.
79 * fqid: ID of the logical Tx queue.
86 uint32_t txid; /* Tx ring index */
93 * @brief Frame Queue is the basic queuing structure used by the QMan.
96 * as a queue of frames.
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/freebsd/sys/dev/qcom_ess_edma/
H A Dqcom_ess_edma_reg.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
5 * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
12 * 2. Redistributions in binary form must reproduce the above copyright
32 * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
96 #define EDMA_REG_RX_SW_CONS_IDX_Q(x) (0x220 + ((x) << 2)) /* x is the queue id */
98 #define EDMA_REG_TX_SW_CONS_IDX_Q(x) (0x240 + ((x) << 2)) /* x is the queue id */
114 #define EDMA_REG_RX_INT_MASK_Q(x) (0x300 + ((x) << 2)) /* x = queue id */
116 /* TX Interrupt mask register */
117 #define EDMA_REG_TX_INT_MASK_Q(x) (0x340 + ((x) << 2)) /* x = queue id */
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/freebsd/sys/arm/ti/cpsw/
H A Dif_cpsw.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
13 * 2. Redistributions in binary form must reproduce the above copyright
39 * a 3-port store-and-forward switch connected to two independent
40 * "sliver" controllers (port 1 and port 2). You can operate the
250 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_SHAREABLE },
252 { -1, 0 }
331 if ((_sc)->debug) { \
341 mtx_assert(&(sc)->rx.lock, MA_NOTOWNED); \
342 mtx_lock(&(sc)->tx.lock); \
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/freebsd/sys/contrib/device-tree/src/arm/ti/keystone/
H A Dkeystone-k2hk-netcp.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for Keystone 2 Hawking Netcp driver
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
8 qmss: qmss@2a40000 {
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 queue-range = <0 0x4000>;
20 #address-cells = <1>;
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H A Dkeystone-k2e-netcp.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for Keystone 2 Edison Netcp driver
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
8 qmss: qmss@2a40000 {
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 queue-range = <0 0x2000>;
20 #address-cells = <1>;
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H A Dkeystone-k2l-netcp.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for Keystone 2 Lamarr Netcp driver
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
8 qmss: qmss@2a40000 {
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 queue-range = <0 0x2000>;
20 #address-cells = <1>;
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/freebsd/sys/dev/ath/
H A Dif_ath_tx_edma.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
44 * by the driver - eg, calls to ath_hal_gettsf32().
129 #define INCR(_l, _sz) (_l) ++; (_l) &= ((_sz) - 1)
130 #define DECR(_l, _sz) (_l) --; (_l) &= ((_sz) - 1)
153 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TX_FIFO_PUSH, in ath_tx_alq_edma_push()
161 * it may not meet the TXOP for say, DBA-gated traffic in TDMA mode.
163 * The TX completion code handles a TX FIFO slot having multiple frames,
184 txq->axq_qnum, in ath_tx_edma_push_staging_list()
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/freebsd/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
61 /* *INDENT-OFF* */
65 /* *INDENT-ON* */
83 #define AL_ETH_REV_ID_2 2 /* Alpine V2 basic */
89 #define AL_ETH_MAC_BAR 2
97 #define AL_ETH_TSO_MSS_MAX_VAL (AL_ETH_MAX_FRAME_LEN - 200)
174 /** Tx to Rx switching decision type */
178 AL_ETH_TX_SWITCH_TYPE_VLAN_TABLE_AND_MAC = 2,
182 /** Tx to Rx VLAN ID selection type */
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/freebsd/sys/dev/cxgb/
H A Dcxgb_sge.c2 SPDX-License-Identifier: BSD-2-Clause
4 Copyright (c) 2007-2009, Chelsio Inc.
13 2. Neither the name of the Chelsio Corporation nor the names of its
44 #include <sys/queue.h>
88 "size of per-queue mbuf ring");
96 #define COALESCE_START_MAX (TX_ETH_Q_SIZE-(TX_ETH_Q_SIZE>>3))
97 #define COALESCE_STOP_DEFAULT TX_ETH_Q_SIZE>>2
100 #define TX_RECLAIM_MAX TX_ETH_Q_SIZE>>2
115 "tx cleaning minimum threshold");
118 * XXX don't re-enable this until TOE stops assuming
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