| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_udma_regs_gen.h | 9 found at http://www.gnu.org/licenses/gpl-2.0.html
100 /* [0x0] Target-ID control */
102 /* [0x4] TX queue 0/1 Target-ID */
104 /* [0x8] TX queue 2/3 Target-ID */
106 /* [0xc] RX queue 0/1 Target-ID */
108 /* [0x10] RX queue 2/3 Target-ID */
112 /* [0x0] TX queue 0/1 Target-Address */
114 /* [0x4] TX queue 2/3 Target-Address */
116 /* [0x8] RX queue 0/1 Target-Address */
118 /* [0xc] RX queue 2/3 Target-Address */
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | renesas,rzv2h-gbeth.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/renesas,rzv2h-gbeth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
17 - renesas,r9a09g047-gbeth
18 - renesas,r9a09g056-gbeth
19 - renesas,r9a09g057-gbeth
20 - renesas,rzv2h-gbeth
22 - compatible
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| H A D | renesas,r9a09g057-gbeth.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/renesas,r9a09g057-gbeth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
17 - renesas,r9a09g056-gbeth
18 - renesas,r9a09g057-gbeth
19 - renesas,rzv2h-gbeth
21 - compatible
26 - enum:
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| H A D | intel,ixp4xx-hss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/intel,ixp4xx-hss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Linus Walleij <linus.walleij@linaro.org>
15 Processing Engine) and the IXP4xx Queue Manager to process
20 const: intel,ixp4xx-hss
23 maxItems: 1
26 intel,npe-handle:
27 $ref: /schemas/types.yaml#/definitions/phandle-array
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| H A D | keystone-netcp.txt | 6 switch sub-module to send and receive packets. NetCP also includes a packet
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
25 NetCP subsystem(10G or 1G)
26 -----------------------------
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| H A D | snps,dwmac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
26 - snps,dwmac-3.610
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| /freebsd/share/man/man4/ |
| H A D | gve.4 | 1 .\" SPDX-License-Identifier: BSD-3-Clause
3 .\" Copyright (c) 2023-2024 Google LLC
8 .\" 1. Redistributions of source code must retain the above copyright notice, this
39 .Bd -ragged -offset indent
46 .Bd -literal -offset indent
51 It is required to support per-VM Tier-1 networking performance, and for using certain VM shapes on …
57 .Bl -bullet -compact
78 .Bl -bullet -compact
80 0x1AE0:0x0042
84 Change the TX queue count to 4 for the gve0 interface:
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| H A D | ena.4 | 1 .\" SPDX-License-Identifier: BSD-2-Clause
3 .\" Copyright (c) 2015-2024 Amazon.com, Inc. or its affiliates.
10 .\" 1. Redistributions of source code must retain the above copyright
40 .Bd -ragged -offset indent
47 .Bd -literal -offset indent
56 through an Admin Queue.
58 The driver supports a range of ENA devices, is link-speed independent
62 Some ENA devices support SR-IOV.
63 This driver is used for both the SR-IOV Physical Function (PF) and Virtual
67 processing by providing multiple Tx/Rx queue pairs (the maximum number
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| H A D | iflib.4 | 24 .Xr kenv 1 .
28 .Bl -tag -width indent
30 Override the number of RX descriptors for each queue.
37 Override the number of TX descriptors for each queue.
45 If not set, the lower of the number of TX or RX queues will be used for both.
52 Set the number of TX queues.
53 If zero, the number of TX queues is derived from the number of cores on the
56 Disables MSI-X interrupts for the device.
62 Requests that RX and TX queues not be paired on the same core.
63 If this is zero or not set, an RX and TX queue pair will be assigned to each
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| /freebsd/sys/dev/vge/ |
| H A D | if_vgereg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
10 * 1. Redistributions of source code must retain the above copyright
18 * 4. Neither the name of the author nor the names of any co-contributors
37 * Definitions for the built-in copper PHY can be found in vgphy.h.
41 * using 32-bit I/O cycles, but some of them are less than 32 bits
55 #define VGE_TXCTL 0x07 /* TX control register */
57 #define VGE_CRS1 0x09 /* Global cmd register 1 (w to set) */
61 #define VGE_CRC1 0x0D /* Global cmd register 1 (w to clr) */
65 #define VGE_MAR1 0x14 /* Mcast hash/CAM register 1 */
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| /freebsd/sys/contrib/dev/iwlwifi/fw/api/ |
| H A D | tx.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2025 Intel Corporation
4 * Copyright (C) 2016-2017 Intel Deutschland GmbH
11 * enum iwl_tx_flags - bitmasks for tx_flags in TX command
12 * @TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame
13 * @TX_CMD_FLG_WRITE_TX_POWER: update current tx power value in the mgmt frame
15 * @TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command.
16 * Otherwise, use rate_n_flags from the TX command
28 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command
29 * @TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU
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| /freebsd/sys/dev/bxe/ |
| H A D | ecore_mfw_req.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
10 * 1. Redistributions of source code must retain the above copyright
36 #define PORT_1 1
96 uint8_t mac_add1[8]; /* Additional Programmed MAC Addr 1. */
115 uint32_t promiscuous_mode; /* Promiscuous Mode. non-zero true */
116 uint32_t txq_size; /* TX Descriptors Queue Size */
117 uint32_t rxq_size; /* RX Descriptors Queue Size */
118 /* TX Descriptor Queue Avg Depth. % Avg Queue Depth since last poll */
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| /freebsd/sys/contrib/dev/iwlwifi/mvm/ |
| H A D | sta.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2025 Intel Corporation
4 * Copyright (C) 2013-2014 Intel Mobile Communications GmbH
5 * Copyright (C) 2015-2016 Intel Deutschland GmbH
14 #include "iwl-trans.h" /* for IWL_MAX_TID_COUNT */
15 #include "fw-api.h" /* IWL_STATION_COUNT_MAX */
22 * DOC: DQA - Dynamic Queue Allocation -introduction
24 * Dynamic Queue Allocation (AKA "DQA") is a feature implemented in iwlwifi
25 * driver to allow dynamic allocation of queues on-demand, rather than allocate
26 * them statically ahead of time. Ideally, we would like to allocate one queue
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| /freebsd/sys/contrib/openzfs/module/zfs/ |
| H A D | dsl_scan.c | 1 // SPDX-License-Identifier: CDDL-1.0
10 * or https://opensource.org/licenses/CDDL-1.0.
64 * Grand theory statement on scan queue sorting
71 * case with pools given the allocation patterns of copy-on-write filesystems.
72 * So instead, we put the I/Os into a reordering queue and issue them in a
73 * way that will most benefit physical disks (LBA-order).
75 * Queue management:
77 * Ideally, we would want to scan all metadata and queue up all block I/O
101 * the scanning code to remove these I/Os from the issuing queue. Additionally,
102 * we do not attempt to queue gang blocks to be issued sequentially since this
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| /freebsd/sys/contrib/dev/ath/ath_hal/ar9300/ |
| H A D | ar9300_xmit.c | 32 * Update Tx FIFO trigger level.
46 if (AH9300(ah)->ah_tx_trig_level >= MAX_TX_FIFO_THRESHOLD && in ar9300_update_tx_trig_level()
55 omask = ar9300_set_interrupts(ah, ahp->ah_mask_reg &~ HAL_INT_GLOBAL, 0); in ar9300_update_tx_trig_level()
66 new_level--; in ar9300_update_tx_trig_level()
75 /* re-enable chip interrupts */ in ar9300_update_tx_trig_level()
78 AH9300(ah)->ah_tx_trig_level = new_level; in ar9300_update_tx_trig_level()
84 * Returns the value of Tx Trigger Level
89 return (AH9300(ah)->ah_tx_trig_level); in ar9300_get_tx_trig_level()
93 * Set the properties of the tx queue with the parameters
100 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; in ar9300_set_tx_queue_props()
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| /freebsd/sys/dev/ath/ath_hal/ar5211/ |
| H A D | ar5211_xmit.c | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2006 Atheros Communications, Inc.
30 * Update Tx FIFO trigger level.
45 * is called from both ISR and non-ISR contexts. in ar5211UpdateTxTrigLevel()
53 ((MAX_TX_FIFO_THRESHOLD - curTrigLevel) / 2); in ar5211UpdateTxTrigLevel()
58 curTrigLevel--; in ar5211UpdateTxTrigLevel()
61 /* re-enable chip interrupts */ in ar5211UpdateTxTrigLevel()
69 /* re-enable chip interrupts */ in ar5211UpdateTxTrigLevel()
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| /freebsd/sys/arm/ti/cpsw/ |
| H A D | if_cpsw.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
11 * 1. Redistributions of source code must retain the above copyright
39 * a 3-port store-and-forward switch connected to two independent
40 * "sliver" controllers (port 1 and port 2). You can operate the
233 MODULE_DEPEND(cpswss, etherswitch, 1, 1, 1);
238 MODULE_DEPEND(cpsw, ether, 1, 1, 1);
239 MODULE_DEPEND(cpsw, miibus, 1, 1, 1);
249 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_SHAREABLE },
252 { -1, 0 }
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| /freebsd/sys/dev/ath/ath_hal/ar5210/ |
| H A D | ar5210_xmit.c | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2004 Atheros Communications, Inc.
31 * Set the properties of the tx queue with the parameters
32 * from qInfo. The queue must previously have been setup
41 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n", in ar5210SetTxQueueProps()
45 return ath_hal_setTxQProps(ah, &ahp->ah_txq[q], qInfo); in ar5210SetTxQueueProps()
49 * Return the properties for the specified tx queue.
57 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n", in ar5210GetTxQueueProps()
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| /freebsd/sys/dev/ath/ |
| H A D | if_ath_tx_edma.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
10 * 1. Redistributions of source code must retain the above copyright
44 * by the driver - eg, calls to ath_hal_gettsf32().
129 #define INCR(_l, _sz) (_l) ++; (_l) &= ((_sz) - 1)
130 #define DECR(_l, _sz) (_l) --; (_l) &= ((_sz) - 1)
153 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TX_FIFO_PUSH, in ath_tx_alq_edma_push()
161 * it may not meet the TXOP for say, DBA-gated traffic in TDMA mode.
163 * The TX completion code handles a TX FIFO slot having multiple frames,
184 txq->axq_qnum, in ath_tx_edma_push_staging_list()
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| /freebsd/sys/dev/cxgbe/firmware/ |
| H A D | t5fw_cfg_uwire.txt | 3 # Copyright (C) 2010-2017 Chelsio Communications. All rights reserved.
6 # WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
10 # This file provides the default, power-on configuration for 4-port T5-based
22 # 1. Virtual Interfaces: 256.
25 # 4. MSI-X Vectors: 1088.
26 # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
34 # functions for ports 0-3 on PF0-3, FCoE on PF4, iSCSI on PF5, etc.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 8 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
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| H A D | t6fw_cfg_uwire.txt | 3 # Copyright (C) 2014-2015 Chelsio Communications. All rights reserved.
6 # WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
10 # This file provides the default, power-on configuration for 2-port T6-based
22 # 1. Virtual Interfaces: 256.
25 # 4. MSI-X Vectors: 1088.
26 # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
34 # functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 16 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
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| H A D | t4fw_cfg_uwire.txt | 3 # Copyright (C) 2010-2017 Chelsio Communications. All rights reserved.
6 # THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT
9 # This file provides the default, power-on configuration for 4-port T4-based
21 # 1. Virtual Interfaces: 128.
22 # 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions
24 # 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a
26 # 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV
28 # same umber of MSI-X Vectors as the base Physical Function.
30 # not, their MSI-X "needs" are counted by the PCI-E implementation.
32 # Functions (PF0-3) must have the same number of configured TotalVFs in
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| /freebsd/sys/dev/qcom_ess_edma/ |
| H A D | qcom_ess_edma_reg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
5 * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
10 * 1. Redistributions of source code must retain the above copyright
32 * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
59 #define ESS_EDMA_TX_BUFFER_ALIGN 1
60 #define ESS_EDMA_RX_BUFFER_ALIGN 1
76 #define EDMA_MISC_ISR_RX_URG_Q(x) (1U << (x)x)
96 #define EDMA_REG_RX_SW_CONS_IDX_Q(x) (0x220 + ((x) << 2)) /* x is the queue id */
98 #define EDMA_REG_TX_SW_CONS_IDX_Q(x) (0x240 + ((x) << 2)) /* x is the queue id */
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| /freebsd/sys/contrib/device-tree/src/arm/ti/keystone/ |
| H A D | keystone-k2hk-netcp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 queue-range = <0 0x4000>;
20 #address-cells = <1>;
21 #size-cells = <1>;
24 managed-queues = <0 0x2000>;
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| /freebsd/sys/dev/cxgb/ |
| H A D | cxgb_sge.c | 2 SPDX-License-Identifier: BSD-2-Clause
4 Copyright (c) 2007-2009, Chelsio Inc.
10 1. Redistributions of source code must retain the above copyright notice,
44 #include <sys/queue.h>
79 int multiq_tx_enable = 1;
88 "size of per-queue mbuf ring");
95 #define COALESCE_START_DEFAULT TX_ETH_Q_SIZE>>1
96 #define COALESCE_START_MAX (TX_ETH_Q_SIZE-(TX_ETH_Q_SIZE>>3))
115 "tx cleaning minimum threshold");
118 * XXX don't re-enable this until TOE stops assuming
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