| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_udma_regs_gen.h | 9 found at http://www.gnu.org/licenses/gpl-2.0.html
58 /* [0x0] Reserved register for the interrupt controller */
60 /* [0x4] Revision register */
62 /* [0x8] Reserved for future use */
64 /* [0xc] Reserved for future use */
66 /* [0x10] Reserved for future use */
68 /* [0x14] Reserved for future use */
70 /* [0x18] General timer configuration */
76 * [0x0] Mailbox interrupt generator.
80 /* [0x4] Mailbox message data out */
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | renesas,rzv2h-gbeth.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/renesas,rzv2h-gbeth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
17 - renesas,r9a09g047-gbeth
18 - renesas,r9a09g056-gbeth
19 - renesas,r9a09g057-gbeth
20 - renesas,rzv2h-gbeth
22 - compatible
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| H A D | renesas,r9a09g057-gbeth.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/renesas,r9a09g057-gbeth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
17 - renesas,r9a09g056-gbeth
18 - renesas,r9a09g057-gbeth
19 - renesas,rzv2h-gbeth
21 - compatible
26 - enum:
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| H A D | keystone-netcp.txt | 6 switch sub-module to send and receive packets. NetCP also includes a packet
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
28 |-> NetCP Devices -> |
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| H A D | snps,dwmac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
26 - snps,dwmac-3.610
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| /freebsd/share/man/man4/ |
| H A D | ena.4 | 1 .\" SPDX-License-Identifier: BSD-2-Clause
3 .\" Copyright (c) 2015-2024 Amazon.com, Inc. or its affiliates.
40 .Bd -ragged -offset indent
47 .Bd -literal -offset indent
56 through an Admin Queue.
58 The driver supports a range of ENA devices, is link-speed independent
62 Some ENA devices support SR-IOV.
63 This driver is used for both the SR-IOV Physical Function (PF) and Virtual
67 processing by providing multiple Tx/Rx queue pairs (the maximum number
68 is advertised by the device via the Admin Queue), a dedicated MSI-X
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| H A D | gve.4 | 1 .\" SPDX-License-Identifier: BSD-3-Clause
3 .\" Copyright (c) 2023-2024 Google LLC
39 .Bd -ragged -offset indent
46 .Bd -literal -offset indent
51 It is required to support per-VM Tier-1 networking performance, and for using certain VM shapes on …
57 .Bl -bullet -compact
78 .Bl -bullet -compact
80 0x1AE0:0x0042
84 Change the TX queue count to 4 for the gve0 interface:
85 .D1 sysctl dev.gve.0.num_tx_queues=4
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| H A D | iflib.4 | 28 .Bl -tag -width indent
30 Override the number of RX descriptors for each queue.
37 Override the number of TX descriptors for each queue.
45 If not set, the lower of the number of TX or RX queues will be used for both.
50 Defaults to 0.
52 Set the number of TX queues.
53 If zero, the number of TX queues is derived from the number of cores on the
56 Disables MSI-X interrupts for the device.
62 Requests that RX and TX queues not be paired on the same core.
63 If this is zero or not set, an RX and TX queue pair will be assigned to each
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| /freebsd/sys/dev/vge/ |
| H A D | if_vgereg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
37 * Definitions for the built-in copper PHY can be found in vgphy.h.
41 * using 32-bit I/O cycles, but some of them are less than 32 bits
48 #define VIA_VENDORID 0x1106
49 #define VIA_DEVICEID_61XX 0x3119
51 #define VGE_PAR0 0x00 /* physical address register */
52 #define VGE_PAR1 0x02
53 #define VGE_PAR2 0x04
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| /freebsd/sys/contrib/dev/iwlwifi/fw/api/ |
| H A D | tx.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2025 Intel Corporation
4 * Copyright (C) 2016-2017 Intel Deutschland GmbH
11 * enum iwl_tx_flags - bitmasks for tx_flags in TX command
12 * @TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame
13 * @TX_CMD_FLG_WRITE_TX_POWER: update current tx power value in the mgmt frame
15 * @TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command.
16 * Otherwise, use rate_n_flags from the TX command
28 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command
29 * @TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU
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| /freebsd/sys/dev/bxe/ |
| H A D | ecore_mfw_req.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
35 #define PORT_0 0
44 #define FCOE_IOS_PER_CONNECTION_MASK 0x0000ffff
45 #define FCOE_IOS_PER_CONNECTION_SHIFT 0
47 #define FCOE_LOGINS_PER_PORT_MASK 0xffff0000
52 #define FCOE_NUMBER_OF_EXCHANGES_MASK 0x0000ffff
53 #define FCOE_NUMBER_OF_EXCHANGES_SHIFT 0
55 #define FCOE_NPIV_WWN_PER_PORT_MASK 0xffff0000
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| /freebsd/sys/contrib/dev/iwlwifi/mvm/ |
| H A D | sta.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2025 Intel Corporation
4 * Copyright (C) 2013-2014 Intel Mobile Communications GmbH
5 * Copyright (C) 2015-2016 Intel Deutschland GmbH
14 #include "iwl-trans.h" /* for IWL_MAX_TID_COUNT */
15 #include "fw-api.h" /* IWL_STATION_COUNT_MAX */
22 * DOC: DQA - Dynamic Queue Allocation -introduction
24 * Dynamic Queue Allocation (AKA "DQA") is a feature implemented in iwlwifi
25 * driver to allow dynamic allocation of queues on-demand, rather than allocate
26 * them statically ahead of time. Ideally, we would like to allocate one queue
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| /freebsd/sys/contrib/openzfs/module/zfs/ |
| H A D | dsl_scan.c | 1 // SPDX-License-Identifier: CDDL-1.0
10 * or https://opensource.org/licenses/CDDL-1.0.
64 * Grand theory statement on scan queue sorting
71 * case with pools given the allocation patterns of copy-on-write filesystems.
72 * So instead, we put the I/Os into a reordering queue and issue them in a
73 * way that will most benefit physical disks (LBA-order).
75 * Queue management:
77 * Ideally, we would want to scan all metadata and queue up all block I/O
101 * the scanning code to remove these I/Os from the issuing queue. Additionally,
102 * we do not attempt to queue gang blocks to be issued sequentially since this
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| /freebsd/sys/dev/ath/ |
| H A D | if_ath_tx_edma.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
44 * by the driver - eg, calls to ath_hal_gettsf32().
129 #define INCR(_l, _sz) (_l) ++; (_l) &= ((_sz) - 1)
130 #define DECR(_l, _sz) (_l) --; (_l) &= ((_sz) - 1)
153 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TX_FIFO_PUSH, in ath_tx_alq_edma_push()
161 * it may not meet the TXOP for say, DBA-gated traffic in TDMA mode.
163 * The TX completion code handles a TX FIFO slot having multiple frames,
184 txq->axq_qnum, in ath_tx_edma_push_staging_list()
185 txq->axq_fifo_depth, in ath_tx_edma_push_staging_list()
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| /freebsd/sys/contrib/dev/ath/ath_hal/ar9300/ |
| H A D | ar9300_xmit.c | 32 * Update Tx FIFO trigger level.
46 if (AH9300(ah)->ah_tx_trig_level >= MAX_TX_FIFO_THRESHOLD && in ar9300_update_tx_trig_level()
55 omask = ar9300_set_interrupts(ah, ahp->ah_mask_reg &~ HAL_INT_GLOBAL, 0); in ar9300_update_tx_trig_level()
66 new_level--; in ar9300_update_tx_trig_level()
75 /* re-enable chip interrupts */ in ar9300_update_tx_trig_level()
76 ar9300_set_interrupts(ah, omask, 0); in ar9300_update_tx_trig_level()
78 AH9300(ah)->ah_tx_trig_level = new_level; in ar9300_update_tx_trig_level()
84 * Returns the value of Tx Trigger Level
89 return (AH9300(ah)->ah_tx_trig_level); in ar9300_get_tx_trig_level()
93 * Set the properties of the tx queue with the parameters
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| /freebsd/sys/arm/ti/cpsw/ |
| H A D | if_cpsw.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
38 * It is basically a single Ethernet port (port 0) wired internally to
39 * a 3-port store-and-forward switch connected to two independent
210 DRIVER_MODULE(cpswss, simplebus, cpsw_driver, 0, 0);
232 DRIVER_MODULE(etherswitch, cpswss, etherswitch_driver, 0, 0);
236 DRIVER_MODULE(cpsw, cpswss, cpswp_driver, 0, 0);
237 DRIVER_MODULE(miibus, cpsw, miibus_driver, 0, 0);
245 static uint32_t slave_mdio_addr[] = { 0x4a100200, 0x4a100300 };
248 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
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| /freebsd/sys/dev/ath/ath_hal/ar5211/ |
| H A D | ar5211_xmit.c | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2006 Atheros Communications, Inc.
30 * Update Tx FIFO trigger level.
45 * is called from both ISR and non-ISR contexts. in ar5211UpdateTxTrigLevel()
53 ((MAX_TX_FIFO_THRESHOLD - curTrigLevel) / 2); in ar5211UpdateTxTrigLevel()
58 curTrigLevel--; in ar5211UpdateTxTrigLevel()
61 /* re-enable chip interrupts */ in ar5211UpdateTxTrigLevel()
69 /* re-enable chip interrupts */ in ar5211UpdateTxTrigLevel()
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| /freebsd/sys/dev/dpaa2/ |
| H A D | dpaa2_types.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright © 2021-2023 Dmitry Salychev
38 #define DPAA2_MAGIC ((uint32_t) 0xD4AA2C0Du)
65 DPAA2_NI_QUEUE_RX = 0,
76 * @brief Tx ring.
78 * fq: Parent (TxConf) frame queue.
79 * fqid: ID of the logical Tx queue.
86 uint32_t txid; /* Tx ring index */
93 * @brief Frame Queue is the basic queuing structure used by the QMan.
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| /freebsd/sys/dev/ath/ath_hal/ar5210/ |
| H A D | ar5210_xmit.c | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2004 Atheros Communications, Inc.
31 * Set the properties of the tx queue with the parameters
32 * from qInfo. The queue must previously have been setup
41 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n", in ar5210SetTxQueueProps()
45 return ath_hal_setTxQProps(ah, &ahp->ah_txq[q], qInfo); in ar5210SetTxQueueProps()
49 * Return the properties for the specified tx queue.
57 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n", in ar5210GetTxQueueProps()
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| /freebsd/sys/dev/qcom_ess_edma/ |
| H A D | qcom_ess_edma_reg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
5 * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
32 * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
63 #define EDMA_REG_MAS_CTRL 0x0
64 #define EDMA_REG_TIMEOUT_CTRL 0x004
65 #define EDMA_REG_DBG0 0x008
66 #define EDMA_REG_DBG1 0x00C
67 #define EDMA_REG_SW_CTRL0 0x100
68 #define EDMA_REG_SW_CTRL1 0x104
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| /freebsd/sys/dev/cxgbe/firmware/ |
| H A D | t5fw_cfg_uwire.txt | 3 # Copyright (C) 2010-2017 Chelsio Communications. All rights reserved.
6 # WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
10 # This file provides the default, power-on configuration for 4-port T5-based
25 # 4. MSI-X Vectors: 1088.
26 # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
34 # functions for ports 0-3 on PF0-3, FCoE on PF4, iSCSI on PF5, etc.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 8 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
52 # 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual
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| H A D | t6fw_cfg_uwire.txt | 3 # Copyright (C) 2014-2015 Chelsio Communications. All rights reserved.
6 # WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
10 # This file provides the default, power-on configuration for 2-port T6-based
25 # 4. MSI-X Vectors: 1088.
26 # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
34 # functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 16 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
52 # 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual
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| H A D | t4fw_cfg_uwire.txt | 3 # Copyright (C) 2010-2017 Chelsio Communications. All rights reserved.
6 # THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT
9 # This file provides the default, power-on configuration for 4-port T4-based
22 # 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions
24 # 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a
26 # 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV
28 # same umber of MSI-X Vectors as the base Physical Function.
30 # not, their MSI-X "needs" are counted by the PCI-E implementation.
32 # Functions (PF0-3) must have the same number of configured TotalVFs in
33 # their SR-IOV Capabilities.
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| /freebsd/sys/contrib/dev/iwlwifi/pcie/gen1_2/ |
| H A D | tx.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2003-2014, 2018-2021, 2023-2025 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
24 #include "iwl-fh.h"
25 #include "iwl-debug.h"
26 #include "iwl-csr.h"
27 #include "iwl-prph.h"
28 #include "iwl-io.h"
29 #include "iwl-scd.h"
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| /freebsd/sys/contrib/device-tree/src/arm/ti/keystone/ |
| H A D | keystone-k2hk-netcp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 queue-range = <0 0x4000>;
16 linkram0 = <0x100000 0x8000>;
17 linkram1 = <0x0 0x10000>;
20 #address-cells = <1>;
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