tx\-fifo\-max\-num (full) in projects: linux

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×illumos-gate

Searched +full:tx +full:- +full:fifo +full:- +full:max +full:- +full:num (Results 1 – 25 of 28) sorted by relevance

/illumos-gate/usr/src/uts/common/io/xge/hal/include/
H A D	xgehal-config.h	21 * Copyright (c) 2002-2006 Neterion, Inc. 27 #include "xge-os-pal.h" 28 #include "xgehal-types.h" 29 #include "xge-queue.h" 33 #define XGE_HAL_DEFAULT_USE_HARDCODE -1 40 * struct xge_hal_tti_config_t - Xframe Tx interrupt configuration. 59 * @timer_ac_en: Enable auto-cancel. That is, reset the timer if utilization 69 * for more details. Note also (min, max) 71 * Note: Valid (min, max) range for each attribute is specified in the body of 127 * struct xge_hal_rti_config_t - Xframe Rx interrupt configuration. [all …]
H A D	xgehal-fifo.h	`21 * Copyright (c) 2002-2006 Neterion, Inc. 27 #include "xgehal-channel.h" 28 #include "xgehal-config.h" 29 #include "xgehal-mm.h" 33 /* HW fifo configuration / 40 / HW FIFO Weight Calender / 49 Represent a single fifo in the BAR1 memory space. 78 * struct xge_hal_fifo_txd_t - TxD. 88 * Transmit descriptor (TxD).Fifo descriptor contains configured number 130 * struct xge_hal_fifo_t - Fifo channel. [all …]`
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/mcp/
H A D	ncsi_basic_types.h	46 * ------------------------------------------------------------------------- 58 /---------------------------------------------------------------------------- 59 ------------------------------ include files --------------------------------- 60 ----------------------------------------------------------------------------/ 71 /---------------------------------------------------------------------------- 72 ------------------------------ local definitions ----------------------------- 76 ----------------------------------------------------------------------------/ 95 #define NCSI_TYPES_MAX_L2_PKT_SIZE 1514 /* max Ethernet frame s… 96 #define NCSI_TYPES_MAX_L2_PKT_SIZE_PLUS_VLAN 1518 /* max Ethernet frame s… 278 u32_t Rx; // Num of valid cmds rx by cmd proc [all …]
/illumos-gate/usr/src/uts/common/io/bfe/
H A D	bfe_hw.h	48 #define BFE_BIST_STAT 0x0000000C /* Built-In Self-Test Status / 58 #define BFE_ISTAT_RFO 0x00004000 / Receive FIFO Overflow / 59 #define BFE_ISTAT_TFU 0x00008000 / Transmit FIFO Underflow / 61 #define BFE_ISTAT_TX 0x01000000 / TX Interrupt / 80 #define BFE_FLOW_RX_HIWAT 0x000000ff / Onchip FIFO HI Water Mark / 88 #define BFE_DMATX_CTRL 0x00000200 / DMA TX Control / 95 #define BFE_DMATX_ADDR 0x00000204 / TX Descriptor Ring Address / 96 #define BFE_DMATX_PTR 0x00000208 / TX Last Posted Descriptor / 97 #define BFE_DMATX_STAT 0x0000020C / TX Curr Active Desc + Status / 108 #define BFE_STAT_EDFU 0x00020000 / Error Data FIFO Underrun */ [all …]
/illumos-gate/usr/src/uts/sun/io/eri/
H A D	eri_mac.h	40 /* The Descriptor Ring base Addresses must be 2K-byte aligned / 45 The transmit and receiver Descriptor Rings are organized as "wrap-around 47 * Each descriptor consists of two double-word entries: a control/status entry 51 * configurable variable to specify the max.no. of Rx buffers posted. 58 * ----------------------------- 60 * ----------------------------- 70 #define ERI_TMD_BUFSIZE (0x7fff << 0) /* 0-14 : Tx Data buffer size / 71 / valid values in range 0 - 17k / 72 #define ERI_TMD_CSSTART (0x3f << 15) / 15-20 : Checksum start offset / 74 #define ERI_TMD_CSSTUFF (0xff << 21) / 21-28 : Checksum stuff offset */ [all …]
/illumos-gate/usr/src/uts/common/io/yge/
H A D	yge.c	16 * are provided to you under the BSD-type license terms provided 21 * - Redistributions of source code must retain the above copyright 23 * - Redistributions in binary form must reproduce the above 27 * - Neither the name of Marvell nor the names of its contributors 61 * 4. Neither the name of the author nor the names of any co-contributors 277 yge_dev_t dev = port->p_dev; in yge_mii_readreg() 278 int pnum = port->p_port; in yge_mii_readreg() 306 yge_dev_t dev = port->p_dev; in yge_mii_writereg() 307 int pnum = port->p_port; in yge_mii_writereg() 328 PHY_LOCK(port->p_dev); in yge_mii_read() [all …]
/illumos-gate/usr/src/uts/common/io/qede/579xx/hsi/hw/
H A D	reg_addr_bb.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 79 … Mask memory read Bit3 : Mask memory write Bit2 : Mask Completion Bit1 : Mask TX Bit0 : Mask RX 82 … 0x003824UL //Access:R DataWidth:0x20 // tx number of tlp sent 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 …h:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW header sync … 86 …taWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header sync fifo pu… 87 …x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW header sync f… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … [all …]
H A D	reg_addr_k2.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 79 … Mask memory read Bit3 : Mask memory write Bit2 : Mask Completion Bit1 : Mask TX Bit0 : Mask RX 82 … 0x003824UL //Access:R DataWidth:0x20 // tx number of tlp sent 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 …h:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW header sync … 86 …taWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header sync fifo pu… 87 …x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW header sync f… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … [all …]
H A D	reg_addr_e5.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 79 … Mask memory read Bit3 : Mask memory write Bit2 : Mask Completion Bit1 : Mask TX Bit0 : Mask RX 82 … 0x003824UL //Access:R DataWidth:0x20 // tx number of tlp sent 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 …h:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW header sync … 86 …taWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header sync fifo pu… 87 …x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW header sync f… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … [all …]
H A D	reg_addr_ah_compile15.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 79 …memory read Bit3 : Mask memory write Bit2 : Mask Completion Bit1 : Mask TX Bit0 : Mask RX Chi… 82 … 0x003824UL //Access:R DataWidth:0x20 tx number of tlp sent … 85 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 87 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 96 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 98 … has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 144 …_SYS_ERR (0x1<<30) // Fatal or Non-Fatal Error Message s… [all …]
H A D	reg_addr.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 80 … Mask memory read Bit3 : Mask memory write Bit2 : Mask Completion Bit1 : Mask TX Bit0 : Mask RX 83 … 0x003824UL //Access:R DataWidth:0x20 // tx number of tlp sent 85 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 86 …h:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW header sync … 87 …taWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header sync fifo pu… 88 …x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW header sync f… 90 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … [all …]
/illumos-gate/usr/src/uts/common/sys/nxge/
H A D	nxge_mac_hw.h	35 /* -------------------------- From May's template --------------------------- / 43 NXGE_TX_DISABLE, / Disable Tx side / 48 #define NXGE_DELAY_AFTER_TXRX 10000 / 10ms after idling rx/tx / 52 #define NXGE_LINK_RESETS 8 / Max PHY resets to wait for / 64 / -------------------------------------------------------------------------- / 87 --- --- --- --- --- --- --- --- 112 * "xgc" as a possible value for the device property "phy-type" 236 (BMAC_ADDR_OFFSET_2 + (((port_num) - 2) * PORT_GT_1_OFFSET)) 254 (PCS_ADDR_OFFSET_2 + (((port_num) - 2) * PORT_GT_1_OFFSET))) 286 #define BTXMAC_SW_RST_REG 0x000 /* TX MAC software reset */ [all …]
/illumos-gate/usr/src/grub/grub-0.97/netboot/
H A D	e1000_hw.h	4 Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved. 18 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 291 /* MAC decode size is 128K - This is the size of BAR0 / 309 (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) 311 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) 355 E1000_RAR_ENTRIES - 1 multicast addresses. 379 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter / 442 #define E1000_TXD_STAT_TC 0x00000004 / Tx Underrun / 559 RW - register is both readable and writable [all …]
/illumos-gate/usr/src/uts/common/io/atge/
H A D	atge_main.c	92 * Atheros/Attansic Ethernet chips are of four types - L1, L2, L1E and L1C. 97 * Atheros/Attansic Ethernet controllers have descriptor based TX and RX 109 * use zero-copy RX because we are limited to two pages and each page 112 * The TX side on all three chips is descriptor based ring; and all the 115 * We use two locks - atge_intr_lock and atge_tx_lock. Both the locks 118 * All the three chips have hash-based multicast filter. 120 * We use CMB (Coalescing Message Block) for RX but not for TX as there 121 * are some issues with TX. RX CMB is used to get the last descriptor 125 * The descriptor table should have 32-bit physical address limit due to 126 * the limitation of having same high address for TX/RX/SMB/CMB. The [all …]
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A D	57712_reg.h	3 …//ACCESS:RW DataWidth:0x2 Description: Defines the number of sets - 3 - 256 ;2- 128; 1- 64; 0- 32 5 …0x8 Description: SPA Done FIFO full bit; RCPL FIFO full bit; TCPL FIFO full bit; IREQ full bit; P… 6 … Description: SPA Done FIFO empty bit; RCPL FIFO empty bit; TCPL FIFO empty bit; IREQ empty bit; … 9 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 10 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 11 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 12 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 13 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 14 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 15 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… [all …]
/illumos-gate/usr/src/uts/common/io/sfxge/common/
H A D	efx_regs_mcdi.h	2 * Copyright 2008-2013 Solarflare Communications Inc. All rights reserved. 33 /* Power-on reset state / 55 / The 'doorbell' addresses are hard-wired to alert the MC when written / 58 / The rest of these are firmware-defined / 66 / Values to be written to the per-port status dword in shared 95 * \| \| \--- Response 96 * \| \------- Error 97 * \------------------------------ Resync (always set) 152 * - To complete a shared memory request if XFLAGS_EVREQ was set 153 * - As a notification (link state, i2c event), controlled [all …]
/illumos-gate/usr/src/uts/common/io/iwn/
H A D	if_iwn.c	1 /* $NetBSD: if_iwn.c,v 1.78 2016/06/10 13:27:14 ozaki-r Exp $ / 4 /- 5 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 21 * Copyright 2016 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> 31 * - turn tunables into driver properties 419 return (ddi_get32(sc->sc_regh, (uint32_t )(sc->sc_base + reg))); in iwn_read() 426 ddi_put32(sc->sc_regh, (uint32_t )(sc->sc_base + reg), val); in iwn_write() 432 ddi_put8(sc->sc_regh, (uint8_t )(sc->sc_base + reg), val); in iwn_write_1() 439 ks = kstat_create(ddi_driver_name(sc->sc_dip), in iwn_kstat_create() 440 ddi_get_instance(sc->sc_dip), name, "misc", KSTAT_TYPE_NAMED, in iwn_kstat_create() [all …]
H A D	if_iwnreg.h	`4 /- 22 Copyright 2016 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> 52 /* Maximum number of DMA segments for TX. / 55 / RX buffers must be large enough to hold a full 4K A-MPDU. / 62 / HW supports 36-bit DMA addresses. / 110 Flow-Handler registers. 128 * TX scheduler registers. 147 * Offsets in TX scheduler's SRAM. 193 #define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 537 #define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) [all …]`
/illumos-gate/usr/src/uts/common/io/xge/hal/xgehal/
H A D	xgehal-device.c	21 * Copyright (c) 2002-2006 Neterion, Inc. 29 #include "xgehal-device.h" 30 #include "xgehal-channel.h" 31 #include "xgehal-fifo.h" 32 #include "xgehal-ring.h" 33 #include "xgehal-driver.h" 34 #include "xgehal-mgmt.h" 52 a -= b; a - 950 __hal_device_tti_apply(xge_hal_device_t * hldev,xge_hal_tti_config_t * tti,int num,int runtime) __hal_device_tti_apply() argument 6526 int fifo = channel->post_qid; xge_hal_channel_msi_set() local 6673 int fifo = channel->post_qid; xge_hal_channel_msix_set() local [all...]
/illumos-gate/usr/src/uts/common/io/e1000g/
H A D	e1000g_main.c	9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 304 * The 82546 chipset is a dual-port device, both the ports share one eeprom. 319 * _init - module initialization 340 * _fini - module finalization 361 e1000g_private_devi_list->next; in _fini() 363 kmem_free(devi_node->priv_dip, in _fini() 380 * _info - module information 389 * e1000g_attach - driver attach 391 * This function is the device-specific initialization entry 435 Adapter->dip = devinfo; in e1000g_attach() [all …]
/illumos-gate/usr/src/uts/common/io/iwk/
H A D	iwk2.c	91 #include "fw-iw/iw4965.ucode.hex" 175 * DMA attributes for a tx buffer. 180 * ability in the future, that is why we don't define rx and tx 301 static int iwk_division(int32_t num, int32_t denom, int32_t *res); 493 mutex_enter(&sc->sc_glock); in iwk_attach() 494 sc->sc_flags &= ~IWK_F_SUSPEND; in iwk_attach() 495 mutex_exit(&sc->sc_glock); in iwk_attach() 497 if (sc->sc_flags & IWK_F_RUNNING) in iwk_attach() 500 mutex_enter(&sc->sc_glock); in iwk_attach() 501 sc->sc_flags \|= IWK_F_LAZY_RESUME; in iwk_attach() [all …]
/illumos-gate/usr/src/uts/common/io/hxge/
H A D	hxge_peu_hw.h	230 * Master Data Parity Error - set if all the following conditions 234 * Fast Back-to-Back Capable (N/A in PCIE) 236 * Capabilities List - presence of extended capability item. 239 * Fast Back-to-Back Enable (N/A in PCIE) 244 * The device can issue Memory Write-and-Invalidate commands (N/A 346 * Multi-Function Device: dbi writeable 374 * Description: PIO BAR0 - For Hydra PIO space PIO BAR1 & PIO BAR0 432 * Description: MSIX BAR0 - For MSI-X Tables and PBA MSIX BAR1 & MSIX 489 * Description: Virtualization BAR0 - Previously for Hydra 566 * Subsystem ID as assigned by PCI-SIG : dbi writeable [all …]
/illumos-gate/usr/src/cmd/cxgbetool/
H A D	cudbg_view.c	167 c_buff->data = pbuf + entity_hdr->start_offset; in cudbg_view_decompress_buff() 169 if (entity_hdr->num_pad) in cudbg_view_decompress_buff() 170 c_buff->size = entity_hdr->size - entity_hdr->num_pad; in cudbg_view_decompress_buff() 172 c_buff->size = entity_hdr->size; in cudbg_view_decompress_buff() 173 c_buff->offset = 0; in cudbg_view_decompress_buff() 182 free(dc_buff->data); in cudbg_view_decompress_buff() 191 if (ver_hdr->signature == CUDBG_ENTITY_SIGNATURE) in get_entity_rev() 192 return ver_hdr->revision; in get_entity_rev() 210 return -1; in cudbg_find_changeset() 242 if ((cudbg_hdr->signature != CUDBG_SIGNATURE) && in validate_next_rec_offset() [all …]
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/
H A D	ecore_sp_verbs.c	75 #define ECORE_TODO_FW_COMMAND(_pdev, _drv_msg_code, _val) (-1) 81 pos = (cast )d_list_next_entry(&pos->_link)) 84 ECORE_LIST_FOR_EACH_ENTRY_SAFE - iterate over list of given type 94 n = (pos) ? (cast )d_list_next_entry(&pos->member) : NULL; \ 97 n = (pos) ? (cast )d_list_next_entry(&pos->member) : NULL) 99 #define ECORE_LIST_IS_LAST(_link, _list) (_link == (_list)->tail) 108 (cast )d_list_next_entry(&((pos)->link)) 258 ecore_exe_queue_init - init the Exe Queue object 280 ECORE_LIST_INIT(&o->exe_queue); in ecore_exe_queue_init() 281 ECORE_LIST_INIT(&o->pending_comp); in ecore_exe_queue_init() [all …]
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/common/
H A D	bnxe_clc.c	55 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1) 83 #define OFFSETOF(_s, _m) ((u32) ((u8 )(&((_s ) 0)->_m) - \ 148 #define CHIP_REV_SIM(_p) (((0xF - (CHIP_REV(_p) >> CHIP_REV_SHIFT)) \ 329 (_phy)->def_md_devad, \ 335 (_phy)->def_md_devad, \ 365 * elink_check_lfa - This function checks if link reinitialization is required, 378 struct elink_dev cb = params->cb; in elink_check_lfa() 381 REG_RD(cb, params->lfa_base + in elink_check_lfa() 384 / NOTE: must be first condition checked - in elink_check_lfa() 389 REG_WR(cb, params->lfa_base + in elink_check_lfa() [all …]