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/illumos-gate/usr/src/man/man8/
H A Dfcinfo.88 fcinfo, fcadm \- Fibre Channel HBA Port Command Line Interface
12 \fBfcinfo\fR hba-port [\fB-lite\fR] [\fIHBA_port_WWN\fR]...
17 \fBfcadm\fR hba-port [\fB-lite\fR] [\fIHBA_port_WWN\fR]...
22 \fBfcinfo\fR remote-port [\fB-ls\fR] [\fB-p\fR \fIHBA_port_WWN\fR]
28 \fBfcadm\fR remote-port [\fB-ls\fR] [\fB-p\fR \fIHBA_port_WWN\fR]
34 \fBfcinfo\fR logical-unit | lu [\fB-v\fR] [OS \fIdevice_path\fR]
39 \fBfcadm\fR logical-unit | lu [\fB-v\fR] [OS \fIdevice_path\fR]
44 \fBfcadm\fR create-npiv-port \fB-p\fR \fIVirtual_Port_WWN\fR [\fB-n\fR \fIVirtual_Node_WWN\fR]
50 \fBfcadm\fR delete-npiv-port \fB-p\fR \fIVirtual_Port_WWN\fR [\fB-n\fR \fIVirtual_Node_WWN\fR]
56 \fBfcadm\fR create-fcoe-port [\fB-tf\fR] \fB-p\fR \fIPort_WWN\fR [\fB-n\fR \fINode_WWN\fR]
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/illumos-gate/usr/src/uts/common/io/ena/
H A Dena.h52 * The minimum supported ENA device controller version.
81 #define ENA_INTERRUPT_MODE -1
93 * device. We default to half a second.
103 * The device sends a keepalive message every second. If we don't see any for
104 * a while we will trigger a device reset. Other open source drivers use
110 * The number of consecutive times a TX queue needs to be seen as blocked by
136 #define ENA_DMA_BIT_MASK(x) ((1ULL << (x)) - 1ULL)
138 VERIFY3U(ENA_DMA_BIT_MASK((ena)->ena_dma_width) & (phys_addr), \
202 * them to device responses.
230 * device.
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H A Dena.c21 * ------------------------------------
23 * The ena driver provides support for the AWS ENA device, also
24 * referred to as their "enhanced networking". This device is present
25 * on "Nitro"-based instances. It presents itself with the following
26 * PCI Vendor/Device IDs
28 * o 1d0f:0ec2 -- ENA PF
29 * o 1d0f:1ec2 -- ENA PF (Reserved)
30 * o 1d0f:ec20 -- ENA VF
31 * o 1d0f:ec21 -- ENA VF (Reserved)
34 * to drive traffic on an ENA device. Support for the following
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H A Dena_hw.h18 * physical ENA device. It is based on the ena_com code of the public
24 * The Linux driver defines enq_admin_aq_entry as the top-level type
28 * present for _some_ commands. Other than that, this top-level type
29 * treats the rest of the data as an opaque array of unsigned 32-bit
37 * 3. The command-specific data.
42 * are made up of several sub-commands, e.g. the get/set feature
47 * a pointer to the top-level type: ena_admin_aq_entry.
52 * turned the Linux approach inside out -- the top-level type is a
54 * then further sub-type via unions to represent its sub-commands.
83 * 128 Tx rings, and 128 Rx rings; though, practically speaking, the
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/illumos-gate/usr/src/uts/common/io/igc/
H A Digc.c18 * ------------------------------
21 * controllers which support up to 2.5 GbE and generally only supports BASE-T
22 * copper phys. This device is yet another variant on the venerable Intel 1 GbE
38 * 1) We believe that the device only supports up to 4 RX and TX queues.
39 * 2) There is only one TX context for each TX queue and it is mapped to the
42 * 4) This does otherwise support both the MSI-X and MSI/INTx interrupt
43 * management which are shaped very differently in the device.
44 * 5) The 2500BASE-T PHY support is unique, but the other PHY settings are
50 * ------------
52 * ------------
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H A Digc.h49 * Maximum number of RX and TX rings that it appears the hardware supports. The
50 * strict maximum segment size that the device can take is basically 9 KiB
63 * These are the default auto-negotiation values the device supports which is
78 * threshold for rx mostly by surveying others. For tx, we picked 512 as that's
89 * These numbers deal with the tx ring, blocking, recycling, and notification
96 * check during tx of 32, which is about 6.25% of the default ring size.
116 * 4-byte aligned.
121 * The buffer sizes that hardware uses for rx and tx are required to be 1 KiB
130 #define IGC_RX_POLL_INTR -1
143 #define IGC_DMA_SYNC(buf, flag) ASSERT0(ddi_dma_sync((buf)->idb_hdl, \
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/illumos-gate/usr/src/uts/common/io/udmf/
H A Ddm9601reg.h15 #define TCR 0x02U /* tx control register */
16 #define TSR1 0x03U /* tx status register 1 */
17 #define TSR2 0x04U /* tx status register 2 */
35 #define USBDA 0xf0U /* usb device address register */
37 #define TUSC 0xf2U /* tx packet counter/usb status register */
68 #define NSR_TXFULL 0x10U /* 1:tx fifo full */
69 #define NSR_TX2END 0x08U /* tx packet2 complete status */
70 #define NSR_TX1END 0x04U /* tx packet1 complete status */
85 /* tx control register */
86 #define TCR_TJDIS 0x40U /* tx jitter control */
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/illumos-gate/usr/src/uts/common/io/vr/
H A Dvr.c61 * (TX) and one for receive (RX).
71 * Each transmit descriptor has a DMA buffer attached to it. The data of TX
95 * Attributes for accessing registers and memory descriptors for this device.
113 * DMA attributes for descriptors for communication with the device
129 1, /* granularity of device */
134 * DMA attributes for the data moved to/from the device
150 1, /* granularity of device */
157 vr_mac_start, /* Start the device */
158 vr_mac_stop, /* Stop the device */
166 NULL, /* Open the device */
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/illumos-gate/usr/src/uts/common/fs/zfs/
H A Dvdev_removal.c61 * a multi-step process:
63 * - Disable allocations from this device (spa_vdev_remove_top).
65 * - From a new thread (spa_vdev_remove_thread), copy data from
71 * - If a free happens during a removal, it is freed from the
75 * - After the removal is completed, the copy thread converts the vdev
90 * doing a device removal. This determines how much i/o we can have
97 * removing a device. This can be no larger than SPA_MAXBLOCKSIZE. If
105 * the I/O and hang the device.)
112 * contiguous chunks, with more "unnecessary" data -- trading off bandwidth
119 * - the mapping will be smaller, since one entry can cover more allocated
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/illumos-gate/usr/src/uts/common/io/iwk/
H A Diwk_hw.h21 * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
41 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
42 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
46 * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
98 * TFDB Area - TFDs buffer table
104 * channels 0 - 8
110 * TFDIB Area - TFD Immediate Buffer
116 * channels 0 - 10
129 * Tx service channels
148 * TRB Area - Transmit Request Buffers
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/illumos-gate/usr/src/uts/sun4v/io/
H A Dcnex.c29 * in software; cnex is the nexus for channel-devices. They use
104 * they are removed in converse order--compared to the order they
108 * Channel interrupt weights affect interrupt-CPU distribution
127 * 0x8 - Errors
128 * 0x4 - Warnings
129 * 0x2 - All debug messages
130 * 0x1 - Minimal debug messages
254 "sun4v channel-devices nexus",
330 mutex_enter(&cnex_ssp->clist_lock); in cnex_intr_redist()
332 cldcp = cnex_ssp->clist; in cnex_intr_redist()
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/illumos-gate/usr/src/uts/common/io/dmfe/
H A Ddmfe_main.c44 * DMFE_PCI_RNUMBER is the register-set number to use for the operating
45 * registers. On an OBP-based machine, regset 0 refers to CONFIG space,
51 * the end of a buffer or descriptor, apparently 6-8 dwords :(
59 * However, the buffer length field in the TX/RX descriptors is only
71 * has been stripped off, the packet data will be 4-byte aligned.
86 * to make the chip spontaneously reset internally - it
88 * writing to PCI address 00000000 - which may or may not
89 * get a MASTER ABORT - after which most of its registers
94 * too, just in case it has some other wierd side-effect.
119 * Number of RX/TX ring entries (128/128)
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/illumos-gate/usr/src/uts/common/io/xge/hal/include/
H A Dxgehal-types.h21 * Copyright (c) 2002-2006 Neterion, Inc.
27 #include "xge-os-pal.h"
32 * BIT(loc) - set bit at offset
37 * vBIT(val, loc, sz) - set bits at offset
39 #define vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz)))
40 #define vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz)))
43 * bVALx(bits, loc) - Get the value of x bits at location
45 #define bVAL1(bits, loc) ((((u64)bits) >> (64-(loc+1))) & 0x1)
46 #define bVAL2(bits, loc) ((((u64)bits) >> (64-(loc+2))) & 0x3)
47 #define bVAL3(bits, loc) ((((u64)bits) >> (64-(loc+3))) & 0x7)
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/illumos-gate/usr/src/uts/common/io/mac/
H A Dmac_sched.c32 * The MAC data path is concerned with the flow of traffic from mac clients --
33 * DLS, IP, etc. -- to various GLDv3 device drivers -- e1000g, vnic, aggr,
34 * ixgbe, etc. -- and from the GLDv3 device drivers back to clients.
36 * -----------
38 * -----------
46 * This driver. It interfaces with device drivers and provides abstractions
47 * that the rest of the system consumes. All data links -- things managed
50 * GLDv3 DEVICE DRIVER
52 * A GLDv3 device driver refers to a driver, both for pseudo-devices and
56 * hardware rings and checksum offloading. For MAC, a GLDv3 device is the
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/illumos-gate/usr/src/man/man4d/
H A Ddmfe.4d8 dmfe \- Davicom Fast Ethernet driver for Davicom DM9102A
18 The \fBdmfe\fR Ethernet device provides 100Base-TX networking interfaces using
28 The 100Base-TX standard specifies an auto-negotiation protocol to automatically
30 performing auto-negotiation with the remote-end of the link (link partner) and
33 also supports a forced-mode of operation under which the driver selects the
38 The \fB/dev/dmfe\fR cloning character-special device is used to access all
43 with a particular device (ppa). The ppa ID is interpreted as an unsigned
44 integer data type and indicates the corresponding device instance (unit)
45 number. If the ppa field value does not correspond to a valid device instance
46 number for this system, an error (DL_ERROR_ACK) is returned. The device is
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/illumos-gate/usr/src/uts/common/io/ath/
H A Dath_impl.h7 * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
20 * 3. Neither the names of the above-listed copyright holders nor the names
75 #define ATH_DBG_RECV 0x00000010 /* receive-side code */
76 #define ATH_DBG_SEND 0x00000020 /* packet-send code */
99 * Node type of wifi device
108 #define list_empty(a) ((a)->list_head.list_next == &(a)->list_head)
114 #define ATH_TXQ_SETUP(asc, i) ((asc)->asc_txqsetup & (1<<i))
116 ((struct ath_desc *)((caddr_t)(_asc)->asc_desc + \
117 ((_pa) - (_asc)->asc_desc_dma.cookie.dmac_address)))
127 #define ATH_TXBUF 200 /* number of TX buffers */
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/illumos-gate/usr/src/uts/common/io/nxge/
H A Dnxge_intr.c30 * This file manages the interrupts for a hybrid I/O (hio) device.
31 * In the future, it may manage interrupts for all Neptune-based
59 * type Tx or Rx
76 nxge_ldg_t *group; /* The logical device group data. */ in nxge_intr_add()
86 if ((vector = nxge_intr_vec_find(nxge, type, channel)) == -1) { in nxge_intr_add()
92 ldvp = &nxge->ldgvp->ldvp[vector]; in nxge_intr_add()
93 group = ldvp->ldgp; in nxge_intr_add()
95 if (group->nldvs == 1) { in nxge_intr_add()
96 inthandler = group->ldvp->ldv_intr_handler; in nxge_intr_add()
97 } else if (group->nldvs > 1) { in nxge_intr_add()
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/illumos-gate/usr/src/uts/common/io/xge/hal/xgehal/
H A Dxgehal-device-fp.c21 * Copyright (c) 2002-2006 Neterion, Inc.
30 #include "xgehal-device.h"
33 #include "xgehal-ring.h"
34 #include "xgehal-fifo.h"
37 * xge_hal_device_bar0 - Get BAR0 mapped address.
38 * @hldev: HAL device handle.
40 * Returns: BAR0 address of the specified device.
45 return hldev->bar0; in xge_hal_device_bar0()
49 * xge_hal_device_isrbar0 - Get BAR0 mapped address.
50 * @hldev: HAL device handle.
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/illumos-gate/usr/src/uts/sun4v/sys/
H A Dvsw_ldc.h32 * can support communications to a single network device). The
42 * The ldc is a bi-directional channel, which is divided up into
44 * virtual network device, the other inbound to the switch.
45 * Depending on the type of device each lane may have seperate
58 * +----->port_t----->port_t----->port_t----->
60 * +--->ldc_t
62 * +--->lane_t (inbound)
64 * | +--->dring
66 * +--->lane_t (outbound)
68 * +--->dring
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H A Dvnet.h41 #define VNET_FAILURE (-1) /* unsuccessful return */
48 (ether_cmp(&ehp->ether_dhost, &etherbroadcastaddr) == 0)
50 ((ehp->ether_dhost.ether_addr_octet[0] & 01) == 1)
53 (ether_cmp(vresp->local_macaddr, vnetp->curr_macaddr) == 0)
56 * Flags used to indicate the state of the vnet device and its associated
69 uint64_t opackets; /* # tx packets */
70 uint64_t oerrors; /* # tx error */
93 kstat_named_t rbytes; /* MIB - ifInOctets */
95 kstat_named_t obytes; /* MIB - ifOutOctets */
97 kstat_named_t multircv; /* MIB - ifInNUcastPkts */
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/illumos-gate/usr/src/uts/common/io/qede/579xx/drivers/ecore/
H A Decore_init_fw_funcs.h9 * or http://opensource.org/licenses/CDDL-1.0.
23 * Copyright 2014-2017 Cavium, Inc.
30 * at http://opensource.org/licenses/CDDL-1.0
43 * @brief ecore_qm_pf_mem_size - Prepare QM ILT sizes
48 * @param pf_id - physical function ID
49 * @param num_pf_cids - number of connections used by this PF
50 * @param num_vf_cids - number of connections used by VFs of this PF
51 * @param num_tids - number of tasks used by this PF
52 * @param num_pf_pqs - number of PQs used by this PF
53 * @param num_vf_pqs - number of PQs used by VFs of this PF
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/illumos-gate/usr/src/uts/sun/io/eri/
H A Deri.h69 * MAC TX Event stats
168 #define HSTAT(erip, x) erip->stats.x++;
169 #define HSTATN(erip, x, n) erip->stats.x += n;
175 * Per-Stream instance state information.
178 * at close(). Each per-Stream instance points to at most one
179 * per-device structure using the sb_erip field. All instances
181 * ordered on minor device number.
190 #define ERI_RPENDING (erip->rpending)
195 #define ERI_TPENDING (erip->tpending)
200 #define NEXTRMD(erip, rmdp) (((rmdp) + 1) == (erip)->rmdlimp ? \
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/illumos-gate/usr/src/uts/common/io/arn/
H A Darn_core.h39 * Node type of wifi device
46 #define ARN_LOCK(_sc) mutex_enter(&(_sc)->sc_genlock)
47 #define ARN_UNLOCK(_sc) mutex_exit(&(_sc)->sc_genlock)
48 #define ARN_LOCK_ASSERT(_sc) ASSERT(mutex_owned(&(_sc)->sc_genlock))
52 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
57 #define abs(x) ((x) >= 0 ? (x) : -(x))
70 #define list_empty(a) ((a)->list_head.list_next == &(a)->list_head)
71 #define list_d2l(a, obj) ((list_node_t *)(((char *)obj) + (a)->list_offset))
72 #define list_object(a, node) ((void *)(((char *)node) - (a)->list_offset))
74 ((type *)((char *)(ptr)-(unsigned long)(&((type *)0)->member)))
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/illumos-gate/usr/src/uts/common/io/iwp/
H A Diwp_hw.h18 * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved.
38 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
39 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
43 * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved.
95 * TFDB Area - TFDs buffer table
101 * channels 0 - 8
107 * TFDIB Area - TFD Immediate Buffer
113 * channels 0 - 10
126 * Tx service channels
145 * TRB Area - Transmit Request Buffers
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/illumos-gate/usr/src/uts/common/io/iwh/
H A Diwh_hw.h21 * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved.
41 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
42 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
46 * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved.
98 * TFDB Area - TFDs buffer table
104 * channels 0 - 8
110 * TFDIB Area - TFD Immediate Buffer
116 * channels 0 - 10
129 * Tx service channels
148 * TRB Area - Transmit Request Buffers
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