Lines Matching +full:tx +full:- +full:device
61 * (TX) and one for receive (RX).
71 * Each transmit descriptor has a DMA buffer attached to it. The data of TX
95 * Attributes for accessing registers and memory descriptors for this device.
113 * DMA attributes for descriptors for communication with the device
129 1, /* granularity of device */
134 * DMA attributes for the data moved to/from the device
150 1, /* granularity of device */
157 vr_mac_start, /* Start the device */
158 vr_mac_stop, /* Stop the device */
166 NULL, /* Open the device */
167 NULL, /* Close the device */
168 vr_mac_setprop, /* Set properties of the device */
169 vr_mac_getprop, /* Get properties of the device */
193 "VIA VT6102-A Rhine II Fast Ethernet",
199 "VIA VT6102-C Rhine II Fast Ethernet",
205 "VIA VT6105-A Rhine III Fast Ethernet",
211 "VIA VT6105-B Rhine III Fast Ethernet",
217 "VIA VT6105-LOM Rhine III Fast Ethernet",
223 "VIA VT6107-A0 Rhine III Fast Ethernet",
229 "VIA VT6107-A1 Rhine III Fast Ethernet",
236 "VIA VT6105M-A0 Rhine III Fast Ethernet Management Adapter",
245 "VIA VT6105M-B1 Rhine III Fast Ethernet Management Adapter",
312 vrp->devinfo = devinfo; in vr_attach()
317 (void) snprintf(vrp->ifname, sizeof (vrp->ifname), "%s%d", in vr_attach()
357 mutex_init(&vrp->intrlock, NULL, MUTEX_DRIVER, in vr_attach()
358 DDI_INTR_PRI(vrp->intr_pri)); in vr_attach()
359 mutex_init(&vrp->oplock, NULL, MUTEX_DRIVER, NULL); in vr_attach()
360 mutex_init(&vrp->tx.lock, NULL, MUTEX_DRIVER, NULL); in vr_attach()
365 if (ddi_intr_enable(vrp->intr_hdl) != DDI_SUCCESS) { in vr_attach()
378 macreg->m_type_ident = MAC_PLUGIN_IDENT_ETHER; in vr_attach()
379 macreg->m_driver = vrp; in vr_attach()
380 macreg->m_dip = devinfo; in vr_attach()
381 macreg->m_src_addr = vrp->vendor_ether_addr; in vr_attach()
382 macreg->m_callbacks = &vr_mac_callbacks; in vr_attach()
383 macreg->m_min_sdu = 0; in vr_attach()
384 macreg->m_max_sdu = ETHERMTU; in vr_attach()
385 macreg->m_margin = VLAN_TAGSZ; in vr_attach()
387 if (mac_register(macreg, &vrp->machdl) != 0) { in vr_attach()
397 (void) ddi_intr_disable(vrp->intr_hdl); in vr_attach()
399 mutex_destroy(&vrp->tx.lock); in vr_attach()
400 mutex_destroy(&vrp->oplock); in vr_attach()
401 mutex_destroy(&vrp->intrlock); in vr_attach()
426 if (vrp->chip.state == CHIPSTATE_RUNNING) in vr_detach()
430 * Try to un-register from the MAC layer. in vr_detach()
432 if (mac_unregister(vrp->machdl) != 0) in vr_detach()
435 (void) ddi_intr_disable(vrp->intr_hdl); in vr_detach()
437 mutex_destroy(&vrp->tx.lock); in vr_detach()
438 mutex_destroy(&vrp->oplock); in vr_detach()
439 mutex_destroy(&vrp->intrlock); in vr_detach()
460 VR_PUT16(vrp->acc_reg, VR_ICR0, 0); in vr_quiesce()
461 VR_PUT8(vrp->acc_reg, VR_ICR1, 0); in vr_quiesce()
466 VR_PUT8(vrp->acc_reg, VR_CTRL0, VR_CTRL0_DMA_STOP); in vr_quiesce()
471 * Add an interrupt for our device to the OS.
479 rc = ddi_intr_alloc(vrp->devinfo, &vrp->intr_hdl, in vr_add_intr()
491 rc = ddi_intr_add_handler(vrp->intr_hdl, vr_intr, vrp, NULL); in vr_add_intr()
494 if (ddi_intr_free(vrp->intr_hdl) != DDI_SUCCESS) in vr_add_intr()
499 rc = ddi_intr_get_pri(vrp->intr_hdl, &vrp->intr_pri); in vr_add_intr()
502 if (ddi_intr_remove_handler(vrp->intr_hdl) != DDI_SUCCESS) in vr_add_intr()
505 if (ddi_intr_free(vrp->intr_hdl) != DDI_SUCCESS) in vr_add_intr()
519 if (ddi_intr_remove_handler(vrp->intr_hdl) != DDI_SUCCESS) in vr_remove_intr()
522 if (ddi_intr_free(vrp->intr_hdl) != DDI_SUCCESS) in vr_remove_intr()
535 mutex_enter(&vrp->oplock); in vr_resume()
536 if (vrp->chip.state == CHIPSTATE_SUSPENDED_RUNNING) in vr_resume()
538 mutex_exit(&vrp->oplock); in vr_resume()
551 mutex_enter(&vrp->oplock); in vr_suspend()
552 if (vrp->chip.state == CHIPSTATE_RUNNING) { in vr_suspend()
554 vrp->chip.state = CHIPSTATE_SUSPENDED_RUNNING; in vr_suspend()
556 mutex_exit(&vrp->oplock); in vr_suspend()
561 * Initial bus- and device configuration during attach(9E).
574 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, vrp->devinfo, in vr_bus_config()
584 vrp->nsets = nsets; in vr_bus_config()
585 vrp->regset = kmem_zalloc(nsets * sizeof (vr_acc_t), KM_SLEEP); in vr_bus_config()
587 rc = ddi_regs_map_setup(vrp->devinfo, n, in vr_bus_config()
588 &vrp->regset[n].addr, 0, 0, in vr_bus_config()
590 &vrp->regset[n].hdl); in vr_bus_config()
594 while (--n >= 0) in vr_bus_config()
595 ddi_regs_map_free(&vrp->regset[n].hdl); in vr_bus_config()
596 kmem_free(vrp->regset, nsets * sizeof (vr_acc_t)); in vr_bus_config()
600 bcopy(®s[n], &vrp->regset[n].reg, sizeof (pci_regspec_t)); in vr_bus_config()
605 * Assign type-named pointers to the register sets. in vr_bus_config()
608 addr = vrp->regset[n].reg.pci_phys_hi & PCI_REG_ADDR_M; in vr_bus_config()
609 if (addr == PCI_ADDR_CONFIG && vrp->acc_cfg == NULL) in vr_bus_config()
610 vrp->acc_cfg = &vrp->regset[n]; in vr_bus_config()
611 else if (addr == PCI_ADDR_IO && vrp->acc_io == NULL) in vr_bus_config()
612 vrp->acc_io = &vrp->regset[n]; in vr_bus_config()
613 else if (addr == PCI_ADDR_MEM32 && vrp->acc_mem == NULL) in vr_bus_config()
614 vrp->acc_mem = &vrp->regset[n]; in vr_bus_config()
620 if (vrp->acc_cfg == NULL || in vr_bus_config()
621 vrp->acc_io == NULL || in vr_bus_config()
622 vrp->acc_mem == NULL) { in vr_bus_config()
624 ddi_regs_map_free(&vrp->regset[n].hdl); in vr_bus_config()
625 kmem_free(vrp->regset, nsets * sizeof (vr_acc_t)); in vr_bus_config()
627 "Config-, I/O- and memory sets not available"); in vr_bus_config()
632 * Store vendor/device/revision. in vr_bus_config()
634 vrp->chip.vendor = VR_GET16(vrp->acc_cfg, PCI_CONF_VENID); in vr_bus_config()
635 vrp->chip.device = VR_GET16(vrp->acc_cfg, PCI_CONF_DEVID); in vr_bus_config()
636 vrp->chip.revision = VR_GET16(vrp->acc_cfg, PCI_CONF_REVID); in vr_bus_config()
643 if (vrp->chip.revision >= vr_chip_info[n].revmin && in vr_bus_config()
644 vrp->chip.revision <= vr_chip_info[n].revmax) { in vr_bus_config()
646 (void*)&vrp->chip.info, in vr_bus_config()
657 if (vrp->chip.info.name[0] == '\0') { in vr_bus_config()
659 (void*) &vrp->chip.info, in vr_bus_config()
667 PCI_REG_BUS_G(vrp->acc_cfg->reg.pci_phys_hi), in vr_bus_config()
668 PCI_REG_DEV_G(vrp->acc_cfg->reg.pci_phys_hi), in vr_bus_config()
669 PCI_REG_FUNC_G(vrp->acc_cfg->reg.pci_phys_hi), in vr_bus_config()
670 vrp->chip.info.name, in vr_bus_config()
671 vrp->chip.revision); in vr_bus_config()
674 * Assure that the device is prepared for memory space accesses in vr_bus_config()
675 * This should be the default as the device advertises memory in vr_bus_config()
679 VR_SETBIT8(vrp->acc_io, VR_CFGD, VR_CFGD_MMIOEN); in vr_bus_config()
684 if (vrp->acc_mem != NULL && in vr_bus_config()
685 (vrp->chip.info.bugs & VR_BUG_NO_MEMIO) == 0) in vr_bus_config()
686 vrp->acc_reg = vrp->acc_mem; in vr_bus_config()
688 vrp->acc_reg = vrp->acc_io; in vr_bus_config()
694 vrp->vendor_ether_addr[n] = VR_GET8(vrp->acc_reg, in vr_bus_config()
708 for (n = 0; n < vrp->nsets; n++) in vr_bus_unconfig()
709 ddi_regs_map_free(&vrp->regset[n].hdl); in vr_bus_unconfig()
710 kmem_free(vrp->regset, vrp->nsets * sizeof (vr_acc_t)); in vr_bus_unconfig()
722 vrp->param.an_en = VR_LINK_AUTONEG_ON; in vr_param_init()
723 vrp->param.anadv_en = 1; /* Select 802.3 autonegotiation */ in vr_param_init()
724 vrp->param.anadv_en |= MII_ABILITY_100BASE_T4; in vr_param_init()
725 vrp->param.anadv_en |= MII_ABILITY_100BASE_TX_FD; in vr_param_init()
726 vrp->param.anadv_en |= MII_ABILITY_100BASE_TX; in vr_param_init()
727 vrp->param.anadv_en |= MII_ABILITY_10BASE_T_FD; in vr_param_init()
728 vrp->param.anadv_en |= MII_ABILITY_10BASE_T; in vr_param_init()
730 vrp->param.anadv_en |= MII_ABILITY_PAUSE; in vr_param_init()
731 vrp->param.mtu = ETHERMTU; in vr_param_init()
736 vr_phy_read(vrp, MII_PHYIDH, &vrp->chip.mii.identh); in vr_param_init()
737 vr_phy_read(vrp, MII_PHYIDL, &vrp->chip.mii.identl); in vr_param_init()
742 vrp->param.an_phymask = vrp->param.anadv_en; in vr_param_init()
743 vr_phy_read(vrp, MII_STATUS, &vrp->chip.mii.status); in vr_param_init()
744 if ((vrp->chip.mii.status & MII_STATUS_10) == 0) in vr_param_init()
745 vrp->param.an_phymask &= ~MII_ABILITY_10BASE_T; in vr_param_init()
747 if ((vrp->chip.mii.status & MII_STATUS_10_FD) == 0) in vr_param_init()
748 vrp->param.an_phymask &= ~MII_ABILITY_10BASE_T_FD; in vr_param_init()
750 if ((vrp->chip.mii.status & MII_STATUS_100_BASEX) == 0) in vr_param_init()
751 vrp->param.an_phymask &= ~MII_ABILITY_100BASE_TX; in vr_param_init()
753 if ((vrp->chip.mii.status & MII_STATUS_100_BASEX_FD) == 0) in vr_param_init()
754 vrp->param.an_phymask &= ~MII_ABILITY_100BASE_TX_FD; in vr_param_init()
756 if ((vrp->chip.mii.status & MII_STATUS_100_BASE_T4) == 0) in vr_param_init()
757 vrp->param.an_phymask &= ~MII_ABILITY_100BASE_T4; in vr_param_init()
766 vrp->param.an_macmask = vrp->param.anadv_en; in vr_param_init()
771 vrp->chip.mii.anadv = vrp->param.anadv_en & in vr_param_init()
772 (vrp->param.an_phymask & vrp->param.an_macmask); in vr_param_init()
777 if (vrp->param.an_en == VR_LINK_AUTONEG_ON) in vr_param_init()
778 vrp->chip.mii.control = MII_CONTROL_ANE; in vr_param_init()
780 vrp->chip.mii.control = in vr_param_init()
791 vrp->rx.ndesc = VR_RX_N_DESC; in vr_rings_init()
792 vrp->tx.ndesc = VR_TX_N_DESC; in vr_rings_init()
797 if (vr_alloc_ring(vrp, &vrp->rxring, vrp->rx.ndesc) != VR_SUCCESS) in vr_rings_init()
803 if (vr_alloc_ring(vrp, &vrp->txring, vrp->tx.ndesc) != VR_SUCCESS) { in vr_rings_init()
804 vr_free_ring(&vrp->rxring, vrp->rx.ndesc); in vr_rings_init()
808 vrp->rx.ring = vrp->rxring.desc; in vr_rings_init()
809 vrp->tx.ring = vrp->txring.desc; in vr_rings_init()
816 vr_free_ring(&vrp->rxring, vrp->rx.ndesc); in vr_rings_fini()
817 vr_free_ring(&vrp->txring, vrp->tx.ndesc); in vr_rings_fini()
838 rc = ddi_dma_alloc_handle(vrp->devinfo, in vr_alloc_ring()
842 &ring->handle); in vr_alloc_ring()
853 rc = ddi_dma_mem_alloc(ring->handle, in vr_alloc_ring()
859 (caddr_t *)&ring->cdesc, in vr_alloc_ring()
861 &ring->acchdl); in vr_alloc_ring()
866 ddi_dma_free_handle(&ring->handle); in vr_alloc_ring()
873 rc = ddi_dma_addr_bind_handle(ring->handle, in vr_alloc_ring()
875 (caddr_t)ring->cdesc, in vr_alloc_ring()
887 ddi_dma_mem_free(&ring->acchdl); in vr_alloc_ring()
888 ddi_dma_free_handle(&ring->handle); in vr_alloc_ring()
891 ring->cdesc_paddr = desc_dma_cookie.dmac_address; in vr_alloc_ring()
896 ring->desc = in vr_alloc_ring()
900 * Interlink the descriptors and connect host- to chip descriptors. in vr_alloc_ring()
906 ring->desc[i].cdesc = &ring->cdesc[i]; in vr_alloc_ring()
910 * Offset is for ddi_dma_sync() and paddr is for ddi_get/-put(). in vr_alloc_ring()
912 ring->desc[i].offset = i * sizeof (vr_chip_desc_t); in vr_alloc_ring()
913 ring->desc[i].paddr = ring->cdesc_paddr + ring->desc[i].offset; in vr_alloc_ring()
920 ring->desc[i-1].next = &ring->desc[i]; in vr_alloc_ring()
923 ddi_put32(ring->acchdl, in vr_alloc_ring()
924 &ring->cdesc[i-1].next, in vr_alloc_ring()
925 ring->desc[i].paddr); in vr_alloc_ring()
932 i = n - 1; in vr_alloc_ring()
933 ring->desc[i].next = &ring->desc[0]; in vr_alloc_ring()
934 ddi_put32(ring->acchdl, &ring->cdesc[i].next, ring->desc[0].paddr); in vr_alloc_ring()
947 (void) ddi_dma_unbind_handle(r->handle); in vr_free_ring()
948 ddi_dma_mem_free(&r->acchdl); in vr_free_ring()
949 ddi_dma_free_handle(&r->handle); in vr_free_ring()
954 kmem_free(r->desc, n * sizeof (vr_desc_t)); in vr_free_ring()
969 vrp->rx.rp = &vrp->rx.ring[0]; in vr_rxring_init()
974 for (i = 0; i < vrp->rx.ndesc; i++) { in vr_rxring_init()
975 rp = &vrp->rx.ring[i]; in vr_rxring_init()
977 &vrp->rx.ring[i].dmabuf, in vr_rxring_init()
981 while (--i >= 0) in vr_rxring_init()
982 vr_free_dmabuf(&vrp->rx.ring[i].dmabuf); in vr_rxring_init()
989 ddi_put32(vrp->rxring.acchdl, in vr_rxring_init()
990 &rp->cdesc->data, in vr_rxring_init()
991 rp->dmabuf.paddr); in vr_rxring_init()
997 ddi_put32(vrp->rxring.acchdl, &rp->cdesc->stat1, in vr_rxring_init()
998 MIN(VR_MAX_PKTSZ, rp->dmabuf.bufsz)); in vr_rxring_init()
1003 ddi_put32(vrp->rxring.acchdl, &rp->cdesc->stat0, VR_RDES0_OWN); in vr_rxring_init()
1008 (void) ddi_dma_sync(vrp->rxring.handle, rp->offset, in vr_rxring_init()
1022 for (i = 0; i < vrp->rx.ndesc; i++) in vr_rxring_fini()
1023 vr_free_dmabuf(&vrp->rx.ring[i].dmabuf); in vr_rxring_fini()
1033 * Set the write- and claim pointer. in vr_txring_init()
1035 vrp->tx.wp = &vrp->tx.ring[0]; in vr_txring_init()
1036 vrp->tx.cp = &vrp->tx.ring[0]; in vr_txring_init()
1039 * (Re)set the TX bookkeeping. in vr_txring_init()
1041 vrp->tx.stallticks = 0; in vr_txring_init()
1042 vrp->tx.resched = 0; in vr_txring_init()
1047 vrp->tx.nfree = vrp->tx.ndesc; in vr_txring_init()
1052 for (i = 0; i < vrp->tx.ndesc; i++) { in vr_txring_init()
1054 &vrp->tx.ring[i].dmabuf, in vr_txring_init()
1058 while (--i >= 0) in vr_txring_init()
1059 vr_free_dmabuf(&vrp->tx.ring[i].dmabuf); in vr_txring_init()
1065 * Init & sync the TX descriptors so the device sees a valid ring. in vr_txring_init()
1067 for (i = 0; i < vrp->tx.ndesc; i++) { in vr_txring_init()
1068 wp = &vrp->tx.ring[i]; in vr_txring_init()
1069 ddi_put32(vrp->txring.acchdl, &wp->cdesc->stat0, 0); in vr_txring_init()
1070 ddi_put32(vrp->txring.acchdl, &wp->cdesc->stat1, 0); in vr_txring_init()
1071 ddi_put32(vrp->txring.acchdl, &wp->cdesc->data, in vr_txring_init()
1072 wp->dmabuf.paddr); in vr_txring_init()
1073 (void) ddi_dma_sync(vrp->txring.handle, wp->offset, in vr_txring_init()
1081 * Free the DMA buffers attached to the TX ring.
1089 * Free the DMA buffers attached to the TX ring in vr_txring_fini()
1091 for (i = 0; i < vrp->tx.ndesc; i++) in vr_txring_fini()
1092 vr_free_dmabuf(&vrp->tx.ring[i].dmabuf); in vr_txring_fini()
1108 rc = ddi_dma_alloc_handle(vrp->devinfo, in vr_alloc_dmabuf()
1111 &dmap->handle); in vr_alloc_dmabuf()
1125 rc = ddi_dma_mem_alloc(dmap->handle, in vr_alloc_dmabuf()
1130 &dmap->buf, in vr_alloc_dmabuf()
1131 &dmap->bufsz, in vr_alloc_dmabuf()
1132 &dmap->acchdl); in vr_alloc_dmabuf()
1137 ddi_dma_free_handle(&dmap->handle); in vr_alloc_dmabuf()
1144 rc = ddi_dma_addr_bind_handle(dmap->handle, in vr_alloc_dmabuf()
1146 (caddr_t)dmap->buf, in vr_alloc_dmabuf()
1147 dmap->bufsz, in vr_alloc_dmabuf()
1161 ddi_dma_mem_free(&dmap->acchdl); in vr_alloc_dmabuf()
1162 ddi_dma_free_handle(&dmap->handle); in vr_alloc_dmabuf()
1165 dmap->paddr = dma_cookie.dmac_address; in vr_alloc_dmabuf()
1175 (void) ddi_dma_unbind_handle(dmap->handle); in vr_free_dmabuf()
1176 ddi_dma_mem_free(&dmap->acchdl); in vr_free_dmabuf()
1177 ddi_dma_free_handle(&dmap->handle); in vr_free_dmabuf()
1182 * When our vector is shared with another device, av_dispatch_autovect calls
1201 mutex_enter(&vrp->intrlock); in vr_intr()
1206 if (vrp->chip.state != CHIPSTATE_RUNNING) { in vr_intr()
1207 mutex_exit(&vrp->intrlock); in vr_intr()
1212 * Read the status register to see if the interrupt is from our device in vr_intr()
1215 status = VR_GET16(vrp->acc_reg, VR_ISR0) & VR_ICR0_CFG; in vr_intr()
1219 * The interrupt was not generated by our device. in vr_intr()
1221 vrp->stats.intr_unclaimed++; in vr_intr()
1222 mutex_exit(&vrp->intrlock); in vr_intr()
1225 vrp->stats.intr_claimed++; in vr_intr()
1230 VR_PUT16(vrp->acc_reg, VR_ISR0, status); in vr_intr()
1245 VR_PUT8(vrp->acc_reg, VR_CTRL0, VR_CTRL0_DMA_GO); in vr_intr()
1259 mutex_enter(&vrp->tx.lock); in vr_intr()
1261 tx_resched = vrp->tx.resched; in vr_intr()
1262 vrp->tx.resched = 0; in vr_intr()
1263 mutex_exit(&vrp->tx.lock); in vr_intr()
1274 mutex_enter(&vrp->oplock); in vr_intr()
1275 mutex_enter(&vrp->tx.lock); in vr_intr()
1277 mutex_exit(&vrp->tx.lock); in vr_intr()
1278 mutex_exit(&vrp->oplock); in vr_intr()
1280 vrp->stats.linkchanges++; in vr_intr()
1289 vrp->reset = 1; in vr_intr()
1297 mutex_exit(&vrp->intrlock); in vr_intr()
1300 * Reset the device if requested in vr_intr()
1301 * The request can come from the periodic tx check or from the interrupt in vr_intr()
1304 if (vrp->reset != 0) { in vr_intr()
1306 vrp->reset = 0; in vr_intr()
1313 mac_rx(vrp->machdl, 0, lp); in vr_intr()
1319 mac_link_update(vrp->machdl, in vr_intr()
1320 (link_state_t)vrp->chip.link.state); in vr_intr()
1322 * Restart transmissions if we were waiting for tx descriptors. in vr_intr()
1325 mac_tx_update(vrp->machdl); in vr_intr()
1329 * writes are delivered to the device before the interrupt is ended. in vr_intr()
1331 (void) VR_GET8(vrp->acc_reg, VR_ETHERADDR); in vr_intr()
1342 mutex_enter(&vrp->intrlock); in vr_error()
1343 mutex_enter(&vrp->oplock); in vr_error()
1344 mutex_enter(&vrp->tx.lock); in vr_error()
1348 mutex_exit(&vrp->tx.lock); in vr_error()
1349 mutex_exit(&vrp->oplock); in vr_error()
1350 mutex_exit(&vrp->intrlock); in vr_error()
1351 vrp->stats.resets++; in vr_error()
1369 for (rxp = vrp->rx.rp; ; rxp = rxp->next, n++) { in vr_receive()
1373 (void) ddi_dma_sync(vrp->rxring.handle, rxp->offset, in vr_receive()
1379 rxstat0 = ddi_get32(vrp->rxring.acchdl, &rxp->cdesc->stat0); in vr_receive()
1390 dmap = &rxp->dmabuf; in vr_receive()
1391 pklen = (rxstat0 >> 16) - ETHERFCSL; in vr_receive()
1396 (void) ddi_dma_sync(dmap->handle, 0, in vr_receive()
1404 bcopy(dmap->buf, np->b_rptr, pklen); in vr_receive()
1405 np->b_wptr = np->b_rptr + pklen; in vr_receive()
1407 vrp->stats.mac_stat_ipackets++; in vr_receive()
1408 vrp->stats.mac_stat_rbytes += pklen; in vr_receive()
1411 vrp->stats.mac_stat_brdcstrcv++; in vr_receive()
1413 vrp->stats.mac_stat_multircv++; in vr_receive()
1418 np->b_next = NULL; in vr_receive()
1422 mp->b_next = np; in vr_receive()
1426 vrp->stats.allocbfail++; in vr_receive()
1427 vrp->stats.mac_stat_norcvbuf++; in vr_receive()
1434 vrp->stats.mac_stat_ierrors++; in vr_receive()
1436 vrp->stats.ether_stat_align_errors++; in vr_receive()
1438 vrp->stats.ether_stat_fcs_errors++; in vr_receive()
1440 vrp->stats.ether_stat_toolong_errors++; in vr_receive()
1442 vrp->stats.ether_stat_tooshort_errors++; in vr_receive()
1444 vrp->stats.mac_stat_overflows++; in vr_receive()
1450 ddi_put32(vrp->rxring.acchdl, in vr_receive()
1451 &rxp->cdesc->stat0, in vr_receive()
1453 (void) ddi_dma_sync(vrp->rxring.handle, in vr_receive()
1454 rxp->offset, in vr_receive()
1458 vrp->rx.rp = rxp; in vr_receive()
1464 if (n > 0 && vrp->chip.link.flowctrl == VR_PAUSE_BIDIRECTIONAL) { in vr_receive()
1472 * Non-zero values written to this byte register are added in vr_receive()
1476 VR_PUT8(vrp->acc_reg, VR_FCR0_RXBUFCOUNT, MIN(n, 0xFF)); in vr_receive()
1492 mutex_enter(&vrp->tx.lock); in vr_mac_tx_enqueue_list()
1494 if (vrp->tx.nfree == 0) { in vr_mac_tx_enqueue_list()
1495 vrp->stats.ether_stat_defer_xmts++; in vr_mac_tx_enqueue_list()
1496 vrp->tx.resched = 1; in vr_mac_tx_enqueue_list()
1499 nextp = mp->b_next; in vr_mac_tx_enqueue_list()
1500 mp->b_next = mp->b_prev = NULL; in vr_mac_tx_enqueue_list()
1503 vrp->tx.nfree--; in vr_mac_tx_enqueue_list()
1505 mutex_exit(&vrp->tx.lock); in vr_mac_tx_enqueue_list()
1508 * Tell the chip to poll the TX ring. in vr_mac_tx_enqueue_list()
1510 VR_PUT8(vrp->acc_reg, VR_CTRL0, VR_CTRL0_DMA_GO); in vr_mac_tx_enqueue_list()
1526 if ((uchar_t)mp->b_rptr[0] == 0xff && in vr_tx_enqueue_msg()
1527 (uchar_t)mp->b_rptr[1] == 0xff && in vr_tx_enqueue_msg()
1528 (uchar_t)mp->b_rptr[2] == 0xff && in vr_tx_enqueue_msg()
1529 (uchar_t)mp->b_rptr[3] == 0xff && in vr_tx_enqueue_msg()
1530 (uchar_t)mp->b_rptr[4] == 0xff && in vr_tx_enqueue_msg()
1531 (uchar_t)mp->b_rptr[5] == 0xff) in vr_tx_enqueue_msg()
1532 vrp->stats.mac_stat_brdcstxmt++; in vr_tx_enqueue_msg()
1533 else if ((uchar_t)mp->b_rptr[0] == 1) in vr_tx_enqueue_msg()
1534 vrp->stats.mac_stat_multixmt++; in vr_tx_enqueue_msg()
1537 wp = vrp->tx.wp; in vr_tx_enqueue_msg()
1538 dmap = &wp->dmabuf; in vr_tx_enqueue_msg()
1541 * Copy the message into the pre-mapped buffer and free mp in vr_tx_enqueue_msg()
1543 mcopymsg(mp, dmap->buf); in vr_tx_enqueue_msg()
1548 padlen = ETHERMIN - pklen; in vr_tx_enqueue_msg()
1550 bzero(dmap->buf + pklen, padlen); in vr_tx_enqueue_msg()
1559 vrp->stats.mac_stat_obytes += pklen; in vr_tx_enqueue_msg()
1562 * Sync the data so the device sees the new content too. in vr_tx_enqueue_msg()
1564 (void) ddi_dma_sync(dmap->handle, 0, pklen, DDI_DMA_SYNC_FORDEV); in vr_tx_enqueue_msg()
1567 * If we have reached the TX interrupt distance, enable a TX interrupt in vr_tx_enqueue_msg()
1572 * MAC's bookkeeping for TX interrupts and fragmented packets. in vr_tx_enqueue_msg()
1574 vrp->tx.intr_distance++; in vr_tx_enqueue_msg()
1575 nextp = ddi_get32(vrp->txring.acchdl, &wp->cdesc->next); in vr_tx_enqueue_msg()
1576 if (vrp->tx.intr_distance >= VR_TX_MAX_INTR_DISTANCE) { in vr_tx_enqueue_msg()
1580 vrp->tx.intr_distance = 0; in vr_tx_enqueue_msg()
1592 ddi_put32(vrp->txring.acchdl, &wp->cdesc->stat1, in vr_tx_enqueue_msg()
1594 ddi_put32(vrp->txring.acchdl, &wp->cdesc->next, nextp); in vr_tx_enqueue_msg()
1595 ddi_put32(vrp->txring.acchdl, &wp->cdesc->stat0, VR_TDES0_OWN); in vr_tx_enqueue_msg()
1596 (void) ddi_dma_sync(vrp->txring.handle, wp->offset, in vr_tx_enqueue_msg()
1601 * descriptors and incremented by the periodic TX stall check. in vr_tx_enqueue_msg()
1603 vrp->tx.stallticks = 1; in vr_tx_enqueue_msg()
1604 vrp->tx.wp = wp->next; in vr_tx_enqueue_msg()
1616 ASSERT(mutex_owned(&vrp->tx.lock)); in vr_tx_reclaim()
1619 dirty = vrp->tx.ndesc - vrp->tx.nfree; in vr_tx_reclaim()
1620 for (cp = vrp->tx.cp; dirty > 0; cp = cp->next) { in vr_tx_reclaim()
1624 (void) ddi_dma_sync(vrp->txring.handle, cp->offset, in vr_tx_reclaim()
1627 stat0 = ddi_get32(vrp->txring.acchdl, &cp->cdesc->stat0); in vr_tx_reclaim()
1635 stat1 = ddi_get32(vrp->txring.acchdl, &cp->cdesc->stat1); in vr_tx_reclaim()
1638 vrp->stats.ether_stat_macxmt_errors++; in vr_tx_reclaim()
1640 vrp->stats.mac_stat_underflows++; in vr_tx_reclaim()
1642 vrp-> stats.ether_stat_ex_collisions++; in vr_tx_reclaim()
1649 VR_PUT8(vrp->acc_reg, VR_CTRL0, in vr_tx_reclaim()
1652 vrp->stats.mac_stat_opackets++; in vr_tx_reclaim()
1656 vrp->stats. in vr_tx_reclaim()
1659 vrp->stats. in vr_tx_reclaim()
1662 vrp->stats.mac_stat_collisions += in vr_tx_reclaim()
1667 vrp->stats.ether_stat_carrier_errors++; in vr_tx_reclaim()
1670 vrp->stats.ether_stat_tx_late_collisions++; in vr_tx_reclaim()
1673 dirty -= 1; in vr_tx_reclaim()
1675 vrp->tx.cp = cp; in vr_tx_reclaim()
1678 vrp->tx.nfree += freed; in vr_tx_reclaim()
1679 vrp->tx.stallticks = 0; in vr_tx_reclaim()
1680 vrp->stats.txreclaims += 1; in vr_tx_reclaim()
1682 vrp->stats.txreclaim0 += 1; in vr_tx_reclaim()
1686 * Check TX health every 2 seconds.
1694 if (vrp->chip.state == CHIPSTATE_RUNNING && in vr_periodic()
1695 vrp->chip.link.state == VR_LINK_STATE_UP && vrp->reset == 0) { in vr_periodic()
1696 if (mutex_tryenter(&vrp->intrlock) != 0) { in vr_periodic()
1697 mutex_enter(&vrp->tx.lock); in vr_periodic()
1698 if (vrp->tx.resched == 1) { in vr_periodic()
1699 if (vrp->tx.stallticks >= VR_MAXTXCHECKS) { in vr_periodic()
1704 vrp->reset = 1; in vr_periodic()
1706 "TX stalled, resetting MAC"); in vr_periodic()
1707 vrp->stats.txstalls++; in vr_periodic()
1713 vrp->tx.stallticks += 1; in vr_periodic()
1716 mutex_exit(&vrp->tx.lock); in vr_periodic()
1717 mutex_exit(&vrp->intrlock); in vr_periodic()
1718 vrp->stats.txchecks++; in vr_periodic()
1721 vrp->stats.cyclics++; in vr_periodic()
1725 * Bring the device to our desired initial state.
1739 VR_PUT8(vrp->acc_io, VR_CTRL1, VR_CTRL1_RESET); in vr_reset()
1744 VR_PUT8(vrp->acc_io, VR_MISC1, VR_MISC1_RESET); in vr_reset()
1747 } while ((VR_GET8(vrp->acc_io, VR_CTRL1) & VR_CTRL1_RESET) != 0); in vr_reset()
1753 VR_SETBIT8(vrp->acc_io, VR_PROMCTL, VR_PROMCTL_RELOAD); in vr_reset()
1760 VR_SETBIT8(vrp->acc_io, VR_CFGD, VR_CFGD_MMIOEN); in vr_reset()
1771 ASSERT(mutex_owned(&vrp->oplock)); in vr_start()
1782 * Allocate DMA buffers for TX. in vr_start()
1794 pci_mode = VR_GET8(vrp->acc_reg, VR_MODE2); in vr_start()
1795 if ((vrp->chip.info.bugs & VR_BUG_NEEDMODE10T) != 0) in vr_start()
1798 if ((vrp->chip.info.bugs & VR_BUG_NEEDMODE2PCEROPT) != 0) in vr_start()
1801 if ((vrp->chip.info.features & VR_FEATURE_MRDLNMULTIPLE) != 0) in vr_start()
1803 VR_PUT8(vrp->acc_reg, VR_MODE2, pci_mode); in vr_start()
1805 pci_mode = VR_GET8(vrp->acc_reg, VR_MODE3); in vr_start()
1806 if ((vrp->chip.info.bugs & VR_BUG_NEEDMIION) != 0) in vr_start()
1808 VR_PUT8(vrp->acc_reg, VR_MODE3, pci_mode); in vr_start()
1813 VR_SETBIT8(vrp->acc_reg, VR_RXCFG, VR_RXCFG_ACCEPTBROAD); in vr_start()
1818 VR_SETBITS8(vrp->acc_reg, VR_RXCFG, VR_RXCFG_FIFO_THRESHOLD_BITS, in vr_start()
1820 VR_SETBITS8(vrp->acc_reg, VR_BCR0, VR_BCR0_RX_FIFO_THRESHOLD_BITS, in vr_start()
1824 * TX: Start transmit when there are 256 bytes in the FIFO. in vr_start()
1826 VR_SETBITS8(vrp->acc_reg, VR_TXCFG, VR_TXCFG_FIFO_THRESHOLD_BITS, in vr_start()
1828 VR_SETBITS8(vrp->acc_reg, VR_BCR1, VR_BCR1_TX_FIFO_THRESHOLD_BITS, in vr_start()
1834 VR_SETBITS8(vrp->acc_reg, VR_BCR0, VR_BCR0_DMABITS, VR_BCR0_DMA256); in vr_start()
1837 * Disable TX autopolling as it is bad for RX performance in vr_start()
1841 VR_SETBIT8(vrp->acc_reg, VR_CTRL1, VR_CTRL1_NOAUTOPOLL); in vr_start()
1846 pci_latency = VR_GET8(vrp->acc_cfg, PCI_CONF_LATENCY_TIMER); in vr_start()
1848 VR_SETBIT8(vrp->acc_reg, VR_CFGB, VR_CFGB_LATENCYTIMER); in vr_start()
1850 VR_CLRBIT8(vrp->acc_reg, VR_CFGB, VR_CFGB_LATENCYTIMER); in vr_start()
1855 if ((vrp->chip.info.features & VR_FEATURE_VLANTAGGING) != 0) { in vr_start()
1856 VR_CLRBIT8(vrp->acc_reg, VR_BCR1, VR_BCR1_VLANFILTER); in vr_start()
1857 VR_CLRBIT8(vrp->acc_reg, VR_TXCFG, VR_TXCFG_8021PQ_EN); in vr_start()
1863 if ((vrp->chip.info.features & VR_FEATURE_CAMSUPPORT) != 0) { in vr_start()
1864 VR_PUT8(vrp->acc_reg, VR_CAM_CTRL, VR_CAM_CTRL_ENABLE); in vr_start()
1865 VR_PUT32(vrp->acc_reg, VR_CAM_MASK, 0); in vr_start()
1866 VR_PUT8(vrp->acc_reg, VR_CAM_CTRL, VR_CAM_CTRL_DONE); in vr_start()
1868 VR_PUT8(vrp->acc_reg, VR_CAM_CTRL, in vr_start()
1870 VR_PUT8(vrp->acc_reg, VR_VCAM0, 0); in vr_start()
1871 VR_PUT8(vrp->acc_reg, VR_VCAM1, 0); in vr_start()
1872 VR_PUT8(vrp->acc_reg, VR_CAM_CTRL, VR_CAM_CTRL_WRITE); in vr_start()
1873 VR_PUT32(vrp->acc_reg, VR_CAM_MASK, 1); in vr_start()
1875 VR_PUT8(vrp->acc_reg, VR_CAM_CTRL, VR_CAM_CTRL_DONE); in vr_start()
1882 VR_PUT32(vrp->acc_reg, VR_RXADDR, vrp->rx.rp->paddr); in vr_start()
1883 VR_PUT32(vrp->acc_reg, VR_TXADDR, vrp->tx.wp->paddr); in vr_start()
1889 VR_PUT8(vrp->acc_reg, VR_ISR1, 0xFF); in vr_start()
1890 VR_PUT8(vrp->acc_reg, VR_ICR1, 0); in vr_start()
1895 VR_PUT16(vrp->acc_reg, VR_ISR0, 0xFFFF); in vr_start()
1896 VR_PUT16(vrp->acc_reg, VR_ICR0, VR_ICR0_CFG); in vr_start()
1901 VR_PUT8(vrp->acc_reg, VR_CTRL0, VR_CTRL0_DMA_GO); in vr_start()
1912 vrp->chip.state = CHIPSTATE_RUNNING; in vr_start()
1922 ASSERT(mutex_owned(&vrp->oplock)); in vr_stop()
1927 VR_PUT16(vrp->acc_reg, VR_ICR0, 0); in vr_stop()
1928 VR_PUT8(vrp->acc_reg, VR_ICR1, 0); in vr_stop()
1933 VR_PUT8(vrp->acc_reg, VR_CTRL0, VR_CTRL0_DMA_STOP); in vr_stop()
1938 vrp->chip.state = CHIPSTATE_STOPPED; in vr_stop()
1955 mutex_enter(&vrp->oplock); in vr_mac_start()
1970 vrp->periodic_id = in vr_mac_start()
1973 mutex_exit(&vrp->oplock); in vr_mac_start()
1982 mutex_enter(&vrp->oplock); in vr_mac_stop()
1983 mutex_enter(&vrp->tx.lock); in vr_mac_stop()
1986 * Stop the device. in vr_mac_stop()
1989 mutex_exit(&vrp->tx.lock); in vr_mac_stop()
1994 ddi_periodic_delete(vrp->periodic_id); in vr_mac_stop()
1995 mutex_exit(&vrp->oplock); in vr_mac_stop()
2003 * 48-bit Ethernet address. Incoming frames with multicast destination
2042 mutex_enter(&vrp->oplock); in vr_mac_set_multicast()
2043 mutex_enter(&vrp->intrlock); in vr_mac_set_multicast()
2046 if ((vrp->chip.info.features & VR_FEATURE_CAMSUPPORT) != 0) { in vr_mac_set_multicast()
2050 cam_mask = VR_GET32(vrp->acc_reg, VR_CAM_MASK); in vr_mac_set_multicast()
2057 if (cam_index != -1) { in vr_mac_set_multicast()
2062 VR_PUT8(vrp->acc_reg, VR_CAM_CTRL, in vr_mac_set_multicast()
2064 VR_PUT8(vrp->acc_reg, VR_CAM_ADDR, cam_index); in vr_mac_set_multicast()
2065 VR_PUT32(vrp->acc_reg, VR_CAM_MASK, cam_mask); in vr_mac_set_multicast()
2067 VR_PUT8(vrp->acc_reg, in vr_mac_set_multicast()
2070 VR_PUT8(vrp->acc_reg, VR_CAM_CTRL, in vr_mac_set_multicast()
2073 VR_PUT8(vrp->acc_reg, VR_CAM_CTRL, in vr_mac_set_multicast()
2085 * If the entry was not found (-1), the addition was in vr_mac_set_multicast()
2089 if (cam_index != -1) { in vr_mac_set_multicast()
2094 VR_PUT8(vrp->acc_reg, VR_CAM_CTRL, in vr_mac_set_multicast()
2096 VR_PUT32(vrp->acc_reg, VR_CAM_MASK, cam_mask); in vr_mac_set_multicast()
2097 VR_PUT8(vrp->acc_reg, VR_CAM_CTRL, in vr_mac_set_multicast()
2119 * Get the CRC-32 of the multicast address in vr_mac_set_multicast()
2124 crc_index = ether_crc_be(mca) >> (32 - 6); in vr_mac_set_multicast()
2130 vrp->mhash0 |= (1 << crc_index); in vr_mac_set_multicast()
2132 vrp->mhash1 |= (1 << (crc_index - 32)); in vr_mac_set_multicast()
2138 vrp->mhash0 &= ~(0 << crc_index); in vr_mac_set_multicast()
2140 vrp->mhash1 &= ~(0 << (crc_index - 32)); in vr_mac_set_multicast()
2147 if (vrp->promisc == B_FALSE) { in vr_mac_set_multicast()
2148 VR_PUT32(vrp->acc_reg, VR_MAR0, vrp->mhash0); in vr_mac_set_multicast()
2149 VR_PUT32(vrp->acc_reg, VR_MAR1, vrp->mhash1); in vr_mac_set_multicast()
2157 vrp->mcount++; in vr_mac_set_multicast()
2158 else if (vrp->mcount != 0) in vr_mac_set_multicast()
2159 vrp->mcount --; in vr_mac_set_multicast()
2160 if (vrp->mcount != 0) in vr_mac_set_multicast()
2161 VR_SETBIT8(vrp->acc_reg, VR_RXCFG, VR_RXCFG_ACCEPTMULTI); in vr_mac_set_multicast()
2163 VR_CLRBIT8(vrp->acc_reg, VR_RXCFG, VR_RXCFG_ACCEPTMULTI); in vr_mac_set_multicast()
2165 mutex_exit(&vrp->intrlock); in vr_mac_set_multicast()
2166 mutex_exit(&vrp->oplock); in vr_mac_set_multicast()
2198 * Return the CAM index (base 0) of maddr or -1 if maddr is not found
2199 * If maddr is 0, return the index of an empty slot in CAM or -1 when no free
2215 mask = VR_GET32(vrp->acc_reg, VR_CAM_MASK); in vr_cam_index()
2218 * If maddr is 0, return the first unused slot or -1 for no unused. in vr_cam_index()
2228 return (-1); in vr_cam_index()
2238 VR_PUT8(vrp->acc_reg, VR_CAM_CTRL, VR_CAM_CTRL_ENABLE); in vr_cam_index()
2239 VR_PUT8(vrp->acc_reg, VR_CAM_ADDR, index); in vr_cam_index()
2240 VR_PUT8(vrp->acc_reg, VR_CAM_CTRL, VR_CAM_CTRL_READ); in vr_cam_index()
2243 taddr[a] = VR_GET8(vrp->acc_reg, VR_MCAM0 + a); in vr_cam_index()
2244 VR_PUT8(vrp->acc_reg, VR_CAM_CTRL, VR_CAM_CTRL_DONE); in vr_cam_index()
2249 return (-1); in vr_cam_index()
2263 mutex_enter(&vrp->intrlock); in vr_mac_set_promisc()
2264 mutex_enter(&vrp->oplock); in vr_mac_set_promisc()
2265 mutex_enter(&vrp->tx.lock); in vr_mac_set_promisc()
2270 rxcfg = VR_GET8(vrp->acc_reg, VR_RXCFG); in vr_mac_set_promisc()
2271 vrp->promisc = promiscflag; in vr_mac_set_promisc()
2278 VR_PUT32(vrp->acc_reg, VR_MAR0, 0xffffffff); in vr_mac_set_promisc()
2279 VR_PUT32(vrp->acc_reg, VR_MAR1, 0xffffffff); in vr_mac_set_promisc()
2284 VR_PUT32(vrp->acc_reg, VR_MAR0, vrp->mhash0); in vr_mac_set_promisc()
2285 VR_PUT32(vrp->acc_reg, VR_MAR1, vrp->mhash1); in vr_mac_set_promisc()
2287 if (vrp->mcount != 0) in vr_mac_set_promisc()
2290 VR_PUT8(vrp->acc_reg, VR_RXCFG, rxcfg); in vr_mac_set_promisc()
2291 mutex_exit(&vrp->tx.lock); in vr_mac_set_promisc()
2292 mutex_exit(&vrp->oplock); in vr_mac_set_promisc()
2293 mutex_exit(&vrp->intrlock); in vr_mac_set_promisc()
2310 v = (vrp->chip.mii.anadv & MII_ABILITY_100BASE_T4) != 0; in vr_mac_getstat()
2314 v = (vrp->chip.mii.anadv & MII_ABILITY_100BASE_TX_FD) != 0; in vr_mac_getstat()
2318 v = (vrp->chip.mii.anadv & MII_ABILITY_100BASE_TX) != 0; in vr_mac_getstat()
2322 v = (vrp->chip.mii.anadv & MII_ABILITY_10BASE_T_FD) != 0; in vr_mac_getstat()
2326 v = (vrp->chip.mii.anadv & MII_ABILITY_10BASE_T) != 0; in vr_mac_getstat()
2334 v = (vrp->chip.mii.control & MII_CONTROL_ANE) != 0; in vr_mac_getstat()
2338 v = (vrp->chip.mii.anadv & MII_ABILITY_PAUSE) != 0; in vr_mac_getstat()
2342 v = (vrp->chip.mii.anadv & MII_AN_ADVERT_REMFAULT) != 0; in vr_mac_getstat()
2346 v = vrp->stats.ether_stat_align_errors; in vr_mac_getstat()
2350 v = (vrp->chip.mii.status & MII_STATUS_100_BASE_T4) != 0; in vr_mac_getstat()
2354 v = (vrp->chip.mii.status & MII_STATUS_100_BASEX_FD) != 0; in vr_mac_getstat()
2358 v = (vrp->chip.mii.status & MII_STATUS_100_BASEX) != 0; in vr_mac_getstat()
2362 v = (vrp->chip.mii.status & MII_STATUS_10_FD) != 0; in vr_mac_getstat()
2366 v = (vrp->chip.mii.status & MII_STATUS_10) != 0; in vr_mac_getstat()
2374 v = (vrp->chip.mii.status & MII_STATUS_CANAUTONEG) != 0; in vr_mac_getstat()
2382 v = (vrp->chip.mii.status & MII_STATUS_REMFAULT) != 0; in vr_mac_getstat()
2390 v = vrp->stats.ether_stat_carrier_errors; in vr_mac_getstat()
2401 v = vrp->stats.ether_stat_defer_xmts; in vr_mac_getstat()
2409 v = vrp->stats.ether_stat_ex_collisions; in vr_mac_getstat()
2416 v = vrp->stats.ether_stat_fcs_errors; in vr_mac_getstat()
2423 v = vrp->stats.ether_stat_first_collisions; in vr_mac_getstat()
2431 v = (vrp->chip.mii.control & MII_CONTROL_ANE) != 0 && in vr_mac_getstat()
2432 (vrp->chip.mii.status & MII_STATUS_ANDONE) != 0; in vr_mac_getstat()
2436 v = vrp->chip.link.duplex; in vr_mac_getstat()
2440 v = vrp->chip.link.flowctrl; in vr_mac_getstat()
2444 v = (vrp->chip.mii.lpable & MII_ABILITY_100BASE_T4) != 0; in vr_mac_getstat()
2456 v = (vrp->chip.mii.lpable & MII_ABILITY_100BASE_TX_FD) != 0; in vr_mac_getstat()
2460 v = (vrp->chip.mii.lpable & MII_ABILITY_100BASE_TX) != 0; in vr_mac_getstat()
2464 v = (vrp->chip.mii.lpable & MII_ABILITY_10BASE_T_FD) != 0; in vr_mac_getstat()
2468 v = (vrp->chip.mii.lpable & MII_ABILITY_10BASE_T) != 0; in vr_mac_getstat()
2476 v = (vrp->chip.mii.anexp & MII_AN_EXP_LPCANAN) != 0; in vr_mac_getstat()
2480 v = (vrp->chip.mii.lpable & MII_ABILITY_PAUSE) != 0; in vr_mac_getstat()
2484 v = (vrp->chip.mii.status & MII_STATUS_REMFAULT) != 0; in vr_mac_getstat()
2492 v = vrp->stats.ether_stat_macrcv_errors; in vr_mac_getstat()
2500 v = vrp->stats.ether_stat_macxmt_errors; in vr_mac_getstat()
2507 v = vrp->stats.ether_stat_multi_collisions; in vr_mac_getstat()
2521 v = vrp->stats.ether_stat_toolong_errors; in vr_mac_getstat()
2525 v = vrp->stats.ether_stat_tooshort_errors; in vr_mac_getstat()
2533 v = vrp->stats.ether_stat_tx_late_collisions; in vr_mac_getstat()
2539 * device in use for a given Ethernet device. in vr_mac_getstat()
2541 v = vrp->chip.phyaddr; in vr_mac_getstat()
2546 * MII transceiver manufacturer and device ID. in vr_mac_getstat()
2548 v = (vrp->chip.mii.identh << 16) | vrp->chip.mii.identl; in vr_mac_getstat()
2552 v = vrp->chip.link.mau; in vr_mac_getstat()
2556 v = vrp->stats.mac_stat_brdcstrcv; in vr_mac_getstat()
2560 v = vrp->stats.mac_stat_brdcstxmt; in vr_mac_getstat()
2564 v = vrp->stats.mac_stat_multixmt; in vr_mac_getstat()
2568 v = vrp->stats.mac_stat_collisions; in vr_mac_getstat()
2572 v = vrp->stats.mac_stat_ierrors; in vr_mac_getstat()
2576 if (vrp->chip.link.speed == VR_LINK_SPEED_100MBS) in vr_mac_getstat()
2578 else if (vrp->chip.link.speed == VR_LINK_SPEED_10MBS) in vr_mac_getstat()
2585 v = vrp->stats.mac_stat_ipackets; in vr_mac_getstat()
2589 v = vrp->stats.mac_stat_multircv; in vr_mac_getstat()
2593 vrp->stats.mac_stat_norcvbuf += in vr_mac_getstat()
2594 VR_GET16(vrp->acc_reg, VR_TALLY_MPA); in vr_mac_getstat()
2595 VR_PUT16(vrp->acc_reg, VR_TALLY_MPA, 0); in vr_mac_getstat()
2596 v = vrp->stats.mac_stat_norcvbuf; in vr_mac_getstat()
2600 v = vrp->stats.mac_stat_noxmtbuf; in vr_mac_getstat()
2604 v = vrp->stats.mac_stat_obytes; in vr_mac_getstat()
2608 v = vrp->stats.ether_stat_macxmt_errors + in vr_mac_getstat()
2609 vrp->stats.mac_stat_underflows + in vr_mac_getstat()
2610 vrp->stats.ether_stat_align_errors + in vr_mac_getstat()
2611 vrp->stats.ether_stat_carrier_errors + in vr_mac_getstat()
2612 vrp->stats.ether_stat_fcs_errors; in vr_mac_getstat()
2616 v = vrp->stats.mac_stat_opackets; in vr_mac_getstat()
2620 v = vrp->stats.mac_stat_rbytes; in vr_mac_getstat()
2630 v = vrp->stats.mac_stat_underflows; in vr_mac_getstat()
2634 v = vrp->stats.mac_stat_overflows; in vr_mac_getstat()
2648 mutex_enter(&vrp->oplock); in vr_mac_set_ether_addr()
2649 mutex_enter(&vrp->intrlock); in vr_mac_set_ether_addr()
2655 VR_PUT8(vrp->acc_reg, VR_ETHERADDR + i, ea[i]); in vr_mac_set_ether_addr()
2657 mutex_exit(&vrp->intrlock); in vr_mac_set_ether_addr()
2658 mutex_exit(&vrp->oplock); in vr_mac_set_ether_addr()
2668 ASSERT(mutex_owned(&vrp->oplock)); in vr_link_init()
2669 if ((vrp->chip.mii.control & MII_CONTROL_ANE) != 0) { in vr_link_init()
2673 vrp->chip.mii.control |= MII_CONTROL_RSAN; in vr_link_init()
2678 vr_phy_write(vrp, MII_AN_ADVERT, vrp->chip.mii.anadv); in vr_link_init()
2687 if ((vrp->param.anadv_en & in vr_link_init()
2689 vrp->chip.mii.control |= MII_CONTROL_100MB; in vr_link_init()
2690 vrp->chip.mii.control |= MII_CONTROL_FDUPLEX; in vr_link_init()
2691 } else if ((vrp->param.anadv_en & in vr_link_init()
2693 vrp->chip.mii.control |= MII_CONTROL_100MB; in vr_link_init()
2694 vrp->chip.mii.control &= ~MII_CONTROL_FDUPLEX; in vr_link_init()
2695 } else if ((vrp->param.anadv_en & in vr_link_init()
2697 vrp->chip.mii.control |= MII_CONTROL_FDUPLEX; in vr_link_init()
2698 vrp->chip.mii.control &= ~MII_CONTROL_100MB; in vr_link_init()
2700 vrp->chip.mii.control &= ~MII_CONTROL_100MB; in vr_link_init()
2701 vrp->chip.mii.control &= ~MII_CONTROL_FDUPLEX; in vr_link_init()
2707 vr_phy_write(vrp, MII_CONTROL, vrp->chip.mii.control); in vr_link_init()
2713 if ((vrp->chip.mii.control & MII_CONTROL_ANE) == 0) { in vr_link_init()
2715 mac_link_update(vrp->machdl, in vr_link_init()
2716 (link_state_t)vrp->chip.link.state); in vr_link_init()
2728 ASSERT(mutex_owned(&vrp->oplock)); in vr_link_state()
2730 vr_phy_read(vrp, MII_STATUS, &vrp->chip.mii.status); in vr_link_state()
2731 vr_phy_read(vrp, MII_CONTROL, &vrp->chip.mii.control); in vr_link_state()
2732 vr_phy_read(vrp, MII_AN_ADVERT, &vrp->chip.mii.anadv); in vr_link_state()
2733 vr_phy_read(vrp, MII_AN_LPABLE, &vrp->chip.mii.lpable); in vr_link_state()
2734 vr_phy_read(vrp, MII_AN_EXPANSION, &vrp->chip.mii.anexp); in vr_link_state()
2740 if ((vrp->chip.mii.control & MII_CONTROL_ANE) != 0) { in vr_link_state()
2741 mask = vrp->chip.mii.anadv & vrp->chip.mii.lpable; in vr_link_state()
2743 vrp->chip.link.speed = VR_LINK_SPEED_100MBS; in vr_link_state()
2744 vrp->chip.link.duplex = VR_LINK_DUPLEX_FULL; in vr_link_state()
2745 vrp->chip.link.mau = VR_MAU_100X; in vr_link_state()
2747 vrp->chip.link.speed = VR_LINK_SPEED_100MBS; in vr_link_state()
2748 vrp->chip.link.duplex = VR_LINK_DUPLEX_HALF; in vr_link_state()
2749 vrp->chip.link.mau = VR_MAU_100T4; in vr_link_state()
2751 vrp->chip.link.speed = VR_LINK_SPEED_100MBS; in vr_link_state()
2752 vrp->chip.link.duplex = VR_LINK_DUPLEX_HALF; in vr_link_state()
2753 vrp->chip.link.mau = VR_MAU_100X; in vr_link_state()
2755 vrp->chip.link.speed = VR_LINK_SPEED_10MBS; in vr_link_state()
2756 vrp->chip.link.duplex = VR_LINK_DUPLEX_FULL; in vr_link_state()
2757 vrp->chip.link.mau = VR_MAU_10; in vr_link_state()
2759 vrp->chip.link.speed = VR_LINK_SPEED_10MBS; in vr_link_state()
2760 vrp->chip.link.duplex = VR_LINK_DUPLEX_HALF; in vr_link_state()
2761 vrp->chip.link.mau = VR_MAU_10; in vr_link_state()
2763 vrp->chip.link.speed = VR_LINK_SPEED_UNKNOWN; in vr_link_state()
2764 vrp->chip.link.duplex = VR_LINK_DUPLEX_UNKNOWN; in vr_link_state()
2765 vrp->chip.link.mau = VR_MAU_UNKNOWN; in vr_link_state()
2772 vrp->chip.link.duplex == VR_LINK_DUPLEX_FULL) in vr_link_state()
2773 vrp->chip.link.flowctrl = VR_PAUSE_BIDIRECTIONAL; in vr_link_state()
2775 vrp->chip.link.flowctrl = VR_PAUSE_NONE; in vr_link_state()
2780 if ((vrp->chip.mii.status & MII_STATUS_REMFAULT) != 0) in vr_link_state()
2784 if ((vrp->chip.mii.lpable & MII_AN_ADVERT_REMFAULT) != 0) in vr_link_state()
2791 if ((vrp->chip.mii.control & MII_CONTROL_100MB) != 0) { in vr_link_state()
2792 vrp->chip.link.speed = VR_LINK_SPEED_100MBS; in vr_link_state()
2793 vrp->chip.link.mau = VR_MAU_100X; in vr_link_state()
2795 vrp->chip.link.speed = VR_LINK_SPEED_10MBS; in vr_link_state()
2796 vrp->chip.link.mau = VR_MAU_10; in vr_link_state()
2799 if ((vrp->chip.mii.control & MII_CONTROL_FDUPLEX) != 0) in vr_link_state()
2800 vrp->chip.link.duplex = VR_LINK_DUPLEX_FULL; in vr_link_state()
2802 vrp->chip.link.duplex = VR_LINK_DUPLEX_HALF; in vr_link_state()
2806 vrp->chip.link.flowctrl = VR_PAUSE_NONE; in vr_link_state()
2813 if (vrp->chip.link.duplex == VR_LINK_DUPLEX_FULL) { in vr_link_state()
2814 VR_SETBIT8(vrp->acc_reg, VR_CTRL1, VR_CTRL1_MACFULLDUPLEX); in vr_link_state()
2818 if ((vrp->chip.info.bugs & VR_BUG_NO_TXQUEUEING) == 0) in vr_link_state()
2819 VR_CLRBIT8(vrp->acc_reg, VR_CFGB, VR_CFGB_QPKTDIS); in vr_link_state()
2821 VR_CLRBIT8(vrp->acc_reg, VR_CTRL1, VR_CTRL1_MACFULLDUPLEX); in vr_link_state()
2824 * this MAC get's lost after a TX abort (too many colisions). in vr_link_state()
2826 VR_SETBIT8(vrp->acc_reg, VR_CFGB, VR_CFGB_QPKTDIS); in vr_link_state()
2832 if (vrp->chip.link.flowctrl == VR_PAUSE_BIDIRECTIONAL) { in vr_link_state()
2836 VR_SETBIT8(vrp->acc_reg, VR_MISC0, VR_MISC0_FDXRFEN); in vr_link_state()
2841 if ((vrp->chip.info.features & VR_FEATURE_TX_PAUSE_CAP) != 0) { in vr_link_state()
2844 * Non-zero values written to this register are added in vr_link_state()
2849 VR_PUT8(vrp->acc_reg, VR_FCR0_RXBUFCOUNT, in vr_link_state()
2850 MIN(vrp->rx.ndesc, 0xFF) - in vr_link_state()
2851 VR_GET8(vrp->acc_reg, in vr_link_state()
2857 VR_SETBITS8(vrp->acc_reg, VR_FCR1, in vr_link_state()
2863 VR_SETBITS8(vrp->acc_reg, VR_FCR1, in vr_link_state()
2867 * Request a pause of FFFF bit-times. This long pause in vr_link_state()
2870 VR_PUT16(vrp->acc_reg, VR_FCR2_PAUSE, 0xFFFF); in vr_link_state()
2875 VR_SETBIT8(vrp->acc_reg, VR_MISC0, VR_MISC0_FDXTFEN); in vr_link_state()
2876 VR_SETBIT8(vrp->acc_reg, VR_FCR1, VR_FCR1_FD_RX_EN | in vr_link_state()
2883 VR_CLRBIT8(vrp->acc_reg, in vr_link_state()
2885 if ((vrp->chip.info.features & VR_FEATURE_TX_PAUSE_CAP) != 0) { in vr_link_state()
2886 VR_CLRBIT8(vrp->acc_reg, VR_FCR1, in vr_link_state()
2895 if ((vrp->chip.mii.status & MII_STATUS_LINKUP) != 0) in vr_link_state()
2896 vrp->chip.link.state = VR_LINK_STATE_UP; in vr_link_state()
2898 vrp->chip.link.state = VR_LINK_STATE_DOWN; in vr_link_state()
2920 if ((vrp->chip.info.bugs & VR_BUG_MIIPOLLSTOP) != 0) { in vr_phy_autopoll_disable()
2924 miicmd = VR_GET8(vrp->acc_reg, VR_MIICMD); in vr_phy_autopoll_disable()
2939 miiaddr = VR_GET8(vrp->acc_reg, VR_MIIADDR); in vr_phy_autopoll_disable()
2945 VR_PUT8(vrp->acc_reg, VR_MIICMD, 0); in vr_phy_autopoll_disable()
2950 VR_PUT8(vrp->acc_reg, VR_MIICMD, 0); in vr_phy_autopoll_disable()
2964 miiaddr = VR_GET8(vrp->acc_reg, VR_MIIADDR); in vr_phy_autopoll_disable()
2977 VR_PUT8(vrp->acc_reg, VR_MIICMD, 0); in vr_phy_autopoll_enable()
2978 VR_PUT8(vrp->acc_reg, VR_MIIADDR, MII_STATUS|VR_MIIADDR_MAUTO); in vr_phy_autopoll_enable()
2979 VR_PUT8(vrp->acc_reg, VR_MIICMD, VR_MIICMD_MD_AUTO); in vr_phy_autopoll_enable()
2992 } while ((VR_GET8(vrp->acc_reg, VR_MIIADDR) & VR_MIIADDR_MDONE) == 0); in vr_phy_autopoll_enable()
2997 VR_SETBIT8(vrp->acc_reg, VR_MIIADDR, VR_MIIADDR_MAUTO); in vr_phy_autopoll_enable()
3014 VR_SETBITS8(vrp->acc_reg, VR_MIIADDR, VR_MIIADDR_BITS, offset); in vr_phy_read()
3020 VR_SETBIT8(vrp->acc_reg, VR_MIICMD, VR_MIICMD_MD_READ); in vr_phy_read()
3033 } while ((VR_GET8(vrp->acc_reg, VR_MIICMD) & VR_MIICMD_MD_READ) != 0); in vr_phy_read()
3035 *value = VR_GET16(vrp->acc_reg, VR_MIIDATA); in vr_phy_read()
3052 VR_SETBITS8(vrp->acc_reg, VR_MIIADDR, VR_MIIADDR_BITS, offset); in vr_phy_write()
3057 VR_PUT16(vrp->acc_reg, VR_MIIDATA, value); in vr_phy_write()
3063 VR_SETBIT8(vrp->acc_reg, VR_MIICMD, VR_MIICMD_MD_WRITE); in vr_phy_write()
3073 } while ((VR_GET8(vrp->acc_reg, VR_MIICMD) & VR_MIICMD_MD_WRITE) != 0); in vr_phy_write()
3109 ksp = kstat_create(MODULENAME, ddi_get_instance(vrp->devinfo), in vr_kstats_init()
3115 ksp->ks_update = vr_update_kstats; in vr_kstats_init()
3116 ksp->ks_private = (void*) vrp; in vr_kstats_init()
3117 knp = ksp->ks_data; in vr_kstats_init()
3124 vrp->ksp = ksp; in vr_kstats_init()
3133 vrp = (vr_t *)ksp->ks_private; in vr_update_kstats()
3134 knp = ksp->ks_data; in vr_update_kstats()
3139 (knp++)->value.ui32 = vrp->stats.allocbfail; in vr_update_kstats()
3140 (knp++)->value.ui64 = vrp->stats.intr_claimed; in vr_update_kstats()
3141 (knp++)->value.ui64 = vrp->stats.intr_unclaimed; in vr_update_kstats()
3142 (knp++)->value.ui64 = vrp->stats.linkchanges; in vr_update_kstats()
3143 (knp++)->value.ui32 = vrp->tx.nfree; in vr_update_kstats()
3144 (knp++)->value.ui32 = vrp->stats.txstalls; in vr_update_kstats()
3145 (knp++)->value.ui32 = vrp->stats.resets; in vr_update_kstats()
3146 (knp++)->value.ui64 = vrp->stats.txreclaims; in vr_update_kstats()
3147 (knp++)->value.ui64 = vrp->stats.txreclaim0; in vr_update_kstats()
3148 (knp++)->value.ui64 = vrp->stats.cyclics; in vr_update_kstats()
3149 (knp++)->value.ui64 = vrp->stats.txchecks; in vr_update_kstats()
3159 if (vrp->ksp != NULL) in vr_remove_kstats()
3160 kstat_delete(vrp->ksp); in vr_remove_kstats()
3164 * Get a property of the device/driver
3166 * - pr_val is always an integer of size pr_valsize
3167 * - ENABLED (EN) is what is configured via dladm
3168 * - ADVERTISED (ADV) is ENABLED minus constraints, like PHY/MAC capabilities
3169 * - DEFAULT are driver- and hardware defaults (DEFAULT is implemented as a
3171 * - perm is the permission printed on ndd -get /.. \?
3195 val = (vrp->chip.mii.anadv & in vr_mac_getprop()
3200 val = (vrp->chip.mii.anadv & in vr_mac_getprop()
3205 val = (vrp->chip.mii.anadv & in vr_mac_getprop()
3210 val = (vrp->chip.mii.anadv & in vr_mac_getprop()
3215 val = (vrp->chip.mii.anadv & in vr_mac_getprop()
3220 val = (vrp->chip.mii.control & in vr_mac_getprop()
3225 val = vrp->chip.link.duplex; in vr_mac_getprop()
3229 val = (vrp->param.anadv_en & in vr_mac_getprop()
3234 val = (vrp->param.anadv_en & in vr_mac_getprop()
3239 val = (vrp->param.anadv_en & in vr_mac_getprop()
3244 val = (vrp->param.anadv_en & in vr_mac_getprop()
3249 val = (vrp->param.anadv_en & in vr_mac_getprop()
3254 val = vrp->param.an_en == VR_LINK_AUTONEG_ON; in vr_mac_getprop()
3258 val = vrp->chip.link.flowctrl; in vr_mac_getprop()
3262 val = vrp->param.mtu; in vr_mac_getprop()
3266 if (vrp->chip.link.speed == in vr_mac_getprop()
3269 else if (vrp->chip.link.speed == in vr_mac_getprop()
3277 val = vrp->chip.link.state; in vr_mac_getprop()
3324 val = (vrp->chip.mii.status & in vr_mac_propinfo()
3329 val = (vrp->chip.mii.status & in vr_mac_propinfo()
3334 val = (vrp->chip.mii.status & in vr_mac_propinfo()
3339 val = (vrp->chip.mii.status & in vr_mac_propinfo()
3344 val = (vrp->chip.mii.status & in vr_mac_propinfo()
3350 val = (vrp->chip.mii.status & in vr_mac_propinfo()
3368 perm = ((vrp->chip.mii.control & in vr_mac_propinfo()
3380 perm = ((vrp->chip.mii.control & in vr_mac_propinfo()
3403 * Set a property of the device.
3418 mutex_enter(&vrp->oplock); in vr_mac_setprop()
3434 mutex_exit(&vrp->oplock); in vr_mac_setprop()
3441 if ((vrp->chip.mii.control & MII_CONTROL_ANE) == 0) { in vr_mac_setprop()
3443 vrp->chip.mii.control |= in vr_mac_setprop()
3446 vrp->chip.mii.control &= in vr_mac_setprop()
3456 vrp->param.anadv_en &= in vr_mac_setprop()
3459 vrp->param.anadv_en |= in vr_mac_setprop()
3465 vrp->param.anadv_en &= in vr_mac_setprop()
3468 vrp->param.anadv_en |= in vr_mac_setprop()
3474 vrp->param.anadv_en &= in vr_mac_setprop()
3477 vrp->param.anadv_en |= in vr_mac_setprop()
3483 vrp->param.anadv_en &= in vr_mac_setprop()
3486 vrp->param.anadv_en |= in vr_mac_setprop()
3492 vrp->param.anadv_en &= in vr_mac_setprop()
3495 vrp->param.anadv_en |= in vr_mac_setprop()
3502 vrp->param.an_en = VR_LINK_AUTONEG_OFF; in vr_mac_setprop()
3503 vrp->chip.mii.control &= ~MII_CONTROL_ANE; in vr_mac_setprop()
3505 vrp->param.an_en = VR_LINK_AUTONEG_ON; in vr_mac_setprop()
3506 if ((vrp->chip.mii.status & in vr_mac_setprop()
3508 vrp->chip.mii.control |= in vr_mac_setprop()
3517 vrp->param.anadv_en &= ~MII_ABILITY_PAUSE; in vr_mac_setprop()
3519 vrp->param.anadv_en |= MII_ABILITY_PAUSE; in vr_mac_setprop()
3526 vrp->param.mtu = (uint32_t)val; in vr_mac_setprop()
3533 vrp->chip.link.speed = in vr_mac_setprop()
3536 vrp->chip.link.speed = in vr_mac_setprop()
3547 vrp->chip.mii.anadv = vrp->param.anadv_en & in vr_mac_setprop()
3548 (vrp->param.an_phymask & vrp->param.an_macmask); in vr_mac_setprop()
3551 mutex_exit(&vrp->oplock); in vr_mac_setprop()
3582 prtdata.ifname = vrp->ifname; in vr_log()