Home
last modified time | relevance | path

Searched +full:tx +full:- +full:delay +full:- +full:ps (Results 1 – 25 of 154) sorted by relevance

1234567

/linux/arch/riscv/boot/dts/starfive/
H A Djh7110-starfive-visionfive-2-v1.3b.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7110-starfive-visionfive-2.dtsi"
12 compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
16 starfive,tx-use-rgmii-clk;
17 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
18 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
22 starfive,tx-use-rgmii-clk;
23 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
24 assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
[all …]
H A Djh7110-pine64-star64.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
18 starfive,tx-use-rgmii-clk;
19 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
20 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
25 phy-handle = <&phy1>;
26 phy-mode = "rgmii-id";
27 starfive,tx-use-rgmii-clk;
28 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
[all …]
H A Djh7110-milkv-mars.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
10 model = "Milk-V Mars";
15 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
16 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
17 starfive,tx-use-rgmii-clk;
34 rx-internal-delay-ps = <1500>;
35 tx-internal-delay-ps = <1500>;
36 motorcomm,rx-clk-drv-microamp = <3970>;
[all …]
H A Djh7110-starfive-visionfive-2-v1.2a.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7110-starfive-visionfive-2.dtsi"
12 compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
16 phy-mode = "rmii";
17 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>,
19 assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>,
24 rx-internal-delay-ps = <1900>;
25 tx-internal-delay-ps = <1350>;
/linux/Documentation/devicetree/bindings/net/dsa/
H A Dvitesse,vsc73xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 The Vitesse DSA Switches were produced in the early-to-mid 2000s.
19 Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
20 Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
21 Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
22 Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
27 reside inside a SPI bus device tree node, see spi/spi-bus.txt
[all …]
H A Dmicrochip,lan937x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - UNGLinuxDriver@microchip.com
13 - $ref: dsa.yaml#/$defs/ethernet-ports
18 - microchip,lan9370
19 - microchip,lan9371
20 - microchip,lan9372
21 - microchip,lan9373
22 - microchip,lan9374
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Drenesas,etheravb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
15 - items:
16 - enum:
17 - renesas,etheravb-r8a7742 # RZ/G1H
18 - renesas,etheravb-r8a7743 # RZ/G1M
19 - renesas,etheravb-r8a7744 # RZ/G1N
20 - renesas,etheravb-r8a7745 # RZ/G1E
[all …]
H A Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
[all …]
H A Dadi,adin.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marcelo Schmitt <marcelo.schmitt@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
28 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
[all …]
H A Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
23 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
[all …]
H A Drenesas,ethertsn.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Ethernet TSN End-station
10 - Niklas Söderlund <niklas.soderlund@ragnatech.se>
14 Gbps full-duplex link via MII/GMII/RMII/RGMII. Depending on the connected PHY.
17 - $ref: ethernet-controller.yaml#
22 - enum:
23 - renesas,r8a779g0-ethertsn # R-Car V4H
24 - const: renesas,rcar-gen4-ethertsn
[all …]
H A Dmediatek-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biao Huang <biao.huang@mediatek.com>
21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
25 - compatible
28 - $ref: snps,dwmac.yaml#
[all …]
H A Dingenic,mac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
18 - ingenic,jz4775-mac
19 - ingenic,x1000-mac
20 - ingenic,x1600-mac
21 - ingenic,x1830-mac
22 - ingenic,x2000-mac
30 interrupt-names:
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-meson8b.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
35 /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one
36 * cycle of the 125MHz RGMII TX clock):
57 * the automatically delay and skew automatically (internally).
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
62 * delay (= the counter value) when to start sampling RXEN and RXD[3:0].
66 * large input delay, the bit for that signal (RXEN = bit 0, RXD[3] = bit 1,
67 * ...) can be configured to be 1 to compensate for a delay of about 1ns.
73 /* Defined for adding a delay to the input RX_CLK for better timing.
[all …]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h6-orangepi-one-plus.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 #include "sun50i-h6-orangepi.dtsi"
9 compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6";
15 reg_gmac_3v3: gmac-3v3 {
16 compatible = "regulator-fixed";
17 regulator-name = "vcc-gmac-3v3";
18 regulator-min-microvolt = <3300000>;
19 regulator-max-microvolt = <3300000>;
20 startup-delay-us = <100000>;
21 enable-active-high;
[all …]
H A Dsun50i-h616-orangepi-zero2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "sun50i-h616-orangepi-zero.dtsi"
9 #include "sun50i-h616-cpu-opp.dtsi"
13 compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
17 cpu-supply = <&reg_dcdca>;
21 allwinner,rx-delay-ps = <3100>;
22 allwinner,tx-delay-ps = <700>;
23 phy-mode = "rgmii";
24 phy-supply = <&reg_dcdce>;
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm47094-asus-rt-ac88u.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 /dts-v1/;
8 #include "bcm47094-asus-rt-ac3100.dtsi"
11 compatible = "asus,rt-ac88u", "brcm,bcm47094", "brcm,bcm4708";
12 model = "ASUS RT-AC88U";
16 #nvmem-cell-cells = <1>;
22 mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;
23 mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
24 reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
25 realtek,disable-leds;
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am642-evm-icssg1-dualemac.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include "k3-pinctrl.h"
16 ethernet1 = "/icssg1-eth/ethernet-ports/port@1";
19 mdio-mux-2 {
20 compatible = "mdio-mux-multiplexer";
21 mux-controls = <&mdio_mux>;
22 mdio-parent-bus = <&icssg1_mdio>;
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_lp.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 /* Definitions for the LP-PHY */
22 #define B43_LPPHY_PA_RAMP_TX_TO B43_PHY_CCK(0x10) /* PA Ramp TX Timeout */
24 #define B43_LPPHY_PA_RAMP_TX_TIME_IN B43_PHY_CCK(0x12) /* PA ramp TX Time in */
42 #define B43_LPPHY_TX_DCOFFSET1 B43_PHY_CCK(0x2E) /* TX DCOffset1 */
43 #define B43_LPPHY_TX_DCOFFSET2 B43_PHY_CCK(0x2F) /* TX DCOffset2 */
98 #define B43_LPPHY_TX_ERROR B43_PHY_OFDM(0x07) /* TX Error */
132 #define B43_LPPHY_DETECTOR_DELAY_ADJUST B43_PHY_OFDM(0x2A) /* Detector Delay Adjust */
133 #define B43_LPPHY_REDUCED_DETECTOR_DELAY B43_PHY_OFDM(0x2B) /* Reduced Detector Delay */
135 #define B43_LPPHY_CORRELATOR_DIS_DELAY B43_PHY_OFDM(0x2D) /* correlator Dis Delay */
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-lx2160a-bluebox3.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 // Copyright 2020-2021 NXP
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-bluebox3", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-jaguar-ethernet-switch.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * (manual: https://embedded.cherry.de/jaguar-ethernet-switch-user-manual/)
10 * two user controllable LEDs, and an M12 12-pin connector which exposes the
12 * - RS232/RS485 (max 250Kbps/500Kbps, RX pin1, TX pin2)
13 * - two digital inputs (pin4 routed to GPIO3_C5 on SoC, pin5 to GPIO4_B4)
14 * - two digital outputs (pin7 routed to GPIO3_D3 on SoC, pin8 to GPIO3_D1)
15 * - two analog inputs (pin10 to channel1 of ADS1015, pin11 to channel2)
17 * RK3588 Jaguar can be powered entirely through the adapter via the M8 3-pin
18 * connector (12-24V).
21 /dts-v1/;
[all …]
/linux/drivers/net/ethernet/realtek/
H A Datp.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 ushort rx_status; /* Unknown bit assignments :-<. */
39 TxSTAT = 8, RxSTAT = 9, /* Tx and Rx status. */
61 #define CMR1h_TxENABLE 0x01 /* Tx unit enable. */
99 inbyte(port + PAR_STATUS); /* Settling time delay */ in read_nibble()
116 inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */ in read_byte_mode0()
117 inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */ in read_byte_mode0()
130 inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */ in read_byte_mode2()
166 outb(outval, port + PAR_DATA); /* Double write for PS/2. */ in write_reg()
186 outb(outval, port + PAR_DATA); /* Double write for PS/2. */ in write_reg_high()
[all …]
/linux/drivers/net/wireless/quantenna/qtnfmac/pcie/
H A Dpearl_pcie.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/delay.h>
47 struct qtnf_shm_ipc_region bda_shm_reg1 __aligned(4096); /* host TX */
100 static inline void qtnf_init_hdp_irqs(struct qtnf_pcie_pearl_state *ps) in qtnf_init_hdp_irqs() argument
104 spin_lock_irqsave(&ps->irq_lock, flags); in qtnf_init_hdp_irqs()
105 ps->pcie_irq_mask = (PCIE_HDP_INT_RX_BITS | PCIE_HDP_INT_TX_BITS); in qtnf_init_hdp_irqs()
106 spin_unlock_irqrestore(&ps->irq_lock, flags); in qtnf_init_hdp_irqs()
109 static inline void qtnf_enable_hdp_irqs(struct qtnf_pcie_pearl_state *ps) in qtnf_enable_hdp_irqs() argument
113 spin_lock_irqsave(&ps->irq_lock, flags); in qtnf_enable_hdp_irqs()
114 writel(ps->pcie_irq_mask, PCIE_HDP_INT_EN(ps->pcie_reg_base)); in qtnf_enable_hdp_irqs()
[all …]
/linux/drivers/net/wireless/marvell/libertas/
H A Dcmdresp.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/delay.h>
18 * lbs_mac_event_disconnected - handles disconnect event. It
19 * reports disconnect to upper layer, clean tx/rx packets,
33 if (priv->connect_status != LBS_CONNECTED) in lbs_mac_event_disconnected()
37 * Cisco AP sends EAP failure and de-auth in less than 0.5 ms. in lbs_mac_event_disconnected()
42 if (priv->wdev->iftype == NL80211_IFTYPE_STATION) in lbs_mac_event_disconnected()
46 netif_stop_queue(priv->dev); in lbs_mac_event_disconnected()
47 netif_carrier_off(priv->dev); in lbs_mac_event_disconnected()
49 /* Free Tx and Rx packets */ in lbs_mac_event_disconnected()
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-sm1-x96-air-gbit.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "meson-sm1-ac2xx.dtsi"
10 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
13 compatible = "amediatech,x96-air-gbit", "amlogic,sm1";
17 compatible = "amlogic,axg-sound-card";
18 model = "X96-AIR";
19 audio-aux-devs = <&tdmout_b>;
20 audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
29 assigned-clocks = <&clkc CLKID_MPLL2>,
[all …]

1234567