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/linux/Documentation/devicetree/bindings/net/
H A Dlantiq,etop-xway.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/lantiq,etop-xway.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Crispin <john@phrozen.org>
14 pattern: "^ethernet@[0-9a-f]+$"
17 const: lantiq,etop-xway
24 - description: TX interrupt
25 - description: RX interrupt
27 interrupt-names:
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H A Dsnps,dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
26 - snps,dwmac-3.610
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H A Dsnps,dwc-qos-ethernet.txt13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
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/linux/Documentation/devicetree/bindings/usb/
H A Dsnps,dwc3-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/snps,dwc3-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 vendor-specific implementation or as a standalone component.
17 - $ref: usb-drd.yaml#
18 - if:
24 - dr_mode
28 $ref: usb-xhci.yaml#
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H A Dchipidea,usb2-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/chipidea,usb2-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
25 clock-names:
31 power-domains:
37 reset-names:
40 "#reset-cells":
48 itc-setting:
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H A Dci-hdrc-usb2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
11 - Peng Fan <peng.fan@nxp.com>
16 - enum:
17 - chipidea,usb2
18 - lsi,zevio-usb
19 - nuvoton,npcm750-udc
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/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac1000_dma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
9 Copyright (C) 2007-2009 STMicroelectronics Ltd
24 pr_info("dwmac1000: Master AXI performs %s burst length\n", in dwmac1000_dma_axi()
27 if (axi->axi_lpi_en) in dwmac1000_dma_axi()
29 if (axi->axi_xit_frm) in dwmac1000_dma_axi()
33 value |= (axi->axi_wr_osr_lmt & DMA_AXI_WR_OSR_LMT_MASK) << in dwmac1000_dma_axi()
37 value |= (axi->axi_rd_osr_lmt & DMA_AXI_RD_OSR_LMT_MASK) << in dwmac1000_dma_axi()
40 /* Depending on the UNDEF bit the Master AXI will perform any burst in dwmac1000_dma_axi()
41 * length according to the BLEN programmed (by default all BLEN are in dwmac1000_dma_axi()
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H A Ddwmac1000.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 Copyright (C) 2007-2009 STMicroelectronics Ltd
23 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
68 #define GMAC_ADDR_HIGH(reg) ((reg > 15) ? 0x00000800 + (reg - 16) * 8 : \
70 #define GMAC_ADDR_LOW(reg) ((reg > 15) ? 0x00000804 + (reg - 16) * 8 : \
97 #define GMAC_CONTROL_BE 0x00200000 /* Frame Burst Enable */
108 #define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */
141 #define GMAC_FLOW_CTRL_TFE 0x00000002 /* Tx Flow Control Enable */
147 #define GMAC_DEBUG_TXFSTS BIT(24) /* MTL Tx FIFO Not Empty Status */
148 #define GMAC_DEBUG_TWCSTS BIT(22) /* MTL Tx FIFO Write Controller */
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/linux/Documentation/networking/device_drivers/ethernet/stmicro/
H A Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
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/linux/drivers/spi/
H A Dspi-meson-spicc.c7 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/clk-provider.h>
24 #include <linux/dma-mapping.h>
31 * DMA achieves a transfer with one or more SPI bursts, each SPI burst is made
32 * up of one or more DMA bursts. The DMA burst implementation mechanism is,
33 * For TX, when the number of words in TXFIFO is less than the preset
34 * reading threshold, SPICC starts a reading DMA burst, which reads the preset
35 * number of words from TX buffer, then writes them into TXFIFO.
37 * writing threshold, SPICC starts a writing request burst, which reads the
40 * - 64 bits per word
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/linux/drivers/net/ethernet/atheros/atlx/
H A Datl1.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
4 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
5 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
8 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
82 /* Wake-On-Lan control register */
89 /* WOL Length ( 2 DWORD ) */
215 /* RX/TX count-down timer to trigger CMB-write. 2us resolution. */
265 /* Normal Interrupt mask without RX/TX enabled */
302 #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* All but 1000-Half */
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/linux/Documentation/devicetree/bindings/dma/
H A Dimg-mdc-dma.txt1 * IMG Multi-threaded DMA Controller (MDC)
4 - compatible: Must be "img,pistachio-mdc-dma".
5 - reg: Must contain the base address and length of the MDC registers.
6 - interrupts: Must contain all the per-channel DMA interrupts.
7 - clocks: Must contain an entry for each entry in clock-names.
8 See ../clock/clock-bindings.txt for details.
9 - clock-names: Must include the following entries:
10 - sys: MDC system interface clock.
11 - img,cr-periph: Must contain a phandle to the peripheral control syscon
13 - img,max-burst-multiplier: Must be the maximum supported burst size multiplier.
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/linux/drivers/net/ethernet/broadcom/
H A Dbcm4908_enet.h1 /* SPDX-License-Identifier: GPL-2.0-only */
60 #define ENET_DMA_CH1_CFG 0xa10 /* TX */
62 #define ENET_DMA_CH1_STATE_RAM 0xc10 /* TX */
67 #define ENET_DMA_CH_CFG_BURST_HALT 0x00000004 /* idle after finish current memory burst */
74 #define ENET_DMA_CH_CFG_MAX_BURST 0x0c /* max burst length permitted */
86 #define DMA_CTL_STATUS_PRIO 0x00000C00 /* Prio for Tx */
H A Dbcm63xx_enet.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 /* maximum burst len for dma (4 bytes unit) */
23 /* tx transmit threshold (4 bytes unit), fifo is 256 bytes, the value
24 * must be low enough so that a DMA transfer of above burst length can
29 * hardware maximum rx/tx packet size including FCS, max mtu is
204 /* hw view of rx & tx dma ring */
208 /* allocated size (in bytes) for rx & tx dma ring */
253 /* dma channel id for tx */
256 /* number of dma desc in tx ring */
259 /* maximum dma burst size */
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H A Db44.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define B44_BIST_STAT 0x000CUL /* Built-In Self-Test Status */
18 #define B44_WKUP_LEN 0x0010UL /* Wakeup Length */
44 #define ISTAT_TX 0x01000000 /* TX Interrupt */
56 #define B44_TXBURST 0x00A0UL /* TX Max Burst Length */
57 #define B44_RXBURST 0x00A4UL /* RX Max Burst Length */
71 #define B44_DMATX_CTRL 0x0200UL /* DMA TX Control */
77 #define B44_DMATX_ADDR 0x0204UL /* DMA TX Descriptor Ring Address */
78 #define B44_DMATX_PTR 0x0208UL /* DMA TX Last Posted Descriptor */
79 #define B44_DMATX_STAT 0x020CUL /* DMA TX Current Active Desc. + Status */
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/linux/arch/arm/boot/dts/axis/
H A Dartpec6.dtsi2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
51 interrupt-parent = <&intc>;
54 #address-cells = <1>;
55 #size-cells = <0>;
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/linux/drivers/net/usb/
H A Dsmsc95xx.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 2007-2008 SMSC
11 /* Tx command words */
17 #define TX_CMD_B_CSUM_ENABLE (0x00004000) /* TX Checksum Enable */
20 #define TX_CMD_B_FRAME_LENGTH_ (0x000007FF) /* Frame Length (bytes) */
24 #define RX_STS_FL_ (0x3FFF0000) /* Frame Length */
27 #define RX_STS_LE_ (0x00001000) /* Length Error */
38 /* SCSRs - System Control and Status Registers */
53 #define INT_STS_TX_STOP_ (0x00020000) /* TX Stopped */
57 #define INT_STS_TDFU_ (0x00002000) /* TX Data FIFO Underrun */
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/linux/drivers/leds/
H A Dleds-sun50i-a100.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2021-2023 Samuel Holland <samuel@sholland.org>
5 * Partly based on drivers/leds/leds-turris-omnia.c, which is:
12 #include <linux/dma-mapping.h>
16 #include <linux/led-class-multicolor.h>
98 static int sun50i_a100_ledc_dma_xfer(struct sun50i_a100_ledc *priv, unsigned int length) in sun50i_a100_ledc_dma_xfer() argument
103 desc = dmaengine_prep_slave_single(priv->dma_chan, priv->dma_handle, in sun50i_a100_ledc_dma_xfer()
104 LEDS_TO_BYTES(length), DMA_MEM_TO_DEV, 0); in sun50i_a100_ledc_dma_xfer()
106 return -ENOMEM; in sun50i_a100_ledc_dma_xfer()
110 return -EIO; in sun50i_a100_ledc_dma_xfer()
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/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2x00queue.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
63 * @SKBDESC_DMA_MAPPED_TX: &skb_dma field has been mapped for TX
86 * @desc_len: Length of the frame descriptor.
87 * @tx_rate_idx: the index of the TX rate, used for TX status reporting
88 * @tx_rate_flags: the TX rate flags, used for TX status reporting
91 * of the scope of the skb->data pointer.
93 * @skb_dma: (PCI-only) the DMA address associated with the sk buffer.
112 * get_skb_frame_desc - Obtain the rt2x00 frame descriptor from a sk_buff.
119 return (struct skb_frame_desc *)&IEEE80211_SKB_CB(skb)->driver_data; in get_skb_frame_desc()
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/linux/drivers/net/ethernet/sun/
H A Dsunqe.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define GLOB_MSIZE 0x0cUL /* Local-memory Size */
45 /* The following registers are for per-qe channel information/status. */
49 #define CREG_TXDS 0x0cUL /* TX descriptor ring ptr */
51 #define CREG_TIMASK 0x14UL /* TX Interrupt Mask */
56 #define CREG_TXWBUFPTR 0x28UL /* Local memory tx write ptr */
57 #define CREG_TXRBUFPTR 0x2cUL /* Local memory tx read ptr */
59 #define CREG_PIPG 0x34UL /* Inter-Frame Gap */
69 #define CREG_STAT_LCOLL 0x02000000 /* Late TX Collision */
74 #define CREG_STAT_CCOFLOW 0x00100000 /* TX Coll-counter Overflow */
[all …]
H A Dsungem.h1 /* SPDX-License-Identifier: GPL-2.0 */
29 #define GREG_CFG_IBURST 0x00000001 /* Infinite Burst */
30 #define GREG_CFG_TXDMALIM 0x0000003e /* TX DMA grant limit */
33 * after infinite burst (Apple) */
39 * This auto-clearing does not occur when the alias at GREG_STAT2
45 #define GREG_STAT_TXINTME 0x00000001 /* TX INTME frame transferred */
46 #define GREG_STAT_TXALL 0x00000002 /* All TX frames transferred */
47 #define GREG_STAT_TXDONE 0x00000004 /* One TX frame transferred */
52 #define GREG_STAT_TXMAC 0x00004000 /* TX MAC signalled interrupt */
69 * signalled to the cpu. GREG_IACK can be used to clear specific top-level
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/linux/drivers/crypto/gemini/
H A Dsl3516-ce.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sl3516-ce.h - hardware cryptographic offloader for cortina/gemini SoC
14 * It acts the same as a network hw, with both RX and TX chained descriptors.
70 /* the burst value is not documented in the datasheet */
78 /* the burst value is not documented in the datasheet */
90 * struct sl3516_ce_descriptor - descriptor for CE operations
100 * struct desc_frame_ctrl - Information for the current descriptor
125 * struct desc_flag_status - flag for this descriptor
140 * struct desc_next - describe chaining of descriptors
158 * struct control - The value of this register is used to set the
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/linux/drivers/dma/dw-edma/
H A Ddw-edma-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
17 #include <linux/dma-mapping.h>
20 #include "dw-edma-core.h"
21 #include "dw-edma-v0-core.h"
22 #include "dw-hdma-v0-core.h"
24 #include "../virt-dma.h"
35 struct dw_edma_chip *chip = chan->dw->chip; in dw_edma_get_pci_address()
37 if (chip->ops->pci_address) in dw_edma_get_pci_address()
38 return chip->ops->pci_address(chip->dev, cpu_addr); in dw_edma_get_pci_address()
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/linux/drivers/usb/dwc3/
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0
3 * core.c - DesignWare USB3 DRD Controller Core file
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
24 #include <linux/dma-mapping.h>
44 #include "../host/xhci-ext-caps.h"
49 * dwc3_get_dr_mode - Validates and sets dr_mode
55 struct device *dev = dwc->dev; in dwc3_get_dr_mode()
58 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) in dwc3_get_dr_mode()
59 dwc->dr_mode = USB_DR_MODE_OTG; in dwc3_get_dr_mode()
61 mode = dwc->dr_mode; in dwc3_get_dr_mode()
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/linux/drivers/net/wireless/ath/ath11k/
H A Ddebugfs_htt_stats.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
146 /* Length should be multiple of DWORD */
148 /* Can be variable length */
154 /* == TX PDEV STATS == */
209 /* NOTE: Variable length TLV, use length spec to infer array size */
215 /* NOTE: Variable length TLV, use length spec to infer array size */
221 /* NOTE: Variable length TLV, use length spec to infer array size */
227 /* NOTE: Variable length TLV, use length spec to infer array size */
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