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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dimg,meta-intc.txt1 * Meta External Trigger Controller Binding
4 representation of a Meta external trigger controller.
8 - compatible: Specifies the compatibility list for the interrupt controller.
9 The type shall be <string> and the value shall include "img,meta-intc".
11 - num-banks: Specifies the number of interrupt banks (each of which can
14 - interrupt-controller: The presence of this property identifies the node
17 - #interrupt-cells: Specifies the number of cells needed to encode an
20 - #address-cells: Specifies the number of cells needed to encode an
21 address. The type shall be <u32> and the value shall be 0. As such,
22 'interrupt-map' nodes do not have to specify a parent unit address.
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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Darm,coresight-cti.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/arm,coresight-ct
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H A Dcoresight-cti.yaml1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/coresight-cti.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: ARM Coresight Cross Trigger Interface (CTI) device.
11 The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected
13 a star topology via the Cross Trigger Matrix (CTM), which is not programmable.
20 output hardware trigger signals. CTIs can have a maximum number of input and
21 output hardware trigger signals (8 each for v1 CTI, 32 each for v2 CTI). The
31 In general the connections between CTI and components via the trigger signals
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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap5-uevm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
7 #include "omap5-board-common.dtsi"
11 compatible = "ti,omap5-uevm", "ti,omap5";
18 reserved-memory {
19 #address-cells = <2>;
20 #size-cells = <2>;
23 dsp_memory_region: dsp-memory@95000000 {
24 compatible = "shared-dma-pool";
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/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dst,stm32-lptimer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-lptimer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Low-Power Timers
10 The STM32 Low-Power Timer (LPTIM) is a 16-bit timer that provides several
12 - PWM output (with programmable prescaler, configurable polarity)
13 - Trigger source for STM32 ADC/DAC (LPTIM_OUT)
14 - Several counter modes:
15 - quadrature encoder to detect angular position and direction of rotary
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/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Ddbg-tlv.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2018-2024 Intel Corporation
34 * struct iwl_fw_ini_header - Common Header for all ini debug TLV's structures
46 * struct iwl_fw_ini_addr_size - Base address and size that defines
49 * @addr: the base address (fixe
259 __le32 address; global() member
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/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm47081-luxul-xwr-1200.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 /dts-v1/;
9 #include "bcm5301x-nand-cs0-bch4.dtsi"
12 compatible = "luxul,xwr-120
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H A Dbcm53573.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-binding
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H A Dbcm47094-dlink-dir-890l.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Device tree for D-Link DIR-890L
4 * D-Link calls this board "WRGAC36"
5 * this router has the same looks and form factor as D-Link DIR-88
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H A Dbcm47094-asus-rt-ac88u.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 /dts-v1/;
8 #include "bcm47094-asus-rt-ac3100.dtsi"
11 compatible = "asus,rt-ac88
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H A Dbcm47094-linksys-panamera.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 /dts-v1/;
9 #include "bcm5301x-nand-cs0-bch8.dtsi"
30 gpio-key
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H A Dbcm47189-luxul-xap-810.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 /dts-v1/;
11 compatible = "luxul,xap-810-v1", "brcm,bcm47189", "brcm,bcm53573";
12 model = "Luxul XAP-810 V1";
23 leds-
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/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dcdns,qspi-nor.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
5 $schema: http://devicetree.org/meta-schema
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H A Dcadence-quadspi.txt4 - compatible : should be one of the following:
5 Generic default - "cdns,qspi-nor".
6 For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
7 For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
8 For Intel LGM SoC - "intel,lgm-qspi", "cdns,qspi-nor".
9 - reg : Contains two entries, each of which is a tuple consisting of a
10 physical address and length. The first entry is the address and
12 address and length of the QSPI Controller data area.
13 - interrupts : Unit interrupt specifier for the controller interrupt.
14 - clocks : phandle to the Quad SPI clock.
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/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstm32f746.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include "../armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32fx-clock.h>
45 #include <dt-bindings/mfd/stm32f7-rcc.h>
48 #address-cells = <1>;
49 #size-cell
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H A Dstm32mp131.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-binding
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H A Dstm32f429.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
22 * MA 02110-1301 USA
48 #include "../armv7-m.dtsi"
49 #include <dt-bindings/clock/stm32fx-clock.h>
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
53 #address-cells = <1>;
54 #size-cells = <1>;
57 clk_hse: clk-hse {
58 #clock-cells = <0>;
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/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Dkirkwood-l-50.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Check Point L-50 Board Description
7 /dts-v1/;
10 #include "kirkwood-6281.dtsi"
13 model = "Check Point L-50";
14 compatible = "checkpoint,l-50", "marvell,kirkwood-88f6281", "marvell,kirkwood";
23 stdout-pat
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/freebsd/sys/contrib/dev/iwlwifi/fw/
H A Derror-dump.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2014-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
17 * enum iwl_fw_error_dump_type - types of data in the dump file
18 * @IWL_FW_ERROR_DUMP_CSR: Control Status Registers - fro
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/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_hsi_debug_tools.h2 * Copyright (c) 2017-2018 Cavium, Inc.
258 * Attention block per-type data
274 …struct dbg_attn_block_type_data per_type_data[2] /* attention block per-type data. Count must matc…
283 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK 0xFFFFFF /* STS attention register GRC address (in d…
287 …ntions within the blocks attentions list (a value in the range 0..number of block attentions-1) */;
326 …ntions within the blocks attentions list (a value in the range 0..number of block attentions-1) */;
328 #define DBG_ATTN_REG_STS_ADDRESS_MASK 0xFFFFFF /* STS attention register GRC address (in dwords) …
332 u32 sts_clr_address /* STS_CLR attention register GRC address (in dwords) */;
333 u32 mask_address /* MASK attention register GRC address (in dwords) */;
372 #define DBG_BUS_LINE_NUM_OF_GROUPS_MASK 0xF /* Number of groups in the line (0-3) */
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/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Dcadence-quadspi.txt4 - compatible : should be one of the following:
5 Generic default - "cdns,qspi-nor".
6 For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
7 For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
8 - reg : Contains two entries, each of which is a tuple consisting of a
9 physical address and length. The first entry is the address and
11 address and length of the QSPI Controller data area.
12 - interrupts : Unit interrupt specifier for the controller interrupt.
13 - clocks : phandle to the Quad SPI clock.
14 - cdns,fifo-depth : Size of the data FIFO in words.
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/freebsd/sys/contrib/device-tree/src/arm64/broadcom/bcmbca/
H A Dbcm4906-netgear-r8000p.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/leds/common.h>
19 compatible = "gpio-leds";
21 led-power-white {
27 led-power-amber {
33 led-wps {
39 led-2ghz {
45 led-5ghz-1 {
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/freebsd/sys/contrib/device-tree/Bindings/iio/adc/
H A Dat91_adc.txt4 - compatible: Should be "atmel,<chip>-adc"
6 - reg: Should contain ADC registers location and length
7 - interrupts: Should contain the IRQ line for the ADC
8 - clock-names: tuple listing input clock names.
10 - clocks: phandles to input clocks.
11 - atmel,adc-channels-used: Bitmask of the channels muxed and enabled for this
13 - atmel,adc-startup-time: Startup Time of the ADC in microseconds as
15 - atmel,adc-vref: Reference voltage in millivolts for the conversions
16 - atmel,adc-res: List of resolutions in bits supported by the ADC. List size
18 - atmel,adc-res-names: Contains one identifier string for each resolution
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/freebsd/sys/contrib/device-tree/Bindings/leds/
H A Dcommon.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacek Anaszewski <jacek.anaszewski@gmail.com>
11 - Pave
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/freebsd/sys/contrib/device-tree/src/arm/intel/ixp/
H A Dintel-ixp42x-freecom-fsg-3.dts1 // SPDX-License-Identifier: ISC
3 * Device Tree file for the Freecom FSG-3 router.
8 /dts-v1/;
10 #include "intel-ixp42x.dtsi"
11 #include <dt-bindings/input/input.h>
14 model = "Freecom FSG-3";
15 compatible = "freecom,fsg-3", "intel,ixp42x";
16 #address-cell
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