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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dnv20.c31 u32 flags, struct nvkm_fb_tile *tile) in nv20_fb_tile_init() argument
33 tile->addr = 0x00000001 | addr; in nv20_fb_tile_init()
34 tile->limit = max(1u, addr + size) - 1; in nv20_fb_tile_init()
35 tile->pitch = pitch; in nv20_fb_tile_init()
37 fb->func->tile.comp(fb, i, size, flags, tile); in nv20_fb_tile_init()
38 tile->addr |= 2; in nv20_fb_tile_init()
44 struct nvkm_fb_tile *tile) in nv20_fb_tile_comp() argument
48 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv20_fb_tile_comp()
49 if (!(flags & 2)) tile->zcomp = 0x00000000; /* Z16 */ in nv20_fb_tile_comp()
50 else tile->zcomp = 0x04000000; /* Z24S8 */ in nv20_fb_tile_comp()
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H A Dnv30.c31 u32 flags, struct nvkm_fb_tile *tile) in nv30_fb_tile_init() argument
35 tile->addr = (0 << 4); in nv30_fb_tile_init()
37 if (fb->func->tile.comp) /* z compression */ in nv30_fb_tile_init()
38 fb->func->tile.comp(fb, i, size, flags, tile); in nv30_fb_tile_init()
39 tile->addr = (1 << 4); in nv30_fb_tile_init()
42 tile->addr |= 0x00000001; /* enable */ in nv30_fb_tile_init()
43 tile->addr |= addr; in nv30_fb_tile_init()
44 tile->limit = max(1u, addr + size) - 1; in nv30_fb_tile_init()
45 tile->pitch = pitch; in nv30_fb_tile_init()
50 struct nvkm_fb_tile *tile) in nv30_fb_tile_comp() argument
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H A Dnv10.c31 u32 flags, struct nvkm_fb_tile *tile) in nv10_fb_tile_init() argument
33 tile->addr = 0x80000000 | addr; in nv10_fb_tile_init()
34 tile->limit = max(1u, addr + size) - 1; in nv10_fb_tile_init()
35 tile->pitch = pitch; in nv10_fb_tile_init()
39 nv10_fb_tile_fini(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv10_fb_tile_fini() argument
41 tile->addr = 0; in nv10_fb_tile_fini()
42 tile->limit = 0; in nv10_fb_tile_fini()
43 tile->pitch = 0; in nv10_fb_tile_fini()
44 tile->zcomp = 0; in nv10_fb_tile_fini()
48 nv10_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv10_fb_tile_prog() argument
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H A Dnv35.c31 struct nvkm_fb_tile *tile) in nv35_fb_tile_comp() argument
35 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv35_fb_tile_comp()
36 if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */ in nv35_fb_tile_comp()
37 else tile->zcomp |= 0x08000000; /* Z24S8 */ in nv35_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 6); in nv35_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 13; in nv35_fb_tile_comp()
41 tile->zcomp |= 0x40000000; in nv35_fb_tile_comp()
50 .tile.regions = 8,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv35_fb_tile_comp,
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H A Dnv36.c31 struct nvkm_fb_tile *tile) in nv36_fb_tile_comp() argument
35 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv36_fb_tile_comp()
36 if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */ in nv36_fb_tile_comp()
37 else tile->zcomp |= 0x20000000; /* Z24S8 */ in nv36_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 6); in nv36_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 14; in nv36_fb_tile_comp()
41 tile->zcomp |= 0x80000000; in nv36_fb_tile_comp()
50 .tile.regions = 8,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv36_fb_tile_comp,
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H A Dnv44.c31 u32 flags, struct nvkm_fb_tile *tile) in nv44_fb_tile_init() argument
33 tile->addr = 0x00000001; /* mode = vram */ in nv44_fb_tile_init()
34 tile->addr |= addr; in nv44_fb_tile_init()
35 tile->limit = max(1u, addr + size) - 1; in nv44_fb_tile_init()
36 tile->pitch = pitch; in nv44_fb_tile_init()
40 nv44_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv44_fb_tile_prog() argument
43 nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit); in nv44_fb_tile_prog()
44 nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch); in nv44_fb_tile_prog()
45 nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr); in nv44_fb_tile_prog()
60 .tile.regions = 12,
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H A Dnv40.c31 struct nvkm_fb_tile *tile) in nv40_fb_tile_comp() argument
36 !nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv40_fb_tile_comp()
37 tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */ in nv40_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 8); in nv40_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13; in nv40_fb_tile_comp()
41 tile->zcomp |= 0x40000000; in nv40_fb_tile_comp()
56 .tile.regions = 8,
57 .tile.init = nv30_fb_tile_init,
58 .tile.comp = nv40_fb_tile_comp,
59 .tile.fini = nv20_fb_tile_fini,
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H A Dnv25.c31 struct nvkm_fb_tile *tile) in nv25_fb_tile_comp() argument
35 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv25_fb_tile_comp()
36 if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */ in nv25_fb_tile_comp()
37 else tile->zcomp = 0x00200000; /* Z24S8 */ in nv25_fb_tile_comp()
38 tile->zcomp |= tile->tag->offset; in nv25_fb_tile_comp()
40 tile->zcomp |= 0x01000000; in nv25_fb_tile_comp()
48 .tile.regions = 8,
49 .tile.init = nv20_fb_tile_init,
50 .tile.comp = nv25_fb_tile_comp,
51 .tile.fini = nv20_fb_tile_fini,
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H A Dnv46.c31 u32 flags, struct nvkm_fb_tile *tile) in nv46_fb_tile_init() argument
34 if (!(flags & 4)) tile->addr = (0 << 3); in nv46_fb_tile_init()
35 else tile->addr = (1 << 3); in nv46_fb_tile_init()
37 tile->addr |= 0x00000001; /* mode = vram */ in nv46_fb_tile_init()
38 tile->addr |= addr; in nv46_fb_tile_init()
39 tile->limit = max(1u, addr + size) - 1; in nv46_fb_tile_init()
40 tile->pitch = pitch; in nv46_fb_tile_init()
46 .tile.regions = 15,
47 .tile.init = nv46_fb_tile_init,
48 .tile.fini = nv20_fb_tile_fini,
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H A Dnv41.c30 nv41_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv41_fb_tile_prog() argument
33 nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit); in nv41_fb_tile_prog()
34 nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch); in nv41_fb_tile_prog()
35 nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr); in nv41_fb_tile_prog()
37 nvkm_wr32(device, 0x100700 + (i * 0x04), tile->zcomp); in nv41_fb_tile_prog()
50 .tile.regions = 12,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv40_fb_tile_comp,
53 .tile.fini = nv20_fb_tile_fini,
54 .tile.prog = nv41_fb_tile_prog,
H A Dbase.c35 nvkm_fb_tile_fini(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile) in nvkm_fb_tile_fini() argument
37 fb->func->tile.fini(fb, region, tile); in nvkm_fb_tile_fini()
42 u32 pitch, u32 flags, struct nvkm_fb_tile *tile) in nvkm_fb_tile_init() argument
44 fb->func->tile.init(fb, region, addr, size, pitch, flags, tile); in nvkm_fb_tile_init()
48 nvkm_fb_tile_prog(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile) in nvkm_fb_tile_prog() argument
51 if (fb->func->tile.prog) { in nvkm_fb_tile_prog()
52 fb->func->tile.prog(fb, region, tile); in nvkm_fb_tile_prog()
201 for (i = 0; i < fb->tile.regions; i++) in nvkm_fb_init()
202 fb->func->tile.prog(fb, i, &fb->tile.region[i]); in nvkm_fb_init()
240 for (i = 0; i < fb->tile.regions; i++) in nvkm_fb_dtor()
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/linux/tools/perf/pmu-events/arch/x86/knightslanding/
H A Dcache.json67 …ounts the loads retired that get the data from the other core in the same tile in M state (Precise…
135 …data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. …
145 …ata forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. …
155 … data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
165 …r responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
175 …esponses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
185 … responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
195 …refetch code read requests that accounts for responses which hit its own tile's L2 with data in E…
205 …refetch code read requests that accounts for responses which hit its own tile's L2 with data in F…
215 …refetch code read requests that accounts for responses which hit its own tile's L2 with data in M…
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/linux/drivers/gpu/drm/xe/
H A Dxe_pt.c61 static u64 __xe_pt_empty_pte(struct xe_tile *tile, struct xe_vm *vm, in __xe_pt_empty_pte() argument
64 struct xe_device *xe = tile_to_xe(tile); in __xe_pt_empty_pte()
66 u8 id = tile->id; in __xe_pt_empty_pte()
90 * @tile: The tile to create for.
103 struct xe_pt *xe_pt_create(struct xe_vm *vm, struct xe_tile *tile, in xe_pt_create() argument
121 bo_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) | in xe_pt_create()
130 bo = xe_bo_create_pin_map(vm->xe, tile, vm, SZ_4K, in xe_pt_create()
143 xe_tile_assert(tile, level <= XE_VM_MAX_LEVEL); in xe_pt_create()
156 * @tile: The tile the scratch pagetable of which to use.
160 * Populate the page-table bo of @pt with entries pointing into the tile's
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H A Dxe_tile_sysfs.c27 struct xe_tile *tile = arg; in tile_sysfs_fini() local
29 kobject_put(tile->sysfs); in tile_sysfs_fini()
32 int xe_tile_sysfs_init(struct xe_tile *tile) in xe_tile_sysfs_init() argument
34 struct xe_device *xe = tile_to_xe(tile); in xe_tile_sysfs_init()
44 kt->tile = tile; in xe_tile_sysfs_init()
46 err = kobject_add(&kt->base, &dev->kobj, "tile%d", tile->id); in xe_tile_sysfs_init()
50 tile->sysfs = &kt->base; in xe_tile_sysfs_init()
52 err = xe_vram_freq_sysfs_init(tile); in xe_tile_sysfs_init()
56 return devm_add_action_or_reset(xe->drm.dev, tile_sysfs_fini, tile); in xe_tile_sysfs_init()
H A Dxe_mmio.c28 struct xe_tile *tile; in tiles_fini() local
31 for_each_remote_tile(tile, xe, id) in tiles_fini()
32 tile->mmio.regs = NULL; in tiles_fini()
36 * On multi-tile devices, partition the BAR space for MMIO on each tile,
38 * tile_mmio_size contains both the tile's 4MB register space, as well as
56 struct xe_tile *tile; in mmio_multi_tile_setup() local
60 * Nothing to be done as tile 0 has already been setup earlier with the in mmio_multi_tile_setup()
66 for_each_remote_tile(tile, xe, id) in mmio_multi_tile_setup()
67 xe_mmio_init(&tile->mmio, tile, xe->mmio.regs + id * tile_mmio_size, SZ_4M); in mmio_multi_tile_setup()
96 * The first 16MB of the BAR, belong to the root tile, and include: in xe_mmio_probe_early()
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H A Dxe_ggtt.c126 struct xe_tile *tile = ggtt->tile; in ggtt_update_access_counter() local
130 if (tile->primary_gt && XE_GT_WA(tile->primary_gt, 22019338487)) { in ggtt_update_access_counter()
131 affected_gt = tile->primary_gt; in ggtt_update_access_counter()
135 xe_tile_assert(tile, IS_DGFX(tile_to_xe(tile))); in ggtt_update_access_counter()
137 affected_gt = tile->media_gt; in ggtt_update_access_counter()
141 xe_tile_assert(tile, !IS_DGFX(tile_to_xe(tile))); in ggtt_update_access_counter()
181 xe_tile_assert(ggtt->tile, !(addr & XE_PTE_MASK)); in xe_ggtt_set_pte()
182 xe_tile_assert(ggtt->tile, addr < ggtt->start + ggtt->size); in xe_ggtt_set_pte()
195 xe_tile_assert(ggtt->tile, !(addr & XE_PTE_MASK)); in xe_ggtt_get_pte()
196 xe_tile_assert(ggtt->tile, addr < ggtt->size); in xe_ggtt_get_pte()
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H A Dxe_pcode.h15 void xe_pcode_init(struct xe_tile *tile);
18 int xe_pcode_init_min_freq_table(struct xe_tile *tile, u32 min_gt_freq,
20 int xe_pcode_read(struct xe_tile *tile, u32 mbox, u32 *val, u32 *val1);
21 int xe_pcode_write_timeout(struct xe_tile *tile, u32 mbox, u32 val,
23 int xe_pcode_write64_timeout(struct xe_tile *tile, u32 mbox, u32 data0,
26 #define xe_pcode_write(tile, mbox, val) \ argument
27 xe_pcode_write_timeout(tile, mbox, val, 1)
29 int xe_pcode_request(struct xe_tile *tile, u32 mbox, u32 request,
H A Dxe_bo_evict.c162 struct xe_tile *tile; in xe_bo_evict_all() local
181 for_each_tile(tile, xe, id) in xe_bo_evict_all()
182 xe_tile_migrate_wait(tile); in xe_bo_evict_all()
201 struct xe_tile *tile; in xe_bo_restore_and_map_ggtt() local
204 for_each_tile(tile, xe_bo_device(bo), id) { in xe_bo_restore_and_map_ggtt()
205 if (tile != bo->tile && !(bo->flags & XE_BO_FLAG_GGTTx(tile))) in xe_bo_restore_and_map_ggtt()
208 xe_ggtt_map_bo_unlocked(tile->mem.ggtt, bo); in xe_bo_restore_and_map_ggtt()
245 struct xe_tile *tile; in xe_bo_restore_late() local
252 for_each_tile(tile, xe, id) in xe_bo_restore_late()
253 xe_tile_migrate_wait(tile); in xe_bo_restore_late()
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/linux/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_mman.c32 struct tile { struct
46 static u64 tiled_offset(const struct tile *tile, u64 v) in tiled_offset() argument
50 if (tile->tiling == I915_TILING_NONE) in tiled_offset()
53 y = div64_u64_rem(v, tile->stride, &x); in tiled_offset()
54 v = div64_u64_rem(y, tile->height, &y) * tile->stride * tile->height; in tiled_offset()
56 if (tile->tiling == I915_TILING_X) { in tiled_offset()
57 v += y * tile->width; in tiled_offset()
58 v += div64_u64_rem(x, tile->width, &x) << tile->size; in tiled_offset()
60 } else if (tile->width == 128) { in tiled_offset()
76 switch (tile->swizzle) { in tiled_offset()
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/linux/drivers/gpu/ipu-v3/
H A Dipu-image-convert.c28 * tile (but taking care to pass the full frame stride length to
30 * to convert each tile back-to-back when possible (see note below
45 * reusable temporary tile buffer and then rotating with the 8x8
61 * With rotation or flipping, tile order changes between input and
96 /* dimensions of one tile */
106 /* start Y or packed offset of this tile */
108 /* offset from start to tile in U plane, for planar formats */
110 /* offset from start to tile in V plane, for planar formats */
126 struct ipu_image_tile tile[MAX_TILES]; member
185 /* next tile to process */
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/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv44.c31 nv44_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) in nv44_gr_tile() argument
44 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
45 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv44_gr_tile()
46 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
53 nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
54 nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit); in nv44_gr_tile()
55 nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
56 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); in nv44_gr_tile()
57 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); in nv44_gr_tile()
58 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); in nv44_gr_tile()
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/linux/drivers/gpu/drm/imagination/
H A Dpvr_rogue_cr_defs_client.h64 * X1 MacroTile boundary, left tile X for second column of macrotiles (16MT mode) - 32 pixels across
65 * tile
70 * X2 MacroTile boundary, left tile X for third(16MT) column of macrotiles - 32 pixels across tile
75 * X3 MacroTile boundary, left tile X for fourth column of macrotiles (16MT) - 32 pixels across tile
85 * X1 MacroTile boundary, ltop tile Y for second column of macrotiles (16MT mode) - 32 pixels tile
91 * X2 MacroTile boundary, top tile Y for third(16MT) column of macrotiles - 32 pixels tile height
96 * X3 MacroTile boundary, top tile Y for fourth column of macrotiles (16MT) - 32 pixels tile height
110 * Maximum Y tile address visible on screen, 32 pixel tile height, 16Kx16K max screen size
115 * Maximum X tile address visible on screen, 32 pixel tile width, 16Kx16K max screen size
/linux/drivers/hid/
H A Dhid-picolcd_fb.c22 * each. Each tile has 8x64 pixel, each data byte representing
23 * a 1-bit wide vertical line of the tile.
25 * The display can be updated at a tile granularity.
29 * | Tile 1 | Tile 1 | Tile 1 | Tile 1 |
31 * | Tile 2 | Tile 2 | Tile 2 | Tile 2 |
35 * | Tile 8 | Tile 8 | Tile 8 | Tile 8 |
89 /* Send a given tile to PicoLCD */
91 int chip, int tile) in picolcd_fb_send_tile() argument
114 hid_set_field(report1->field[0], 4, 0xb8 | tile); in picolcd_fb_send_tile()
127 tdata = vbitmap + (tile * 4 + chip) * 64; in picolcd_fb_send_tile()
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/linux/arch/arm/mach-versatile/
H A DKconfig129 bool "Integrator/CT926 (ARM926EJ-S) core tile"
135 bool "Integrator/CTB36 (ARM1136JF-S) core tile"
178 the ARM926EJ-S core tile, while on an ARMv6/v7 kernel, at least
180 core tile options should be enabled.
183 bool "Support ARM1136J(F)-S Tile"
187 Enable support for the ARM1136 tile fitted to the
191 bool "Support ARM1176JZ(F)-S Tile"
194 Enable support for the ARM1176 tile fitted to the
198 bool "Support Multicore Cortex-A9 Tile"
201 Enable support for the Cortex-A9MPCore tile fitted to the
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/linux/Documentation/devicetree/bindings/arm/
H A Darm,vexpress-juno.yaml22 The motherboard and each core tile should be described by a separate Device
23 Tree source file, with the tile's description including the motherboard file
33 The root node indicates the CPU SoC on the core tile, and this
35 string shall match the name given in the core tile's technical reference
37 further subvariants are released of the core tile, even more fine-granular
46 in MPCore configuration in a test chip on the core tile. See ARM
52 in a test chip on the core tile. It is intended to evaluate NEON, FPU
58 cores in a MPCore configuration in a test chip on the core tile. See
64 A15 CPU cores in a test chip on the core tile. This is the first test
72 in a test chip on the core tile. See ARM DDI 0503I.
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