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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dnv20.c31 u32 flags, struct nvkm_fb_tile *tile) in nv20_fb_tile_init() argument
33 tile->addr = 0x00000001 | addr; in nv20_fb_tile_init()
34 tile->limit = max(1u, addr + size) - 1; in nv20_fb_tile_init()
35 tile->pitch = pitch; in nv20_fb_tile_init()
37 fb->func->tile.comp(fb, i, size, flags, tile); in nv20_fb_tile_init()
38 tile->addr |= 2; in nv20_fb_tile_init()
44 struct nvkm_fb_tile *tile) in nv20_fb_tile_comp() argument
48 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv20_fb_tile_comp()
49 if (!(flags & 2)) tile->zcomp = 0x00000000; /* Z16 */ in nv20_fb_tile_comp()
50 else tile->zcomp = 0x04000000; /* Z24S8 */ in nv20_fb_tile_comp()
[all …]
H A Dnv30.c31 u32 flags, struct nvkm_fb_tile *tile) in nv30_fb_tile_init() argument
35 tile->addr = (0 << 4); in nv30_fb_tile_init()
37 if (fb->func->tile.comp) /* z compression */ in nv30_fb_tile_init()
38 fb->func->tile.comp(fb, i, size, flags, tile); in nv30_fb_tile_init()
39 tile->addr = (1 << 4); in nv30_fb_tile_init()
42 tile->addr |= 0x00000001; /* enable */ in nv30_fb_tile_init()
43 tile->addr |= addr; in nv30_fb_tile_init()
44 tile->limit = max(1u, addr + size) - 1; in nv30_fb_tile_init()
45 tile->pitch = pitch; in nv30_fb_tile_init()
50 struct nvkm_fb_tile *tile) in nv30_fb_tile_comp() argument
[all …]
H A Dnv10.c31 u32 flags, struct nvkm_fb_tile *tile) in nv10_fb_tile_init() argument
33 tile->addr = 0x80000000 | addr; in nv10_fb_tile_init()
34 tile->limit = max(1u, addr + size) - 1; in nv10_fb_tile_init()
35 tile->pitch = pitch; in nv10_fb_tile_init()
39 nv10_fb_tile_fini(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv10_fb_tile_fini() argument
41 tile->addr = 0; in nv10_fb_tile_fini()
42 tile->limit = 0; in nv10_fb_tile_fini()
43 tile->pitch = 0; in nv10_fb_tile_fini()
44 tile->zcomp = 0; in nv10_fb_tile_fini()
48 nv10_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv10_fb_tile_prog() argument
[all …]
H A Dnv35.c31 struct nvkm_fb_tile *tile) in nv35_fb_tile_comp() argument
35 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv35_fb_tile_comp()
36 if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */ in nv35_fb_tile_comp()
37 else tile->zcomp |= 0x08000000; /* Z24S8 */ in nv35_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 6); in nv35_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 13; in nv35_fb_tile_comp()
41 tile->zcomp |= 0x40000000; in nv35_fb_tile_comp()
50 .tile.regions = 8,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv35_fb_tile_comp,
[all …]
H A Dnv36.c31 struct nvkm_fb_tile *tile) in nv36_fb_tile_comp() argument
35 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv36_fb_tile_comp()
36 if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */ in nv36_fb_tile_comp()
37 else tile->zcomp |= 0x20000000; /* Z24S8 */ in nv36_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 6); in nv36_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 14; in nv36_fb_tile_comp()
41 tile->zcomp |= 0x80000000; in nv36_fb_tile_comp()
50 .tile.regions = 8,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv36_fb_tile_comp,
[all …]
H A Dnv44.c31 u32 flags, struct nvkm_fb_tile *tile) in nv44_fb_tile_init() argument
33 tile->addr = 0x00000001; /* mode = vram */ in nv44_fb_tile_init()
34 tile->addr |= addr; in nv44_fb_tile_init()
35 tile->limit = max(1u, addr + size) - 1; in nv44_fb_tile_init()
36 tile->pitch = pitch; in nv44_fb_tile_init()
40 nv44_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv44_fb_tile_prog() argument
43 nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit); in nv44_fb_tile_prog()
44 nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch); in nv44_fb_tile_prog()
45 nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr); in nv44_fb_tile_prog()
60 .tile.regions = 12,
[all …]
H A Dnv40.c31 struct nvkm_fb_tile *tile) in nv40_fb_tile_comp() argument
36 !nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv40_fb_tile_comp()
37 tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */ in nv40_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 8); in nv40_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13; in nv40_fb_tile_comp()
41 tile->zcomp |= 0x40000000; in nv40_fb_tile_comp()
56 .tile.regions = 8,
57 .tile.init = nv30_fb_tile_init,
58 .tile.comp = nv40_fb_tile_comp,
59 .tile.fini = nv20_fb_tile_fini,
[all …]
H A Dnv25.c31 struct nvkm_fb_tile *tile) in nv25_fb_tile_comp() argument
35 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv25_fb_tile_comp()
36 if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */ in nv25_fb_tile_comp()
37 else tile->zcomp = 0x00200000; /* Z24S8 */ in nv25_fb_tile_comp()
38 tile->zcomp |= tile->tag->offset; in nv25_fb_tile_comp()
40 tile->zcomp |= 0x01000000; in nv25_fb_tile_comp()
48 .tile.regions = 8,
49 .tile.init = nv20_fb_tile_init,
50 .tile.comp = nv25_fb_tile_comp,
51 .tile.fini = nv20_fb_tile_fini,
[all …]
H A Dnv46.c31 u32 flags, struct nvkm_fb_tile *tile) in nv46_fb_tile_init() argument
34 if (!(flags & 4)) tile->addr = (0 << 3); in nv46_fb_tile_init()
35 else tile->addr = (1 << 3); in nv46_fb_tile_init()
37 tile->addr |= 0x00000001; /* mode = vram */ in nv46_fb_tile_init()
38 tile->addr |= addr; in nv46_fb_tile_init()
39 tile->limit = max(1u, addr + size) - 1; in nv46_fb_tile_init()
40 tile->pitch = pitch; in nv46_fb_tile_init()
46 .tile.regions = 15,
47 .tile.init = nv46_fb_tile_init,
48 .tile.fini = nv20_fb_tile_fini,
[all …]
H A Dnv41.c30 nv41_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv41_fb_tile_prog() argument
33 nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit); in nv41_fb_tile_prog()
34 nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch); in nv41_fb_tile_prog()
35 nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr); in nv41_fb_tile_prog()
37 nvkm_wr32(device, 0x100700 + (i * 0x04), tile->zcomp); in nv41_fb_tile_prog()
50 .tile.regions = 12,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv40_fb_tile_comp,
53 .tile.fini = nv20_fb_tile_fini,
54 .tile.prog = nv41_fb_tile_prog,
H A Dbase.c35 nvkm_fb_tile_fini(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile) in nvkm_fb_tile_fini() argument
37 fb->func->tile.fini(fb, region, tile); in nvkm_fb_tile_fini()
42 u32 pitch, u32 flags, struct nvkm_fb_tile *tile) in nvkm_fb_tile_init() argument
44 fb->func->tile.init(fb, region, addr, size, pitch, flags, tile); in nvkm_fb_tile_init()
48 nvkm_fb_tile_prog(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile) in nvkm_fb_tile_prog() argument
51 if (fb->func->tile.prog) { in nvkm_fb_tile_prog()
52 fb->func->tile.prog(fb, region, tile); in nvkm_fb_tile_prog()
201 for (i = 0; i < fb->tile.regions; i++) in nvkm_fb_init()
202 fb->func->tile.prog(fb, i, &fb->tile.region[i]); in nvkm_fb_init()
240 for (i = 0; i < fb->tile.regions; i++) in nvkm_fb_dtor()
[all …]
/linux/drivers/gpu/drm/xe/
H A Dxe_tile_types.h24 * struct xe_tile - hardware tile structure
26 * From a driver perspective, a "tile" is effectively a complete GPU, containing
29 * Multi-tile platforms effectively bundle multiple GPUs behind a single PCI
30 * device and designate one "root" tile as being responsible for external PCI
32 * tile in a stacked layout, and PCI BAR2 exposes the local memory associated
33 * with each tile similarly. Device-wide interrupts can be enabled/disabled
34 * at the root tile, and the MSTR_TILE_INTR register will report which tiles
38 /** @xe: Backpointer to tile's PCI device */
41 /** @id: ID of the tile */
57 * @mmio: MMIO info for a tile.
[all …]
H A Dxe_pt.c62 static u64 __xe_pt_empty_pte(struct xe_tile *tile, struct xe_vm *vm, in __xe_pt_empty_pte()
65 struct xe_device *xe = tile_to_xe(tile); in __xe_pt_empty_pte()
67 u8 id = tile->id; in __xe_pt_empty_pte()
91 * @tile: The tile to create for.
104 struct xe_pt *xe_pt_create(struct xe_vm *vm, struct xe_tile *tile, in xe_pt_create()
122 bo_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) | in xe_pt_create()
131 bo = xe_bo_create_pin_map(vm->xe, tile, vm, SZ_4K, in xe_pt_create()
144 xe_tile_assert(tile, level <= XE_VM_MAX_LEVEL); in xe_pt_create()
157 * @tile
61 __xe_pt_empty_pte(struct xe_tile * tile,struct xe_vm * vm,unsigned int level) __xe_pt_empty_pte() argument
103 xe_pt_create(struct xe_vm * vm,struct xe_tile * tile,unsigned int level,struct drm_exec * exec) xe_pt_create() argument
163 xe_pt_populate_empty(struct xe_tile * tile,struct xe_vm * vm,struct xe_pt * pt) xe_pt_populate_empty() argument
290 struct xe_tile *tile; global() member
703 xe_pt_stage_bind(struct xe_tile * tile,struct xe_vma * vma,struct xe_svm_range * range,struct xe_vm_pgtable_update * entries,u32 * num_entries,bool clear_pt) xe_pt_stage_bind() argument
872 struct xe_tile *tile; global() member
929 xe_pt_zap_ptes(struct xe_tile * tile,struct xe_vma * vma) xe_pt_zap_ptes() argument
971 xe_pt_zap_ptes_range(struct xe_tile * tile,struct xe_vm * vm,struct xe_svm_range * range) xe_pt_zap_ptes_range() argument
1009 xe_vm_populate_pgtable(struct xe_migrate_pt_update * pt_update,struct xe_tile * tile,struct iosys_map * map,void * data,u32 qword_ofs,u32 num_qwords,const struct xe_vm_pgtable_update * update) xe_vm_populate_pgtable() argument
1183 xe_pt_prepare_bind(struct xe_tile * tile,struct xe_vma * vma,struct xe_svm_range * range,struct xe_vm_pgtable_update * entries,u32 * num_entries,bool invalidate_on_bind) xe_pt_prepare_bind() argument
1553 struct xe_tile *tile; global() member
1611 generate_reclaim_entry(struct xe_tile * tile,struct xe_page_reclaim_list * prl,u64 pte,struct xe_pt * xe_child) generate_reclaim_entry() argument
1828 xe_pt_stage_unbind(struct xe_tile * tile,struct xe_vm * vm,struct xe_vma * vma,struct xe_svm_range * range,struct xe_vm_pgtable_update * entries) xe_pt_stage_unbind() argument
1861 xe_migrate_clear_pgtable_callback(struct xe_migrate_pt_update * pt_update,struct xe_tile * tile,struct iosys_map * map,void * ptr,u32 qword_ofs,u32 num_qwords,const struct xe_vm_pgtable_update * update) xe_migrate_clear_pgtable_callback() argument
1969 bind_op_prepare(struct xe_vm * vm,struct xe_tile * tile,struct xe_vm_pgtable_update_ops * pt_update_ops,struct xe_vma * vma,bool invalidate_on_bind) bind_op_prepare() argument
2036 bind_range_prepare(struct xe_vm * vm,struct xe_tile * tile,struct xe_vm_pgtable_update_ops * pt_update_ops,struct xe_vma * vma,struct xe_svm_range * range) bind_range_prepare() argument
2078 unbind_op_prepare(struct xe_tile * tile,struct xe_vm_pgtable_update_ops * pt_update_ops,struct xe_vma * vma) unbind_op_prepare() argument
2159 unbind_range_prepare(struct xe_vm * vm,struct xe_tile * tile,struct xe_vm_pgtable_update_ops * pt_update_ops,struct xe_svm_range * range) unbind_range_prepare() argument
2199 op_prepare(struct xe_vm * vm,struct xe_tile * tile,struct xe_vm_pgtable_update_ops * pt_update_ops,struct xe_vma_op * op) op_prepare() argument
2308 xe_pt_update_ops_prepare(struct xe_tile * tile,struct xe_vma_ops * vops) xe_pt_update_ops_prepare() argument
2346 bind_op_commit(struct xe_vm * vm,struct xe_tile * tile,struct xe_vm_pgtable_update_ops * pt_update_ops,struct xe_vma * vma,struct dma_fence * fence,struct dma_fence * fence2,bool invalidate_on_bind) bind_op_commit() argument
2388 unbind_op_commit(struct xe_vm * vm,struct xe_tile * tile,struct xe_vm_pgtable_update_ops * pt_update_ops,struct xe_vma * vma,struct dma_fence * fence,struct dma_fence * fence2) unbind_op_commit() argument
2432 op_commit(struct xe_vm * vm,struct xe_tile * tile,struct xe_vm_pgtable_update_ops * pt_update_ops,struct xe_vma_op * op,struct dma_fence * fence,struct dma_fence * fence2) op_commit() argument
2544 xe_pt_update_ops_run(struct xe_tile * tile,struct xe_vma_ops * vops) xe_pt_update_ops_run() argument
2722 xe_pt_update_ops_fini(struct xe_tile * tile,struct xe_vma_ops * vops) xe_pt_update_ops_fini() argument
2748 xe_pt_update_ops_abort(struct xe_tile * tile,struct xe_vma_ops * vops) xe_pt_update_ops_abort() argument
[all...]
H A Dxe_mem_pool.c20 * XE tile.
23 * from a backing buffer object (BO) on a specific XE tile. It is designed to
57 return pool->bo->tile; in pool_to_tile()
72 struct xe_tile *tile = pool->bo->tile; in pool_shadow_init() local
73 struct xe_device *xe = tile_to_xe(tile); in pool_shadow_init()
88 shadow = xe_managed_bo_create_pin_map(xe, tile, in pool_shadow_init()
90 XE_BO_FLAG_VRAM_IF_DGFX(tile) | in pool_shadow_init()
104 * @tile: the &xe_tile where allocate.
111 * specified XE tile. The backing BO is pinned in the GGTT and mapped into
117 struct xe_mem_pool *xe_mem_pool_init(struct xe_tile *tile, u32 size, in xe_mem_pool_init() argument
[all …]
H A Dxe_ggtt.c108 * In general, each tile can contains its own Global Graphics Translation Table
112 /** @tile: Back pointer to tile where this GGTT belongs */ member
113 struct xe_tile *tile;
185 struct xe_tile *tile = ggtt->tile; in ggtt_update_access_counter() local
189 if (tile->primary_gt && XE_GT_WA(tile->primary_gt, 22019338487)) { in ggtt_update_access_counter()
190 affected_gt = tile->primary_gt; in ggtt_update_access_counter()
194 xe_tile_assert(tile, IS_DGF in ggtt_update_access_counter()
299 xe_ggtt_alloc(struct xe_tile * tile) xe_ggtt_alloc() argument
[all...]
H A Dxe_bo_evict.c162 struct xe_tile *tile; in xe_bo_evict_all() local
181 for_each_tile(tile, xe, id) in xe_bo_evict_all()
182 xe_tile_migrate_wait(tile); in xe_bo_evict_all()
201 struct xe_tile *tile; in xe_bo_restore_and_map_ggtt() local
204 for_each_tile(tile, xe_bo_device(bo), id) { in xe_bo_restore_and_map_ggtt()
205 if (tile != bo->tile && !(bo->flags & XE_BO_FLAG_GGTTx(tile))) in xe_bo_restore_and_map_ggtt()
208 xe_ggtt_map_bo_unlocked(tile->mem.ggtt, bo); in xe_bo_restore_and_map_ggtt()
245 struct xe_tile *tile; in xe_bo_restore_late() local
252 for_each_tile(tile, xe, id) in xe_bo_restore_late()
253 xe_tile_migrate_wait(tile); in xe_bo_restore_late()
[all …]
H A Dxe_tile_sysfs_types.h14 * struct kobj_tile - A tile's kobject struct that connects the kobject
15 * and the TILE
18 * TILE needs to be addressed on a given sysfs call.
23 /** @tile: A pointer to the tile itself */
24 struct xe_tile *tile; member
H A Dxe_migrate.c54 /** @tile: Backpointer to the tile this struct xe_migrate belongs to. */ member
55 struct xe_tile *tile;
189 static int xe_migrate_pt_bo_alloc(struct xe_tile *tile, struct xe_migrate *m, in xe_migrate_pt_bo_alloc()
192 struct xe_bo *bo, *batch = tile->mem.kernel_bb_pool->bo; in xe_migrate_pt_bo_alloc()
203 xe_tile_assert(tile, m->batch_base_ofs + xe_bo_size(batch) < SZ_2M); in xe_migrate_pt_bo_alloc()
205 bo = xe_bo_create_pin_map(vm->xe, tile, vm, in xe_migrate_pt_bo_alloc()
208 XE_BO_FLAG_VRAM_IF_DGFX(tile) | in xe_migrate_pt_bo_alloc()
217 static void xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m, in xe_migrate_prepare_vm()
220 struct xe_device *xe = tile_to_xe(tile); in xe_migrate_prepare_vm()
188 xe_migrate_pt_bo_alloc(struct xe_tile * tile,struct xe_migrate * m,struct xe_vm * vm,struct drm_exec * exec) xe_migrate_pt_bo_alloc() argument
216 xe_migrate_prepare_vm(struct xe_tile * tile,struct xe_migrate * m,struct xe_vm * vm,u32 * ofs) xe_migrate_prepare_vm() argument
419 xe_migrate_alloc(struct xe_tile * tile) xe_migrate_alloc() argument
428 xe_migrate_lock_prepare_vm(struct xe_tile * tile,struct xe_migrate * m,struct xe_vm * vm) xe_migrate_lock_prepare_vm() argument
464 struct xe_tile *tile = m->tile; xe_migrate_init() local
1157 xe_migrate_ccs_rw_copy(struct xe_tile * tile,struct xe_exec_queue * q,struct xe_bo * src_bo,enum xe_sriov_vf_ccs_rw_ctxs read_write) xe_migrate_ccs_rw_copy() argument
1363 struct xe_tile *tile = vram_bo->tile; xe_migrate_vram_copy_chunk() local
1704 write_pgtable(struct xe_tile * tile,struct xe_bb * bb,u64 ppgtt_ofs,const struct xe_vm_pgtable_update_op * pt_op,const struct xe_vm_pgtable_update * update,struct xe_migrate_pt_update * pt_update) write_pgtable() argument
1824 struct xe_tile *tile = m->tile; __xe_migrate_update_pgtables() local
2420 struct xe_tile *tile = m->tile; xe_migrate_access_memory() local
[all...]
/linux/tools/perf/pmu-events/arch/x86/knightslanding/
H A Dcache.json67 …ounts the loads retired that get the data from the other core in the same tile in M state (Precise…
135 …data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. …
145 …ata forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. …
155 … data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
165 …r responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
175 …esponses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
185 … responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
195 …refetch code read requests that accounts for responses which hit its own tile's L2 with data in E…
205 …refetch code read requests that accounts for responses which hit its own tile's L2 with data in F…
215 …refetch code read requests that accounts for responses which hit its own tile's L2 with data in M…
[all …]
/linux/drivers/gpu/ipu-v3/
H A Dipu-image-convert.c28 * tile (but taking care to pass the full frame stride length to
30 * to convert each tile back-to-back when possible (see note below
45 * reusable temporary tile buffer and then rotating with the 8x8
61 * With rotation or flipping, tile order changes between input and
96 /* dimensions of one tile */
106 /* start Y or packed offset of this tile */
108 /* offset from start to tile in U plane, for planar formats */
110 /* offset from start to tile in V plane, for planar formats */
126 struct ipu_image_tile tile[MAX_TILES]; member
185 /* next tile to process */
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv44.c31 nv44_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) in nv44_gr_tile() argument
44 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
45 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv44_gr_tile()
46 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
53 nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
54 nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit); in nv44_gr_tile()
55 nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
56 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); in nv44_gr_tile()
57 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); in nv44_gr_tile()
58 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); in nv44_gr_tile()
[all …]
/linux/drivers/gpu/drm/imagination/
H A Dpvr_rogue_cr_defs_client.h64 * X1 MacroTile boundary, left tile X for second column of macrotiles (16MT mode) - 32 pixels across
65 * tile
70 * X2 MacroTile boundary, left tile X for third(16MT) column of macrotiles - 32 pixels across tile
75 * X3 MacroTile boundary, left tile X for fourth column of macrotiles (16MT) - 32 pixels across tile
85 * X1 MacroTile boundary, ltop tile Y for second column of macrotiles (16MT mode) - 32 pixels tile
91 * X2 MacroTile boundary, top tile Y for third(16MT) column of macrotiles - 32 pixels tile height
96 * X3 MacroTile boundary, top tile Y for fourth column of macrotiles (16MT) - 32 pixels tile height
110 * Maximum Y tile address visible on screen, 32 pixel tile height, 16Kx16K max screen size
115 * Maximum X tile address visible on screen, 32 pixel tile width, 16Kx16K max screen size
/linux/drivers/hid/
H A Dhid-picolcd_fb.c22 * each. Each tile has 8x64 pixel, each data byte representing
23 * a 1-bit wide vertical line of the tile.
25 * The display can be updated at a tile granularity.
29 * | Tile 1 | Tile 1 | Tile 1 | Tile 1 |
31 * | Tile 2 | Tile 2 | Tile 2 | Tile 2 |
35 * | Tile 8 | Tile 8 | Tile 8 | Tile 8 |
89 /* Send a given tile to PicoLCD */
91 int chip, int tile) in picolcd_fb_send_tile() argument
114 hid_set_field(report1->field[0], 4, 0xb8 | tile); in picolcd_fb_send_tile()
127 tdata = vbitmap + (tile * 4 + chip) * 64; in picolcd_fb_send_tile()
[all …]
/linux/arch/arm/mach-versatile/
H A DKconfig129 bool "Integrator/CT926 (ARM926EJ-S) core tile"
135 bool "Integrator/CTB36 (ARM1136JF-S) core tile"
178 the ARM926EJ-S core tile, while on an ARMv6/v7 kernel, at least
180 core tile options should be enabled.
183 bool "Support ARM1136J(F)-S Tile"
187 Enable support for the ARM1136 tile fitted to the
191 bool "Support ARM1176JZ(F)-S Tile"
194 Enable support for the ARM1176 tile fitted to the
198 bool "Support Multicore Cortex-A9 Tile"
201 Enable support for the Cortex-A9MPCore tile fitted to the
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/linux/drivers/gpu/drm/xe/tests/
H A Dxe_bo.c25 static int ccs_test_migrate(struct xe_tile *tile, struct xe_bo *bo, in ccs_test_migrate() argument
47 fence = xe_migrate_clear(tile->migrate, bo, bo->ttm.resource, in ccs_test_migrate()
110 offset = xe_device_ccs_bytes(tile_to_xe(tile), xe_bo_size(bo)); in ccs_test_migrate()
127 static void ccs_test_run_tile(struct xe_device *xe, struct xe_tile *tile, in ccs_test_run_tile() argument
135 unsigned int bo_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile); in ccs_test_run_tile()
139 kunit_info(test, "Testing vram id %u\n", tile->id); in ccs_test_run_tile()
153 ret = ccs_test_migrate(tile, bo, false, 0ULL, 0xdeadbeefdeadbeefULL, in ccs_test_run_tile()
159 ret = ccs_test_migrate(tile, bo, false, 0xdeadbeefdeadbeefULL, in ccs_test_run_tile()
165 ret = ccs_test_migrate(tile, bo, true, 0ULL, 0ULL, test, exec); in ccs_test_run_tile()
175 struct xe_tile *tile; in ccs_test_run_device() local
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