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/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,sm8550-tcsr.yaml4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-tcsr.yaml#
7 title: Qualcomm TCSR Clock Controller on SM8550
14 Qualcomm TCSR clock control module provides the clocks, resets and
18 - include/dt-bindings/clock/qcom,eliza-tcsr.h
21 - include/dt-bindings/clock/qcom,sm8550-tcsr.h
22 - include/dt-bindings/clock/qcom,sm8650-tcsr.h
23 - include/dt-bindings/clock/qcom,sm8750-tcsr.h
30 - qcom,eliza-tcsr
32 - qcom,kaanapali-tcsr
33 - qcom,milos-tcsr
[all …]
H A Dqcom,glymur-tcsr.yaml4 $id: http://devicetree.org/schemas/clock/qcom,glymur-tcsr.yaml#
7 title: Qualcomm TCSR Clock Controller on Glymur
14 Qualcomm TCSR clock control module provides the clocks, resets and
18 - include/dt-bindings/clock/qcom,glymur-tcsr.h
24 - qcom,glymur-tcsr
25 - qcom,mahua-tcsr
66 const: qcom,glymur-tcsr
90 const: qcom,mahua-tcsr
121 compatible = "qcom,glymur-tcsr", "syscon";
/linux/Documentation/devicetree/bindings/hwlock/
H A Dqcom-hwspinlock.yaml21 - qcom,tcsr-mutex
24 - qcom,apq8084-tcsr-mutex
25 - qcom,ipq6018-tcsr-mutex
26 - qcom,msm8226-tcsr-mutex
27 - qcom,msm8994-tcsr-mutex
28 - const: qcom,tcsr-mutex
31 - qcom,msm8974-tcsr-mutex
32 - const: qcom,tcsr-mutex
51 compatible = "qcom,tcsr-mutex";
/linux/drivers/soc/qcom/
H A Dqcom_gsbi.c114 struct regmap *tcsr; member
118 { .compatible = "qcom,tcsr-ipq8064", .data = &config_ipq8064},
119 { .compatible = "qcom,tcsr-apq8064", .data = &config_apq8064},
120 { .compatible = "qcom,tcsr-msm8960", .data = &config_msm8960},
121 { .compatible = "qcom,tcsr-msm8660", .data = &config_msm8660},
145 /* get the tcsr node and setup the config and regmap */ in gsbi_probe()
146 gsbi->tcsr = syscon_regmap_lookup_by_phandle(node, "syscon-tcsr"); in gsbi_probe()
148 if (!IS_ERR(gsbi->tcsr)) { in gsbi_probe()
149 tcsr_node = of_parse_phandle(node, "syscon-tcsr", 0); in gsbi_probe()
155 dev_warn(&pdev->dev, "no matching TCSR\n"); in gsbi_probe()
[all …]
/linux/include/clocksource/
H A Dtimer-xilinx.h51 * @tcsr: The value of the TCSR register for this counter
59 u32 xilinx_timer_tlr_cycles(struct xilinx_timer_priv *priv, u32 tcsr,
66 * @tcsr: The value of TCSR for this counter
71 u32 tlr, u32 tcsr);
/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,qcs615-qmp-usb3dp-phy.yaml61 qcom,tcsr-reg:
65 - description: phandle to TCSR hardware block
68 description: Clamp and PHY mode register present in the TCSR
97 - qcom,tcsr-reg
157 qcom,tcsr-reg = <&tcsr 0xbff0 0xb24c>;
H A Dqcom,glymur-qmp-gen5x8-pcie-phy.yaml16 at runtime via a TCSR syscon register:
82 Reference to a register in the TCSR syscon that reports the link
91 - description: phandle of TCSR syscon
134 #include <dt-bindings/clock/qcom,glymur-tcsr.h>
143 <&tcsr TCSR_PCIE_3_CLKREF_EN>,
171 qcom,link-mode = <&tcsr 0x5000>;
H A Dqcom,qusb2-phy.yaml88 qcom,tcsr-syscon:
90 Phandle to TCSR syscon register region.
/linux/drivers/clk/qcom/
H A Dtcsrcc-sm8650.c13 #include <dt-bindings/clock/qcom,sm8650-tcsr.h>
150 { .compatible = "qcom,milos-tcsr" },
151 { .compatible = "qcom,sm8650-tcsr" },
158 if (of_device_is_compatible(pdev->dev.of_node, "qcom,milos-tcsr")) { in tcsr_cc_sm8650_probe()
H A DKconfig43 tristate "Eliza TCSR Clock Controller"
48 Support for the TCSR clock controller on Eliza devices.
105 tristate "Glymur TCSR Clock Controller"
110 Support for the TCSR clock controller on Glymur devices.
166 tristate "Kaanapali TCSR Clock Controller"
171 Support for the TCSR clock controller on Kaanapali devices.
289 tristate "X1E80100 TCSR Clock Controller"
294 Support for the TCSR clock controller on X1E80100 devices.
437 tristate "Hawi TCSR Clock Controller"
441 Support for the TCSR clock controller on Hawi devices.
[all …]
H A Dtcsrcc-sm8550.c14 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
169 { .compatible = "qcom,sar2130p-tcsr", .data = &tcsr_cc_sar2130p_desc },
170 { .compatible = "qcom,sm8550-tcsr", .data = &tcsr_cc_sm8550_desc },
H A Dtcsrcc-x1e80100.c12 #include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
257 { .compatible = "qcom,x1e80100-tcsr" },
287 MODULE_DESCRIPTION("QTI TCSR Clock Controller X1E80100 Driver");
H A Dtcsrcc-sm8750.c11 #include <dt-bindings/clock/qcom,sm8750-tcsr.h>
109 { .compatible = "qcom,sm8750-tcsr" },
H A Dtcsrcc-eliza.c11 #include <dt-bindings/clock/qcom,eliza-tcsr.h>
147 { .compatible = "qcom,eliza-tcsr" },
H A Dtcsrcc-glymur.c13 #include <dt-bindings/clock/qcom,glymur-tcsr.h>
274 { .compatible = "qcom,glymur-tcsr", .data = &tcsr_cc_glymur_data },
275 { .compatible = "qcom,mahua-tcsr", .data = &tcsr_cc_mahua_data },
H A Dlpasscc-sm6115.c44 .name = "lpass-tcsr",
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qusb2.c289 /* offset to PHY_CLK_SCHEME register in TCSR map */
453 * @tcsr: TCSR syscon register map
473 struct regmap *tcsr; member
831 * register in the TCSR so, if there's none, use the default in qusb2_phy_init()
842 if (qphy->tcsr) { in qusb2_phy_init()
843 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset, in qusb2_phy_init()
1053 qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node, in qusb2_phy_probe()
1054 "qcom,tcsr-syscon"); in qusb2_phy_probe()
1055 if (IS_ERR(qphy->tcsr)) { in qusb2_phy_probe()
1056 dev_dbg(dev, "failed to lookup TCSR regmap\n"); in qusb2_phy_probe()
[all …]
/linux/Documentation/arch/mips/
H A Dingenic-tcu.rst19 different clocks (pclk, ext, rtc), gated, and reclocked, through their TCSR register.
21 - The watchdog and OST hardware blocks also feature a TCSR register with the same
/linux/drivers/net/ethernet/marvell/mvpp2/
H A Dmvpp2_tai.c242 u32 tcsr; in mvpp22_tai_gettimex64() local
260 tcsr = readl(base + MVPP22_TAI_TCSR); in mvpp22_tai_gettimex64()
261 if (tcsr & TCSR_CAPTURE_1_VALID) { in mvpp22_tai_gettimex64()
264 } else if (tcsr & TCSR_CAPTURE_0_VALID) { in mvpp22_tai_gettimex64()
/linux/drivers/clk/ingenic/
H A Dtcu.c130 WARN_ONCE(ret < 0, "Unable to read TCSR %d", tcu_clk->idx); in ingenic_tcu_get_parent()
146 WARN_ONCE(ret < 0, "Unable to update TCSR %d", tcu_clk->idx); in ingenic_tcu_set_parent()
163 WARN_ONCE(ret < 0, "Unable to read TCSR %d", tcu_clk->idx); in ingenic_tcu_recalc_rate()
212 WARN_ONCE(ret < 0, "Unable to update TCSR %d", tcu_clk->idx); in ingenic_tcu_set_rate()
/linux/include/dt-bindings/clock/
H A Dqcom,sc8280xp-lpasscc.h14 /* LPASS TCSR */
H A Dqcom,sm8550-tcsr.h10 /* TCSR CC clocks */
H A Dqcom,sm8650-tcsr.h10 /* TCSR CC clocks */
H A Dqcom,x1e80100-tcsr.h9 /* TCSR CC clocks */
/linux/drivers/rtc/
H A Drtc-rs5c348.c101 udelay(62); /* Tcsr 62us */ in rs5c348_rtc_set_time()
133 udelay(62); /* Tcsr 62us */ in rs5c348_rtc_read_time()

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