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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstrInfo.td208 // out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
211 // out = (src1 > src0) ? 1 : 0
247 // Special case divide FMA with scale and flags (src0 = Quotient,
253 // Special case divide fixup and flags(src0 = Quotient, src1 =
272 // src0: vec4(src, 0, 0, mask)
349 // i32 or f32 src0
422 def AMDGPUfp_class : PatFrags<(ops node:$src0, node:$src1),
423 [(int_amdgcn_class node:$src0, node:$src1),
424 (AMDGPUfp_class_impl node:$src0, node:$src1)]>;
426 def AMDGPUfmed3 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
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H A DAMDGPUInstructions.td172 (ops node:$src0),
173 (op $src0)> {
178 (ops node:$src0, node:$src1),
179 (op $src0, $src1)> {
184 (ops node:$src0, node:$src1, node:$src2),
185 (op $src0, $src1, $src2)> {
190 (ops node:$src0),
191 (op $src0),
208 (ops node:$src0, node:$src1),
209 (op $src0, $src1),
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H A DSIInstructions.td69 let DisableEncoding = "$src0", Constraints = "$src0 = $vdst" in {
74 (ins VGPR_32:$src0, VGPR_32:$vsrc, InterpAttr:$attr,
77 [(set f32:$vdst, (int_amdgcn_interp_p2 f32:$src0, f32:$vsrc,
80 } // End DisableEncoding = "$src0", Constraints = "$src0 = $vdst"
124 (ins VSrc_b64:$src0, VSrc_b64:$src1, SSrc_b64:$src2), "", []> {
133 (ins VSrc_b64:$src0)> {
150 (ins i64imm:$src0)> {
162 def WQM : PseudoInstSI <(outs unknown:$vdst), (ins unknown:$src0)>;
166 def SOFT_WQM : PseudoInstSI <(outs unknown:$vdst), (ins unknown:$src0)>;
170 // the instruction that defines $src0 (which is run in Whole Wave Mode) doesn't
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H A DSOPInstructions.td73 bits<8> src0;
75 let Inst{7-0} = !if(ps.has_src0, src0, ?);
83 !if(tied_in, (ins SSrc_b32:$src0, SReg_32:$sdst_in),
84 (ins SSrc_b32:$src0)),
85 "$sdst, $src0", pattern> {
91 opName, (outs SReg_32:$sdst), (ins SReg_32:$src0),
92 "$sdst, $src0", pattern>;
96 opName, (outs), (ins SSrc_b32:$src0),
97 "$src0", pattern> {
103 opName, (outs), (ins SReg_32:$sdst, SSrc_b32:$src0),
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H A DEvergreenInstructions.td348 // [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))]
352 // Src0 = Input
366 [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))],
371 [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))],
412 [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))],
464 (fcopysign f32:$src0, f32:$src1),
465 (BFI_INT_eg (MOV_IMM_I32 (i32 0x7fffffff)), $src0, $src1)
469 (fcopysign f32:$src0, f64:$src1),
470 (BFI_INT_eg (MOV_IMM_I32 (i32 0x7fffffff)), $src0,
475 (fcopysign f64:$src0, f64:$src1),
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H A DVOPInstructions.td226 bits<9> src0;
239 let Inst{40-32} = !if(P.HasSrc0, src0, 0);
318 // NB: For V_INTERP* opcodes, src0 is encoded as src1 and vice versa
324 let Inst{8} = 0; // No modifiers for src0
334 let Inst{49-41} = src0;
347 let Inst{49-41} = src0;
357 bits<9> src0;
368 let Inst{40-32} = !if(P.HasSrc0, src0, 0);
380 bits<9> src0;
390 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // neg_hi src0
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H A DVOP2Instructions.td15 bits<9> src0;
18 let Inst{8-0} = !if(P.HasSrc0, src0, 0);
27 bits<9> src0;
31 let Inst{8-0} = !if(P.HasSrc0, src0, 0);
135 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
136 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))),
138 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
282 (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
345 (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
353 ps.Pfl.Src0RC32:$src0, ps.Pfl.Src1RC32:$src1, Clamp:$clamp),
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H A DVOP3Instructions.td40 let Asm64 = "$vdst, $sdst, $src0, $src1, $src2$clamp";
65 let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
73 let Ins64 = (ins InterpSlot:$src0,
77 let Asm64 = "$vdst, $src0, $attr$attrchan$clamp$omod";
94 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
98 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
103 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
183 // result = src0 * src1 + src2
190 // result = src0 * src1 + src2
361 (VOP3Mods f32:$src0, i32:$src0_modifiers),
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H A DR600ExpandSpecialInstrs.cpp111 MI.getOperand(1).getReg(), // src0 in runOnMachineFunction()
146 Register Src0 = in runOnMachineFunction() local
147 BMI->getOperand(TII->getOperandIdx(Opcode, R600::OpName::src0)) in runOnMachineFunction()
152 (void) Src0; in runOnMachineFunction()
154 if ((TRI.getEncodingValue(Src0) & 0xff) < 127 && in runOnMachineFunction()
156 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1)); in runOnMachineFunction()
198 Register Src0 = in runOnMachineFunction() local
199 MI.getOperand(TII->getOperandIdx(MI, R600::OpName::src0)).getReg(); in runOnMachineFunction()
211 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
217 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
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H A DR600Instructions.td105 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
110 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
136 [(set R600_Reg32:$dst, (node R600_Reg32:$src0))], itin
147 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
153 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
175 [(set R600_Reg32:$dst, (node R600_Reg32:$src0,
187 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
193 "$src0_neg$src0$src0_rel, "
372 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
373 "INTERP_PAIR_XY $src0
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H A DVOP3PInstructions.td33 (ins FP16InputMods:$src0_modifiers, VCSrc_f16:$src0,
37 (ins FPVRegInputMods:$src0_modifiers, VGPRSrc_32:$src0,
130 (pat (v2i16 (VOP3PMods v2i16:$src0, i32:$src0_modifiers)),
132 (inst $src0_modifiers, $src0, $src1_modifiers, $src1, DSTCLAMP.ENABLE)
151 (f32 (fma_like (f32 (VOP3PMadMixModsExt f16:$src0, i32:$src0_mods)),
154 (mix_inst $src0_mods, $src0, $src1_mods, $src1, $src2_mods, $src2,
157 (f32 (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_mods)),
160 (mix_inst $src0_mods, $src0, $src1_mods, $src1, $src2_mods, $src2,
163 (f32 (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_mods)),
166 (mix_inst $src0_mods, $src0, $src1_mods, $src1, $src2_mods, $src2,
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H A DAMDGPUGISel.td309 (dst_vt (node (src0_vt SReg_32:$src0), (src1_vt SReg_32:$src1))),
310 (inst src0_vt:$src0, src1_vt:$src1)
319 (dst_vt (node (src0_vt (sd_vsrc0 src0_vt:$src0)), (src1_vt VGPR_32:$src1))),
320 (inst src0_vt:$src0, src1_vt:$src1)
329 (dst_vt (node (src1_vt VGPR_32:$src1), (src0_vt (sd_vsrc0 src0_vt:$src0)))),
330 (inst src0_vt:$src0, src1_vt:$src1)
339 (dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))),
340 (inst src0_vt:$src0, src1_vt:$src1)
349 (dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))),
350 (inst src0_vt:$src1, src1_vt:$src0)
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H A DSIShrinkInstructions.cpp93 int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0); in foldImmediates()
95 // Try to fold Src0 in foldImmediates()
96 MachineOperand &Src0 = MI.getOperand(Src0Idx); in foldImmediates() local
97 if (Src0.isReg()) { in foldImmediates()
98 Register Reg = Src0.getReg(); in foldImmediates()
107 Src0.ChangeToImmediate(MovSrc.getImm()); in foldImmediates()
110 Src0.ChangeToFrameIndex(MovSrc.getIndex()); in foldImmediates()
113 Src0.ChangeToGA(MovSrc.getGlobal(), MovSrc.getOffset(), in foldImmediates()
129 // We have failed to fold src0, so commute the instruction and try again. in foldImmediates()
242 // cmpk requires src0 to be a register in shrinkScalarCompare()
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H A DGCNVOPDUtils.cpp83 const MachineOperand &Src0 = MI.getOperand(VOPD::Component::SRC0); in checkVOPDRegConstraints() local
84 if (Src0.isReg()) { in checkVOPDRegConstraints()
85 if (!TRI->isVectorRegister(MRI, Src0.getReg())) { in checkVOPDRegConstraints()
86 if (!is_contained(UniqueScalarRegs, Src0.getReg())) in checkVOPDRegConstraints()
87 UniqueScalarRegs.push_back(Src0.getReg()); in checkVOPDRegConstraints()
90 if (!TII.isInlineConstant(MI, VOPD::Component::SRC0)) in checkVOPDRegConstraints()
91 addLiteral(Src0); in checkVOPDRegConstraints()
H A DSIInstrInfo.td667 (ops node:$src1, node:$src0),
668 (srl $src0, $src1)
672 (ops node:$src1, node:$src0),
673 (sra $src0, $src1)
677 (ops node:$src1, node:$src0),
678 (shl $src0, $src1)
682 (ops node:$src0, node:$src1),
683 (add (ctpop $src0), $src1)
687 (ops node:$src0, node:$src1),
688 (not (xor $src0, $src1))
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H A DEXPInstructions.td16 ExpSrc0:$src0, ExpSrc1:$src1, ExpSrc2:$src2, ExpSrc3:$src3,
41 : EXPCommon<0, ps.done, "exp$tgt $src0, $src1, $src2, $src3"
49 : EXPCommon<ps.row, ps.done, name#"$tgt $src0, $src1, $src2, $src3"
142 (vt ExpSrc0:$src0), (vt ExpSrc1:$src1),
145 (Inst timm:$tgt, ExpSrc0:$src0, ExpSrc1:$src1,
151 (vt ExpSrc0:$src0), (vt ExpSrc1:$src1),
154 (Inst timm:$tgt, ExpSrc0:$src0, ExpSrc1:$src1,
160 (vt ExpSrc0:$src0), (vt ExpSrc1:$src1),
162 (Inst timm:$tgt, ExpSrc0:$src0, ExpSrc1:$src1,
H A DSIPeepholeSDWA.cpp316 if (TII->getNamedOperand(*MI, AMDGPU::OpName::src0) == SrcOp) { in getSrcMods()
386 MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in convertToSDWA()
392 // If this is not src0 then it could be src1 in convertToSDWA()
582 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
583 auto Imm = foldToImm(*Src0); in matchSDWAOperand()
622 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
623 auto Imm = foldToImm(*Src0); in matchSDWAOperand()
689 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
692 if (!Src0->isReg() || Src0->getReg().isPhysical() || in matchSDWAOperand()
697 Src0, Dst, SrcSel, false, false, Opcode != AMDGPU::V_BFE_U32_e64); in matchSDWAOperand()
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H A DGCNDPPCombine.cpp8 // The pass combines V_MOV_B32_dpp instruction with its VALU uses as a DPP src0
290 auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0); in createDPPInst() local
291 assert(Src0); in createDPPInst()
293 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src0)) { in createDPPInst()
294 LLVM_DEBUG(dbgs() << " failed: src0 is illegal\n"); in createDPPInst()
298 DPPInst.add(*Src0); in createDPPInst()
318 // requirements are the same as for src0. We check src0 instead because in createDPPInst()
323 "Src0 and Src1 operands should have the same size"); in createDPPInst()
565 auto *SrcOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0); in combineDPPMov()
684 auto *Src0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0); in combineDPPMov() local
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H A DVOP1Instructions.td16 bits<9> src0;
18 let Inst{8-0} = !if(P.HasSrc0, src0{8-0}, ?);
111 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods P.Src0VT:$src0, i32:$src0_modifiers))))],
113 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3OMods P.Src0VT:$src0,
115 [(set P.DstVT:$vdst, (node (P.Src0VT P.Src0RC32:$src0)))]
181 let Ins64 = (ins Src0RC64:$src0, Clamp:$clamp, omod:$omod);
182 let InsVOP3Base = (ins Src0VOP3DPP:$src0, Clamp:$clamp, omod:$omod);
183 let AsmVOP3Base = "$vdst, $src0$clamp$omod";
192 let Ins64 = (ins Src0RC64:$src0, Clamp:$clamp, omod:$omod);
193 let InsVOP3Base = (ins Src0VOP3DPP:$src0, Clamp:$clamp, omod:$omod);
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H A DAMDGPUInstCombineIntrinsic.cpp45 static APFloat fmed3AMDGCN(const APFloat &Src0, const APFloat &Src1, in fmed3AMDGCN() argument
47 APFloat Max3 = maxnum(maxnum(Src0, Src1), Src2); in fmed3AMDGCN()
49 APFloat::cmpResult Cmp0 = Max3.compare(Src0); in fmed3AMDGCN()
57 return maxnum(Src0, Src2); in fmed3AMDGCN()
59 return maxnum(Src0, Src1); in fmed3AMDGCN()
601 Value *Src0 = II.getArgOperand(0); in instCombineIntrinsic() local
606 II.getModule(), Intrinsic::is_fpclass, Src0->getType())); in instCombineIntrinsic()
615 if (isa<PoisonValue>(Src0) || isa<PoisonValue>(Src1)) in instCombineIntrinsic()
623 if (IC.getSimplifyQuery().isUndefValue(Src0)) { in instCombineIntrinsic()
631 Value *Src0 = II.getArgOperand(0); in instCombineIntrinsic() local
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H A DVINTERPInstructions.td16 bits<9> src0;
34 let Inst{40-32} = src0;
77 let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
95 let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
130 (VINTERPMods f32:$src0, i32:$src0_modifiers),
133 (inst $src0_modifiers, $src0,
149 (pat[0] f32:$src0, i32:$src0_modifiers),
153 (inst $src0_modifiers, $src0,
H A DSIOptimizeExecMasking.cpp536 MachineOperand &Src0 = SaveExecInst->getOperand(1); in optimizeExecSequence() local
541 if (Src0.isReg() && Src0.getReg() == CopyFromExec) { in optimizeExecSequence()
547 OtherOp = &Src0; in optimizeExecSequence()
583 MachineOperand *Src0 = TII->getNamedOperand(VCmp, AMDGPU::OpName::src0); in optimizeVCMPSaveExecSequence() local
609 Builder.add(*Src0); in optimizeVCMPSaveExecSequence()
617 if (Src0->isReg()) in optimizeVCMPSaveExecSequence()
618 MRI->clearKillFlags(Src0->getReg()); in optimizeVCMPSaveExecSequence()
653 MachineOperand *SaveExecSrc0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in tryRecordVCmpxAndSaveexecSequence()
681 MachineOperand *Src0 = TII->getNamedOperand(*VCmp, AMDGPU::OpName::src0); in tryRecordVCmpxAndSaveexecSequence() local
682 if (Src0->isReg() && TRI->isSGPRReg(*MRI, Src0->getReg()) && in tryRecordVCmpxAndSaveexecSequence()
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/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Damxintrin.h138 /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in src0 with
149 /// \param src0
153 #define _tile_dpbssd(dst, src0, src1) \ argument
154 __builtin_ia32_tdpbssd((dst), (src0), (src1))
157 /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in src0 with
168 /// \param src0
172 #define _tile_dpbsud(dst, src0, src1) \ argument
173 __builtin_ia32_tdpbsud((dst), (src0), (src1))
176 /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in src0 with
187 /// \param src0
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H A Damxcomplexintrin.h124 /// element in input tiles src0 and src1 is interpreted as a complex number with
134 /// \param src0
139 static void __tile_cmmimfp16ps(__tile1024i *dst, __tile1024i src0, in __tile_cmmimfp16ps() argument
141 dst->tile = _tile_cmmimfp16ps_internal(src0.row, src1.col, src0.col, in __tile_cmmimfp16ps()
142 dst->tile, src0.tile, src1.tile); in __tile_cmmimfp16ps()
147 /// element in input tiles src0 and src1 is interpreted as a complex number with
157 /// \param src0
162 static void __tile_cmmrlfp16ps(__tile1024i *dst, __tile1024i src0, in __tile_cmmrlfp16ps() argument
164 dst->tile = _tile_cmmrlfp16ps_internal(src0.row, src1.col, src0.col, in __tile_cmmrlfp16ps()
165 dst->tile, src0.tile, src1.tile); in __tile_cmmrlfp16ps()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h1142 /// Build and insert `Res = G_INSERT_SUBVECTOR Src0, Src1, Idx`.
1145 /// \pre \p Res, \p Src0, and \p Src1 must be generic virtual registers with
1149 MachineInstrBuilder buildInsertSubvector(const DstOp &Res, const SrcOp &Src0,
1673 MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0,
1676 return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1690 MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0,
1693 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1706 MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
1709 return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1712 MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0,
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