Lines Matching full:src0
15 bits<9> src0;
18 let Inst{8-0} = !if(P.HasSrc0, src0, 0);
27 bits<9> src0;
31 let Inst{8-0} = !if(P.HasSrc0, src0, 0);
135 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
136 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))),
138 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
282 (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
345 (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
353 ps.Pfl.Src0RC32:$src0, ps.Pfl.Src1RC32:$src1, Clamp:$clamp),
373 (ins VSrc_f32_Deferred:$src0, VGPR_32:$src1, ImmOpType:$imm),
374 (ins VSrc_f16_Deferred:$src0, VGPR_32:$src1, ImmOpType:$imm));
380 field string Asm32 = "$vdst, $src0, $src1, $imm";
392 let Ins32 = (ins VSrcFake16_f16_Lo128_Deferred:$src0, VGPR_32_Lo128:$src1, ImmOpType:$imm);
399 (ins VSrc_f32_Deferred:$src0, ImmOpType:$imm, VGPR_32:$src1),
400 (ins VSrc_f16_Deferred:$src0, ImmOpType:$imm, VGPR_32:$src1));
405 field string Asm32 = "$vdst, $src0, $imm, $src1";
417 let Ins32 = (ins VSrcFake16_f16_Lo128_Deferred:$src0, ImmOpType:$imm, VGPR_32_Lo128:$src1);
424 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, getVregSrcForVT<Src2VT>.ret:$src2);
428 let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
447 let InsDPP8 = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
451 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
488 …let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 1/*IsFake1…
495 let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
500 let InsDPP8 = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
539 let Asm64 = "$vdst, $src0, $src1$clamp";
544 let Asm32 = "$vdst, vcc, $src0, $src1";
545 let AsmVOP3Base = "$vdst, $sdst, $src0, $src1$clamp";
548 let AsmDPP = "$vdst, vcc, $src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
549 let AsmDPP8 = "$vdst, vcc, $src0, $src1 $dpp8$fi";
552 Src0DPP:$src0,
558 Src0DPP:$src0,
571 let Asm32 = "$vdst, vcc, $src0, $src1, vcc";
574 let AsmDPP = "$vdst, vcc, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
575 let AsmDPP8 = "$vdst, vcc, $src0, $src1, vcc $dpp8$fi";
579 let AsmVOP3Base = "$vdst, $sdst, $src0, $src1, $src2$clamp";
585 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
587 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
594 Src0DPP:$src0,
600 Src0DPP:$src0,
613 let Asm32 = "$vdst, $src0, $src1";
617 let AsmDPP8 = "$vdst, $src0, $src1, vcc $dpp8$fi";
626 let Ins32 = (ins VSrc_f32:$src0, Src1RC32:$src1);
638 let InsSDWA = (ins FP32SDWAInputMods:$src0_modifiers, SDWASrc_f32:$src0,
645 FPVRegInputMods:$src0_modifiers, Src0DPP:$src0,
651 FPVRegInputMods:$src0_modifiers, Src0DPP:$src0,
681 let Ins32 = (ins VRegOrLdsSrc_32:$src0, SCSrc_b32:$src1);
683 let Asm32 = " $vdst, $src0, $src1";
697 let Ins32 = (ins SCSrc_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in);
699 let Asm32 = " $vdst, $src0, $src1";
792 def : GCNPat<(vt (int_amdgcn_readlane vt:$src0, i32:$src1)),
793 (V_READLANE_B32 VRegOrLdsSrc_32:$src0, SCSrc_b32:$src1)
796 def : GCNPat<(vt (int_amdgcn_writelane vt:$src0, i32:$src1, vt:$src2)),
797 (V_WRITELANE_B32 SCSrc_b32:$src0, SCSrc_b32:$src1, VGPR_32:$src2)
838 (DivergentBinFrag<Op> Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),
840 (Inst $src0, $src1),
841 (Inst $src1, $src0)
847 (DivergentBinFrag<Op> Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),
849 (Inst $src0, $src1, 0),
850 (Inst $src1, $src0, 0)
873 (DivergentBinFrag<Op> i64:$src0, i64:$src1),
876 (i32 (EXTRACT_SUBREG $src0, sub0)),
880 (i32 (EXTRACT_SUBREG $src0, sub1)),
892 (i64 (Op i32:$src0, i32:$src1)),
894 (InstLo $src0, $src1), sub0,
895 (InstHi $src0, $src1), sub1)
951 (P.DstVT (op (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
953 (inst $src0_modifiers, $src0,
1034 (i32 (DivergentUnaryFrag<not> (xor_oneuse i32:$src0, i32:$src1))),
1035 (i32 (V_XNOR_B32_e64 $src0, $src1))
1039 (i32 (DivergentBinFrag<xor_oneuse> (not i32:$src0), i32:$src1)),
1040 (i32 (V_XNOR_B32_e64 $src0, $src1))
1044 (i64 (DivergentUnaryFrag<not> (xor_oneuse i64:$src0, i64:$src1))),
1046 (i32 (EXTRACT_SUBREG $src0, sub0)),
1049 (i32 (EXTRACT_SUBREG $src0, sub1)),
1054 (i64 (DivergentBinFrag<xor_oneuse> (not i64:$src0), i64:$src1)),
1056 (i32 (EXTRACT_SUBREG $src0, sub0)),
1059 (i32 (EXTRACT_SUBREG $src0, sub1)),
1106 (f32 (AMDGPUfdot2 v2f16:$src0, v2f16:$src1, f32:$src2, (i1 DSTCLAMP.NONE))),
1107 (f32 (V_DOT2C_F32_F16_e32 $src0, $src1, $src2))
1112 (i32 (int_amdgcn_sdot4 i32:$src0, i32:$src1, i32:$src2, (i1 DSTCLAMP.NONE))),
1113 (i32 (V_DOT4C_I32_I8_e32 $src0, $src1, $src2))
1118 (i32 (int_amdgcn_sdot2 v2i16:$src0, v2i16:$src1, i32:$src2, (i1 DSTCLAMP.NONE))),
1119 (i32 (V_DOT2C_I32_I16_e32 $src0, $src1, $src2))
1124 (i32 (int_amdgcn_sdot8 i32:$src0, i32:$src1, i32:$src2, (i1 DSTCLAMP.NONE))),
1125 (i32 (V_DOT8C_I32_I4_e32 $src0, $src1, $src2))
1147 (i32 (zext (op i16:$src0, i16:$src1))),
1148 (inst VSrc_b16:$src0, VSrc_b16:$src1)
1152 (i64 (zext (op i16:$src0, i16:$src1))),
1154 (inst $src0, $src1), sub0,
1161 (V_CNDMASK_B32_e64 (i32 0/*src0mod*/), (i32 0/*src0*/),
1168 (and vt:$src0, vt:$src1),
1169 (V_AND_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
1173 (or vt:$src0, vt:$src1),
1174 (V_OR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
1178 (xor vt:$src0, vt:$src1),
1179 (V_XOR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
1189 (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)),
1190 (V_SUB_U16_e64 VSrc_b16:$src0, NegSubInlineIntConst16:$src1)
1194 (i32 (zext (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)))),
1195 (V_SUB_U16_e64 VSrc_b16:$src0, NegSubInlineIntConst16:$src1)
1218 (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
2162 let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in {
2164 } // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in)
2439 name#" $dst, $src0, $src1",
2441 (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0, 0),
2442 (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0))