| /freebsd/sys/arm/qualcomm/ |
| H A D | qcom_cpu_kpssv2.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
56 * Since DELAY() hangs this early, we need some way to
57 * delay things to settle.
60 loop_delay(int usec) in loop_delay() argument
62 int lcount = usec * 100000; in loop_delay()
70 * and shared L2 cache power-on.
91 * Walk the qcom,acc and next-level-cache entries to find their in qcom_cpu_kpssv2_regulator_start()
96 * The next-level-cache actually is a phandle through to a qcom,saw in qcom_cpu_kpssv2_regulator_start()
105 sret = OF_getencprop(node, "next-level-cache", (void *) &l2_phandle, in qcom_cpu_kpssv2_regulator_start()
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| /freebsd/sys/contrib/device-tree/Bindings/input/touchscreen/ |
| H A D | ads7846.txt | 7 Documentation/devicetree/bindings/spi/spi-bus.txt
23 vcc-supply A regulator node for the supply voltage.
28 ti,vref-delay-usecs vref supply delay in usecs, 0 for
30 ti,vref-mv The VREF voltage, in millivolts (u16).
33 ti,keep-vref-on set to keep vref on for differential
35 ti,settle-delay-usec Settling time of the analog signals;
37 on the X/Y drivers. If set to non-zero,
40 ~150 uSec with 0.01uF caps (u16).
41 ti,penirq-recheck-delay-usecs If set to non-zero, after samples are
42 taken this delay is applied and penirq
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| H A D | ti,ads7843.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Stein <alexander.stein@ew.tq-group.com>
11 - Dmitry Torokhov <dmitry.torokhov@gmail.com>
12 - Marek Vasut <marex@denx.de>
21 - ti,ads7843
22 - ti,ads7845
23 - ti,ads7846
24 - ti,ads7873
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| /freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
| H A D | omap3-devkit8000-lcd-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "omap3-devkit8000-common.dtsi"
15 compatible = "panel-dpi";
18 enable-gpios = <&twl_gpio 18 GPIO_ACTIVE_HIGH>;
22 remote-endpoint = <&dpi_lcd_out>;
30 #address-cells = <1>;
31 #size-cells = <0>;
34 remote-endpoint = <&lcd_in>;
35 data-lines = <24>;
41 regulator-min-microvolt = <1800000>;
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| /freebsd/sys/contrib/device-tree/src/arm/nxp/imx/ |
| H A D | imx7d-pico-hobbit.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 #include "imx7d-pico.dtsi"
8 model = "TechNexion PICO-IMX7D Board using Hobbit baseboard";
9 compatible = "technexion,imx7d-pico-hobbit", "fsl,imx7d";
12 compatible = "gpio-leds";
13 pinctrl-names = "default";
14 pinctrl-0 = <&pinctrl_gpio_leds>;
17 label = "gpio-led";
23 compatible = "simple-audio-card";
24 simple-audio-card,name = "imx7-sgtl5000";
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| /freebsd/sys/dev/ath/ath_hal/ar5312/ |
| H A D | ar5312_reset.c | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
33 /* Additional Time delay to wait after activiting the Base band */
34 #define BASE_ACTIVATE_DELAY 100 /* 100 usec */
35 #define PLL_SETTLE_DELAY 300 /* 300 usec */
62 #define V(r, c) (ia)->data[((r)*(ia)->cols) + (c)] in write_common()
66 for (i = 0; i < ia->rows; i++) { in write_common()
110 HALASSERT(ah->ah_magic == AR5212_MAGIC); in ar5312Reset()
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| /freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
| H A D | imx8mn-var-som.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright 2019-2020 Variscite Ltd.
11 model = "Variscite VAR-SOM-MX8MN module";
12 compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";
15 stdout-path = &uart4;
23 reg_eth_phy: regulator-et
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| H A D | imx8mm-var-som.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 model = "Variscite VAR-SOM-MX8MM module";
13 stdout-path = &uart4;
21 reg_eth_phy: regulator-eth-phy {
22 compatible = "regulator-fixed";
23 pinctrl-names = "default";
24 pinctrl-0 = <&pinctrl_reg_eth_phy>;
25 regulator-name = "eth_phy_pwr";
26 regulator-min-microvolt = <3300000>;
27 regulator-max-microvolt = <3300000>;
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| /freebsd/sys/dev/ath/ath_hal/ar5212/ |
| H A D | ar5212_reset.c | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
31 /* Additional Time delay to wait after activiting the Base band */
32 #define BASE_ACTIVATE_DELAY 100 /* 100 usec */
33 #define PLL_SETTLE_DELAY 300 /* 300 usec */
78 #define V(r, c) (ia)->data[((r)*(ia)->cols) + (c)] in write_common()
82 for (r = 0; r < ia->rows; r++) { in write_common()
141 HALASSERT(ah->ah_magic == AR5212_MAGIC); in ar5212Reset()
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| /freebsd/sys/dev/ath/ath_hal/ar5416/ |
| H A D | ar5416_reset.c | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
33 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK)
37 /* Additional Time delay to wait after activiting the Base band */
38 #define BASE_ACTIVATE_DELAY 100 /* 100 usec */
39 #define PLL_SETTLE_DELAY 300 /* 300 usec */
122 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); in ar5416Reset()
144 * Don't do this for the AR9285 - it breaks RX for single in ar5416Reset()
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| /freebsd/contrib/ntp/ntpd/ |
| H A D | refclock_datum.c | 2 ** refclock_datum - clock driver for the Datum Programmable Time Server
50 ** byte 0: | - - - - | H D |
54 ** byte 2: | - - | T H | U H |
56 ** byte 3: | - | T M | U M |
58 ** byte 4: | - | T S | U S |
62 ** byte 6: | m S | - - - - |
67 ** "-" means don't care
95 ** correct time by less than +- 30 minutes. The default is for GMT to not
96 ** defined. If you really want to force GMT without the funny +- 30 minute
107 #define PRECISION (-10) /* precision assumed 1/1024 ms */
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| /freebsd/sys/contrib/dev/ath/ath_hal/ar9300/ |
| H A D | ar9300_reset.c | 34 /* Additional Time delay to wait after activiting the Base band */
35 #define BASE_ACTIVATE_DELAY 100 /* usec */
36 #define RTC_PLL_SETTLE_DELAY 100 /* usec */
121 ahp->ah_hwp = HAL_TRUE_CHIP; in ar9300_attach_hw_platform()
126 * This includes: +USEC, TX/RX latency,
133 u_int32_t tx_lat, rx_lat, usec, slot, regval, eifs; in ar9300_set_ifs_timing() local
143 usec = SM(AR_USEC_HALF_FAST_CLOCK, AR_USEC_USEC); in ar9300_set_ifs_timing()
147 usec = SM(AR_USEC_HALF, AR_USEC_USEC); in ar9300_set_ifs_timing()
155 usec = SM(AR_USEC_QUARTER_FAST_CLOCK, AR_USEC_USEC); in ar9300_set_ifs_timing()
159 usec = SM(AR_USEC_QUARTER, AR_USEC_USEC); in ar9300_set_ifs_timing()
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| H A D | ar9300reg.h | 32 /* MAC Control Register - only write values of 1 have effect */
37 #define AR_CR_SWI 0x00000040 // One-shot software interrupt
47 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 // AP/adhoc indication (0-AP 1-Adhoc)
55 /* Rx DMA Data Buffer Pointer Threshold - High and Low Priority register */
124 #define AR_RXCFG_ZLFDMA 0x00000010 // Enable DMA of zero-length frame
211 #define AR_GTTM_USEC 0x00000001 // usec strobe
214 #define AR_GTTM_CST_USEC 0x00000008 // CST usec strobe
238 #define AR_ISR_HP_RXOK 0x00000001 // At least one frame rx on high-priority queue sans errors
239 #define AR_ISR_LP_RXOK 0x00000002 // At least one frame rx on low-priority queue sans errors
249 #define AR_ISR_MIB 0x00001000 // MIB interrupt - see MIBC
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| /freebsd/sys/dev/ath/ath_hal/ar5211/ |
| H A D | ar5211_reset.c | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2006 Atheros Communications, Inc.
50 { 1, 0x46, 96 }, /* 2312 -19 */
51 { 1, 0x46, 97 }, /* 2317 -18 */
52 { 1, 0x46, 98 }, /* 2322 -17 */
53 { 1, 0x46, 99 }, /* 2327 -16 */
54 { 1, 0x46, 100 }, /* 2332 -15 */
55 { 1, 0x46, 101 }, /* 2337 -14 */
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| /freebsd/sys/netinet/tcp_stacks/ |
| H A D | rack.c | 1 /*-
2 * Copyright (c) 2016-2020 Netflix, Inc.
162 * - Matt Mathis's Rate Halving which slowly drops
165 * - Yuchung Cheng's RACK TCP (for which its named) that
168 * - Reorder Detection of RFC4737 and the Tail-Loss probe draft
186 * TCP output is also over-written with a new version since it
191 static int32_t rack_tlp_limit = 2; /* No more than 2 TLPs w-out new data */
194 static int32_t rack_reorder_fade = 60000000; /* 0 - never fade, def 60,000,000
195 * - 6
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| /freebsd/sys/dev/ice/ |
| H A D | ice_lib.c | 1 /* SPDX-License-Identifier: BSD-3-Clause */
267 * ice_map_bar - Map PCIe BAR memory in ice_map_bar()
278 if (bar->res != NULL) { in ice_map_bar()
283 bar->rid = PCIR_BAR(bar_num);
284 bar->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &bar->rid,
286 if (!bar->re
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| /freebsd/sys/dev/qlnx/qlnxe/ |
| H A D | reg_addr.h | 2 * Copyright (c) 2017-2018 Cavium, Inc.
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
116 … (0x1<<9) // Fast back-to-back transaction ena…
128 … (0x1<<23) // Fast back-to-back capable. Not ap…
145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
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|