Home
last modified time | relevance | path

Searched full:scr (Results 1 – 25 of 138) sorted by relevance

123456

/linux/drivers/media/tuners/
H A Dtda827x.c337 u8 scr; member
343 { .lomax = 56875000, .svco = 3, .spd = 4, .scr = 0, .sbs = 0, .gc3 = 1},
344 { .lomax = 67250000, .svco = 0, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 1},
345 { .lomax = 81250000, .svco = 1, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 1},
346 { .lomax = 97500000, .svco = 2, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 1},
347 { .lomax = 113750000, .svco = 3, .spd = 3, .scr = 0, .sbs = 1, .gc3 = 1},
348 { .lomax = 134500000, .svco = 0, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
349 { .lomax = 154000000, .svco = 1, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
350 { .lomax = 162500000, .svco = 1, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
351 { .lomax = 183000000, .svco = 2, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
[all …]
/linux/sound/soc/mxs/
H A Dmxs-saif.c80 u32 scr; in mxs_saif_set_clk() local
101 scr = __raw_readl(master_saif->base + SAIF_CTRL); in mxs_saif_set_clk()
102 scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE; in mxs_saif_set_clk()
103 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; in mxs_saif_set_clk()
126 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; in mxs_saif_set_clk()
133 scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE; in mxs_saif_set_clk()
143 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; in mxs_saif_set_clk()
154 __raw_writel(scr, master_saif->base + SAIF_CTRL); in mxs_saif_set_clk()
166 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4); in mxs_saif_set_clk()
169 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); in mxs_saif_set_clk()
[all …]
/linux/Documentation/arch/s390/
H A Dconfig3270.sh22 SCR=$ROOT/tmp/mkdev3270
23 SCRTMP=$SCR.a
37 echo "#!/bin/sh" > $SCR || exit 1
38 echo " " >> $SCR
39 echo "# Script built by /sbin/config3270" >> $SCR
41 echo rm -rf "$D/$SUBD/*" >> $SCR
46 echo mkdir -p $D/$SUBD >> $SCR
56 echo mknod $D/$TUB c $fsmaj 0 >> $SCR
57 echo chmod 666 $D/$TUB >> $SCR
61 echo mknod $D/$TUB$devno c $fsmaj $min >> $SCR
[all …]
/linux/net/netfilter/
H A Dnf_conntrack_proto_dccp.c92 #define sCR CT_DCCP_CLOSEREQ macro
141 * sCR -> sIG Ignore, conntrack might be out of sync
145 * sNO, sRQ, sRS, sPO. sOP, sCR, sCG, sTW, */
155 * sCR -> sIG Ignore, might be response to ignored Request
160 * sNO, sRQ, sRS, sPO, sOP, sCR, sCG, sTW */
170 * sCR -> sCR Ack in CLOSEREQ MAY be processed (8.3.)
174 * sNO, sRQ, sRS, sPO, sOP, sCR, sCG, sTW */
175 sIV, sIV, sPO, sPO, sOP, sCR, sCG, sIV
184 * sCR -> sCR Data in CLOSEREQ MAY be processed (8.3.)
188 * sNO, sRQ, sRS, sPO, sOP, sCR, sCG, sTW */
[all …]
/linux/arch/loongarch/kernel/
H A Dlbt.S27 movscr2gr t1, $scr0 # save scr
46 ldptr.d t1, a0, THREAD_SCR0 # restore scr
62 * Load scr/eflag with zero.
75 * a0: scr
79 movscr2gr t1, $scr0 # save scr
95 * a0: scr
99 EX ld.d t1, a0, (0 * SCR_REG_WIDTH) # restore scr
/linux/net/netfilter/ipvs/
H A Dip_vs_proto_sctp.c276 #define sCR IP_VS_SCTP_S_COOKIE_REPLIED macro
290 /* sNO, sI1, sIN, sCS, sCR, sCW, sCO, sCE, sES, sSS, sSR, sSA, sRJ, sCL*/
291 /* d */{sES, sI1, sIN, sCS, sCR, sCW, sCO, sCE, sES, sSS, sSR, sSA, sRJ, sCL},
292 /* i */{sI1, sIN, sIN, sCS, sCR, sCW, sCO, sCE, sES, sSS, sSR, sSA, sIN, sIN},
293 /* i_a */{sCW, sCW, sCW, sCS, sCR, sCO, sCO, sCE, sES, sSS, sSR, sSA, sRJ, sCL},
294 /* c_e */{sCR, sIN, sIN, sCR, sCR, sCW, sCO, sCE, sES, sSS, sSR, sSA, sRJ, sCL},
295 /* c_a */{sES, sI1, sIN, sCS, sCR, sCW, sCO, sES, sES, sSS, sSR, sSA, sRJ, sCL},
296 /* s */{sSR, sI1, sIN, sCS, sCR, sCW, sCO, sCE, sSR, sSS, sSR, sSA, sRJ, sCL},
297 /* s_a */{sCL, sIN, sIN, sCS, sCR, sCW, sCO, sCE, sES, sCL, sSR, sCL, sRJ, sCL},
298 /* s_c */{sCL, sCL, sCL, sCS, sCR, sCW, sCO, sCE, sES, sSS, sSR, sCL, sRJ, sCL},
[all …]
/linux/drivers/net/wan/
H A Dhdlc_ppp.c86 enum {INV = 0x10, IRC = 0x20, ZRC = 0x40, SCR = 0x80, SCA = 0x100, enumerator
263 RCR+ = Receive-Configure-Request (Good) scr = Send-Configure-Request
280 {IRC|SCR|3, INV , INV , INV , INV , INV , INV }, /* START */
282 { INV , INV ,STR|2, SCR|3 ,SCR|3, SCR|5 , INV }, /* TO+ */
284 { STA|0 ,IRC|SCR|SCA|5, 2 , SCA|5 ,SCA|6, SCA|5 ,SCR|SCA|5}, /* RCR+ */
285 { STA|0 ,IRC|SCR|SCN|3, 2 , SCN|3 ,SCN|4, SCN|3 ,SCR|SCN|3}, /* RCR- */
286 { STA|0 , STA|1 , 2 , IRC|4 ,SCR|3, 6 , SCR|3 }, /* RCA */
287 { STA|0 , STA|1 , 2 ,IRC|SCR|3,SCR|3,IRC|SCR|5, SCR|3 }, /* RCN */
289 { 0 , 1 , 1 , 3 , 3 , 5 , SCR|3 }, /* RTA */
318 if (action & (SCR | STR)) /* set Configure-Req/Terminate-Req timer */ in ppp_cp_event()
[all …]
/linux/arch/powerpc/platforms/85xx/
H A Dmpc85xx_mds.c58 int scr; in mpc8568_fixup_125_clock() local
62 scr = phy_read(phydev, MV88E1111_SCR); in mpc8568_fixup_125_clock()
64 if (scr < 0) in mpc8568_fixup_125_clock()
65 return scr; in mpc8568_fixup_125_clock()
67 err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK)); in mpc8568_fixup_125_clock()
77 scr = phy_read(phydev, MV88E1111_SCR); in mpc8568_fixup_125_clock()
79 if (scr < 0) in mpc8568_fixup_125_clock()
80 return scr; in mpc8568_fixup_125_clock()
82 err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008); in mpc8568_fixup_125_clock()
/linux/sound/soc/fsl/
H A Dfsl_ssi.c123 u32 scr; member
213 * @i2s_net: I2S and Network mode configurations of SCR register
394 * fsl_ssi_config_enable - Set SCR, SIER, STCR and SRCR registers with
417 * to prevent online reconfigurations, then jump to set SCR directly in fsl_ssi_config_enable()
468 /* Enable all remaining bits in SCR */ in fsl_ssi_config_enable()
470 vals[dir].scr, vals[dir].scr); in fsl_ssi_config_enable()
497 * fsl_ssi_config_disable - Unset SCR, SIER, STCR and SRCR registers
510 u32 sier, srcr, stcr, scr; in fsl_ssi_config_disable() local
527 scr = ssi_excl_shared_bits(vals->scr, avals->scr, aactive); in fsl_ssi_config_disable()
529 /* Disable safe bits of SCR register for the current stream */ in fsl_ssi_config_disable()
[all …]
/linux/drivers/mmc/core/
H A Dsd_ops.c316 __be32 *scr; in mmc_app_send_scr() local
318 /* NOTE: caller guarantees scr is heap-allocated */ in mmc_app_send_scr()
327 scr = kmalloc(sizeof(card->raw_scr), GFP_KERNEL); in mmc_app_send_scr()
328 if (!scr) in mmc_app_send_scr()
344 sg_init_one(&sg, scr, 8); in mmc_app_send_scr()
350 card->raw_scr[0] = be32_to_cpu(scr[0]); in mmc_app_send_scr()
351 card->raw_scr[1] = be32_to_cpu(scr[1]); in mmc_app_send_scr()
353 kfree(scr); in mmc_app_send_scr()
H A Dsd.c201 * Given a 64-bit response, decode to our card SCR structure.
205 struct sd_scr *scr = &card->scr; in mmc_decode_scr() local
214 pr_err("%s: unrecognised SCR structure version %d\n", in mmc_decode_scr()
219 scr->sda_vsn = unstuff_bits(resp, 56, 4); in mmc_decode_scr()
220 scr->bus_widths = unstuff_bits(resp, 48, 4); in mmc_decode_scr()
221 if (scr->sda_vsn == SCR_SPEC_VER_2) in mmc_decode_scr()
223 scr->sda_spec3 = unstuff_bits(resp, 47, 1); in mmc_decode_scr()
225 if (scr->sda_spec3) { in mmc_decode_scr()
226 scr->sda_spec4 = unstuff_bits(resp, 42, 1); in mmc_decode_scr()
227 scr->sda_specx = unstuff_bits(resp, 38, 4); in mmc_decode_scr()
[all …]
/linux/drivers/tty/serial/8250/
H A D8250_pericom.c54 int scr; in pericom_do_set_divisor() local
56 for (scr = 16; scr > 4; scr--) { in pericom_do_set_divisor()
57 unsigned int maxrate = port->uartclk / scr; in pericom_do_set_divisor()
78 serial_port_out(port, 2, 16 - scr); in pericom_do_set_divisor()
H A D8250_uniphier.c20 * - No SCR (Instead, CHAR can be used as a scratch register)
64 * IO callbacks must be overridden for correct access to FCR, LCR, MCR and SCR.
72 /* No SCR for this hardware. Use CHAR as a scratch register */ in uniphier_serial_in()
102 /* No SCR for this hardware. Use CHAR as a scratch register */ in uniphier_serial_out()
/linux/arch/sh/boards/mach-hp6xx/
H A Dpm.c101 u8 scr; in hp6x0_pm_enter() local
108 scr = inb(HD64461_PCC1SCR); in hp6x0_pm_enter()
109 scr |= HD64461_PCCSCR_VCC1; in hp6x0_pm_enter()
110 outb(scr, HD64461_PCC1SCR); in hp6x0_pm_enter()
/linux/drivers/spi/
H A Dspi-ep93xx.c106 * @div_scr: pointer to return the scr divider
113 int cpsr, scr; in ep93xx_spi_calc_divisors() local
124 * rate = spi_clock_rate / (cpsr * (1 + scr)) in ep93xx_spi_calc_divisors()
126 * cpsr must be even number and starts from 2, scr can be any number in ep93xx_spi_calc_divisors()
130 for (scr = 0; scr <= 255; scr++) { in ep93xx_spi_calc_divisors()
131 if ((spi_clk_rate / (cpsr * (scr + 1))) <= rate) { in ep93xx_spi_calc_divisors()
132 *div_scr = (u8)scr; in ep93xx_spi_calc_divisors()
165 dev_dbg(&host->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n", in ep93xx_spi_chip_setup()
H A Datmel-quadspi.c156 u32 scr; member
198 return "SCR"; in atmel_qspi_reg_name()
504 aq->scr &= ~QSPI_SCR_SCBR_MASK; in atmel_qspi_setup()
505 aq->scr |= QSPI_SCR_SCBR(scbr); in atmel_qspi_setup()
506 atmel_qspi_write(aq->scr, aq, QSPI_SCR); in atmel_qspi_setup()
562 aq->scr &= ~QSPI_SCR_DLYBS_MASK; in atmel_qspi_set_cs_timing()
563 aq->scr |= QSPI_SCR_DLYBS(cs_setup); in atmel_qspi_set_cs_timing()
564 atmel_qspi_write(aq->scr, aq, QSPI_SCR); in atmel_qspi_set_cs_timing()
801 atmel_qspi_write(aq->scr, aq, QSPI_SCR); in atmel_qspi_resume()
/linux/drivers/dma/stm32/
H A Dstm32-dma.c532 u32 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_dump_reg() local
539 dev_dbg(chan2dev(chan), "SCR: 0x%08x\n", scr); in stm32_dma_dump_reg()
656 * to set it here in SCR backup to ensure a good reconfiguration on transfer complete. in stm32_dma_handle_chan_paused()
734 static void stm32_dma_handle_chan_done(struct stm32_dma_chan *chan, u32 scr) in stm32_dma_handle_chan_done() argument
745 if (!(scr & (STM32_DMA_SCR_CIRC | STM32_DMA_SCR_DBM))) in stm32_dma_handle_chan_done()
747 else if (scr & STM32_DMA_SCR_DBM) in stm32_dma_handle_chan_done()
764 u32 status, scr, sfcr; in stm32_dma_chan_irq() local
769 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_chan_irq()
776 if (!(scr & STM32_DMA_SCR_EN) && in stm32_dma_chan_irq()
792 if (scr & STM32_DMA_SCR_TCIE) { in stm32_dma_chan_irq()
[all …]
/linux/drivers/ata/
H A Dsata_uli.c33 ULI5287_BASE = 0x90, /* sata0 phy SCR registers */
35 ULI5281_BASE = 0x60, /* sata0 phy SCR registers */
103 static void uli_scr_cfg_write(struct ata_link *link, unsigned int scr, u32 val) in uli_scr_cfg_write() argument
106 unsigned int cfg_addr = get_scr_cfg_addr(link->ap, scr); in uli_scr_cfg_write()
H A Dsata_via.c75 static int vt8251_scr_read(struct ata_link *link, unsigned int scr, u32 *val);
76 static int vt8251_scr_write(struct ata_link *link, unsigned int scr, u32 val);
201 static int vt8251_scr_read(struct ata_link *link, unsigned int scr, u32 *val) in vt8251_scr_read() argument
209 switch (scr) { in vt8251_scr_read()
250 static int vt8251_scr_write(struct ata_link *link, unsigned int scr, u32 val) in vt8251_scr_write() argument
256 switch (scr) { in vt8251_scr_write()
315 * SCR registers on vt6420 are pieces of shit and may hang the
317 * To avoid such catastrophe, vt6420 doesn't provide generic SCR
338 /* don't do any SCR stuff if we're not loading */ in vt6420_prereset()
H A Dpata_pdc2027x.c586 u32 scr; in pdc_detect_pll_input_clock() local
592 scr = ioread32(mmio_base + PDC_SYS_CTL); in pdc_detect_pll_input_clock()
593 dev_dbg(host->dev, "scr[%X]\n", scr); in pdc_detect_pll_input_clock()
594 iowrite32(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL); in pdc_detect_pll_input_clock()
609 scr = ioread32(mmio_base + PDC_SYS_CTL); in pdc_detect_pll_input_clock()
610 dev_dbg(host->dev, "scr[%X]\n", scr); in pdc_detect_pll_input_clock()
611 iowrite32(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL); in pdc_detect_pll_input_clock()
H A Dlibata-sata.c31 * @link: ATA link to test SCR accessibility for
50 * sata_scr_read - read SCR register of the specified port
51 * @link: ATA link to read SCR for
52 * @reg: SCR to read
55 * Read SCR register @reg of @link into *@val. This function is
78 * sata_scr_write - write SCR register of the specified port
79 * @link: ATA link to write SCR for
80 * @reg: SCR to write
83 * Write @val to SCR register @reg of @link. This function is
106 * sata_scr_write_flush - write SCR register of the specified port and flush
[all …]
/linux/drivers/tty/serial/
H A Domap-serial.c59 /* SCR register bitmasks */
139 unsigned char scr; member
286 if (up->scr & OMAP_UART_SCR_TX_EMPTY) { in serial_omap_stop_tx()
294 up->scr &= ~OMAP_UART_SCR_TX_EMPTY; in serial_omap_stop_tx()
295 serial_out(up, UART_OMAP_SCR, up->scr); in serial_omap_stop_tx()
313 up->scr |= OMAP_UART_SCR_TX_EMPTY; in serial_omap_stop_tx()
314 serial_out(up, UART_OMAP_SCR, up->scr); in serial_omap_stop_tx()
369 up->scr &= ~OMAP_UART_SCR_TX_EMPTY; in serial_omap_start_tx()
370 serial_out(up, UART_OMAP_SCR, up->scr); in serial_omap_start_tx()
862 up->scr = 0; in serial_omap_set_termios()
[all …]
/linux/Documentation/userspace-api/media/v4l/
H A Dmetafmt-uvc.rst26 SCR field or with that field identical to the previous header), or generally to
51 - The rest of the header, possibly including UVC PTS and SCR fields
/linux/include/dt-bindings/clock/
H A Dbcm-sr.h36 /* GENPLL 0 clock channel ID SCR HSLS FS PCIE */
64 /* GENPLL 4 SCR clock channel ID */
/linux/drivers/scsi/libfc/
H A Dfc_encode.h888 * fc_scr_fill - Fill in a scr request frame.
892 struct fc_els_scr *scr; in fc_scr_fill() local
894 scr = fc_frame_payload_get(fp, sizeof(*scr)); in fc_scr_fill()
895 memset(scr, 0, sizeof(*scr)); in fc_scr_fill()
896 scr->scr_cmd = ELS_SCR; in fc_scr_fill()
897 scr->scr_reg_func = ELS_SCRF_FULL; in fc_scr_fill()

123456