Searched +full:rza1 +full:- +full:irqc (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,rza1-irqc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Chris Brandt <chris.brandt@renesas.com>11 - Geert Uytterhoeven <geert+renesas@glider.be>14 The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and16 - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts,17 - NMI edge select.20 - $ref: /schemas/interrupt-controller.yaml#[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Renesas RZ/A1 IRQC Driver19 #include <dt-bindings/interrupt-controller/arm-gic.h>51 return data->domain->host_data; in irq_data_to_priv()60 tmp = readw_relaxed(priv->base + IRQRR); in rza1_irqc_eoi()62 writew_relaxed(GENMASK(IRQC_NUM_IRQ - 1, 0) & ~bit, in rza1_irqc_eoi()63 priv->base + IRQRR); in rza1_irqc_eoi()92 return -EINVAL; in rza1_irqc_set_type()95 tmp = readw_relaxed(priv->base + ICR1); in rza1_irqc_set_type()98 writew_relaxed(tmp, priv->base + ICR1); in rza1_irqc_set_type()[all …]
1 // SPDX-License-Identifier: GPL-2.09 #include <dt-bindings/interrupt-controller/arm-gic.h>10 #include <dt-bindings/clock/r7s9210-cpg-mssr.h>14 interrupt-parent = <&gic>;15 #address-cells = <1>;16 #size-cells = <1>;20 #clock-cells = <0>;21 compatible = "fixed-clock";23 clock-frequency = <0>;27 #clock-cells = <0>;[all …]