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/freebsd/sys/contrib/device-tree/Bindings/reset/
H A Daltr,rst-mgr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/altr,rst
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H A Dsocfpga-reset.txt4 - compatible : "altr,rst-mgr" for (Cyclone5/Arria5/Arria10)
5 "altr,stratix10-rst-mgr","altr,rst-mgr" for Stratix10 ARM64 SoC
6 - reg : Should contain 1 register ranges(address and length)
7 - altr,modrst-offset : Should contain the offset of the first modrst register.
8 - #reset-cells: 1
12 #reset-cells = <1>;
13 compatible = "altr,rst-mgr";
15 altr,modrst-offset = <0x10>;
/freebsd/sys/contrib/device-tree/src/arm64/intel/
H A Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
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H A Dsocfpga_agilex5.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
14 compatible = "intel,socfpga-agilex5";
15 #address-cells = <2>;
16 #size-cells = <2>;
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/freebsd/sys/contrib/device-tree/src/arm64/altera/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
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/freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr
782 rst: rstmgr@ffd05000 { global() label
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H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cell
805 rst: rstmgr@ffd05000 { global() label
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/freebsd/sys/contrib/device-tree/Bindings/fpga/
H A Daltera-socfpga-a10-fpga-mgr.txt4 - compatible : should contain "altr,socfpga-a10-fpga-mgr"
5 - reg : base address and size for memory mapped io.
6 - The first index is for FPGA manager register access.
7 - The second index is for writing FPGA configuration data.
8 - resets : Phandle and reset specifier for the device's reset.
9 - clocks : Clocks used by the device.
13 fpga_mgr: fpga-mgr@ffd03000 {
14 compatible = "altr,socfpga-a10-fpga-mgr";
18 resets = <&rst FPGAMGR_RESET>;
H A Dfpga-region.txt6 - Introduction
7 - Terminology
8 - Sequence
9 - FPGA Region
10 - Supported Use Models
11 - Device Tree Examples
12 - Constraints
82 ---
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/freebsd/sys/contrib/device-tree/include/dt-bindings/reset/
H A Daltr,rst-mgr-a10sr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Adapted from altr,rst-mgr-a10.h
H A Daltr,rst-mgr-s10.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h"
71 /* 82-87 is empty */
90 /* 164-16
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/freebsd/sys/contrib/device-tree/Bindings/net/can/
H A Dbosch,c_can.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Dario Binacchi <dariobin@libero.it>
15 - $ref: can-controller.yaml#
20 - enum:
21 - bosch,c_can
22 - bosch,d_can
23 - ti,dra7-d_can
24 - ti,am3352-d_can
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/freebsd/share/misc/
H A Dpci_vendors5 # Date: 2024-11-25 03:15:02
8 # the PCI ID Project at https://pci-ids.ucw.cz/.
14 # (version 2 or higher) or the 3-clause BSD License.
25 # device device_name <-- single tab
26 # subvendor subdevice subsystem_name <-- two tabs
30 # This is a relabelled RTL-8139
31 8139 AT-2500TX V3 Ethernet
41 7a09 PCI-to-PCI Bridge
50 7a19 PCI-to-PCI Bridge
55 7a29 PCI-to-PCI Bridge
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