Lines Matching +full:rst +full:- +full:mgr
6 - Introduction
7 - Terminology
8 - Sequence
9 - FPGA Region
10 - Supported Use Models
11 - Device Tree Examples
12 - Constraints
82 ---------------- ----------------------------------
85 | ----| | ----------- -------- |
87 | | W | | | ----------- -------- |
89 | | B |<=====>|<==| ----------- -------- |
91 | | I | | | ----------- -------- |
93 | | G | | | ----------- -------- |
95 | ----| | ----------- -------- |
97 ---------------- ----------------------------------
100 region (PRR0-2) gets its own split of the busses that is independently gated by
101 a soft logic bridge (Bridge0-2) in the FPGA. The contents of each PRR can be
130 * image-specific information needed to to the programming.
137 If the live tree shows a "firmware-name" property or child nodes under an FPGA
139 and adds the "firmware-name" property is taken as a request to reprogram the
167 - compatible : should contain "fpga-region"
168 - fpga-mgr : should contain a phandle to an FPGA Manager. Child FPGA Regions
169 inherit this property from their ancestor regions. An fpga-mgr property
171 - #address-cells, #size-cells, ranges : must be present to handle address space
175 - firmware-name : should contain the name of an FPGA image file located on the
180 - fpga-bridges : should contain a list of phandles to FPGA Bridges that must be
183 If the fpga-region is the child of an fpga-bridge, the list should not
185 - partial-fpga-config : boolean, set if partial reconfiguration is to be done,
187 - external-fpga-config : boolean, set if the FPGA has already been configured
189 - encrypted-fpga-config : boolean, set if the bitstream is encrypted
190 - region-unfreeze-timeout-us : The maximum time in microseconds to wait for
193 - region-freeze-timeout-us : The maximum time in microseconds to wait for
196 - config-complete-timeout-us : The maximum time in microseconds time for the
198 - child nodes : devices in the FPGA after programming.
200 In the example below, when an overlay is applied targeting fpga-region0,
204 fpga-bridges property. During programming, these bridges are disabled, the
216 fpga_mgr: fpga-mgr@ff706000 {
217 compatible = "altr,socfpga-fpga-mgr";
223 fpga_bridge0: fpga-bridge@ff400000 {
224 compatible = "altr,socfpga-lwhps2fpga-bridge";
226 resets = <&rst LWHPS2FPGA_RESET>;
229 #address-cells = <1>;
230 #size-cells = <1>;
233 fpga_region0: fpga-region0 {
234 compatible = "fpga-region";
235 fpga-mgr = <&fpga_mgr>;
239 fpga_bridge1: fpga-bridge@ff500000 {
240 compatible = "altr,socfpga-hps2fpga-bridge";
242 resets = <&rst HPS2FPGA_RESET>;
248 /dts-v1/;
252 #address-cells = <1>;
253 #size-cells = <1>;
255 firmware-name = "soc_system.rbf";
256 fpga-bridges = <&fpga_bridge1>;
261 compatible = "altr,pio-1.0";
264 #gpio-cells = <2>;
266 gpio-controller;
269 onchip-memory {
271 compatible = "altr,onchipmem-15.1";
295 fpga-bridges property in the FPGA region or in the device tree overlay.
315 * target-path or target
323 Bridges. The FPGA Region's "fpga-mgr" property specifies the manager by phandle
326 they are specified in the FPGA Region by the "fpga-bridges" property. During
328 "fpga-bridges" list and will re-enable them after FPGA programming has
332 * "target-path" or "target"
334 live tree. target-path is a full path, while target is a phandle.
337 * "firmware-name"
340 * "partial-fpga-config"
350 fpga_mgr0: fpga-mgr@f8007000 {
351 compatible = "xlnx,zynq-devcfg-1.0";
353 interrupt-parent = <&intc>;
356 clock-names = "ref_clk";
360 fpga_region0: fpga-region0 {
361 compatible = "fpga-region";
362 fpga-mgr = <&fpga_mgr0>;
363 #address-cells = <0x1>;
364 #size-cells = <0x1>;
370 /dts-v1/;
374 #address-cells = <1>;
375 #size-cells = <1>;
377 firmware-name = "zynq-gpio.bin";
380 compatible = "xlnx,xps-gpio-1.00.a";
382 gpio-controller;
383 #gpio-cells = <0x2>;
384 xlnx,gpio-width= <0x6>;
398 /dts-v1/;
402 #address-cells = <1>;
403 #size-cells = <1>;
405 firmware-name = "base.rbf";
407 fpga-bridge@4400 {
408 compatible = "altr,freeze-bridge-controller";
411 fpga_region1: fpga-region1 {
412 compatible = "fpga-region";
413 #address-cells = <0x1>;
414 #size-cells = <0x1>;
419 fpga-bridge@4420 {
420 compatible = "altr,freeze-bridge-controller";
423 fpga_region2: fpga-region2 {
424 compatible = "fpga-region";
425 #address-cells = <0x1>;
426 #size-cells = <0x1>;
439 "partial-fpga-config" boolean and the only bridge that is controlled during
442 /dts-v1/;
446 #address-cells = <1>;
447 #size-cells = <1>;
449 firmware-name = "soc_image2.rbf";
450 partial-fpga-config;
453 compatible = "altr,pio-1.0";
457 #gpio-cells = <0x2>;
458 gpio-controller;
476 --
477 [1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf