1<?xml version="1.0" encoding="UTF-8"?> 2<database xmlns="http://nouveau.freedesktop.org/" 3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> 5<import file="freedreno_copyright.xml"/> 6 7<enum name="chip" bare="yes"> 8 <value name="A2XX" value="2"/> 9 <value name="A3XX" value="3"/> 10 <value name="A4XX" value="4"/> 11 <value name="A5XX" value="5"/> 12 <value name="A6XX" value="6"/> 13 <value name="A7XX" value="7"/> 14 <value name="A8XX" value="8"/> 15</enum> 16 17<enum name="desctype" bare="yes"> 18 <value name="DESC_NONE" value="0"/> 19 <doc> 20 TEX_MEMOBJ descriptor types. These are used 21 to mark fields that only apply to certain 22 descriptor types, and potentially overlap 23 with fields in other types. 24 </doc> 25 <value name="DESC_SINGLE_PLANE" value="1"/> 26 <value name="DESC_MULTI_PLANE" value="2"/> 27 <value name="DESC_BUFFER" value="3"/> 28 <value name="DESC_WEIGHT" value="4"/> 29 <doc> 30 Additional descriptor types not part of 31 TEX_MEMOBJ. These are described by their 32 own toplevel domain. 33 </doc> 34 <value name="DESC_SAMPLER" value="10"/> <!-- AxXX_UBO --> 35 <value name="DESC_UBO" value="11"/> <!-- A6XX_UBO, same on gen8 --> 36</enum> 37 38<enum name="adreno_pa_su_sc_draw"> 39 <value name="PC_DRAW_POINTS" value="0"/> 40 <value name="PC_DRAW_LINES" value="1"/> 41 <value name="PC_DRAW_TRIANGLES" value="2"/> 42</enum> 43 44<enum name="adreno_compare_func"> 45 <value name="FUNC_NEVER" value="0"/> 46 <value name="FUNC_LESS" value="1"/> 47 <value name="FUNC_EQUAL" value="2"/> 48 <value name="FUNC_LEQUAL" value="3"/> 49 <value name="FUNC_GREATER" value="4"/> 50 <value name="FUNC_NOTEQUAL" value="5"/> 51 <value name="FUNC_GEQUAL" value="6"/> 52 <value name="FUNC_ALWAYS" value="7"/> 53</enum> 54 55<enum name="adreno_stencil_op"> 56 <value name="STENCIL_KEEP" value="0"/> 57 <value name="STENCIL_ZERO" value="1"/> 58 <value name="STENCIL_REPLACE" value="2"/> 59 <value name="STENCIL_INCR_CLAMP" value="3"/> 60 <value name="STENCIL_DECR_CLAMP" value="4"/> 61 <value name="STENCIL_INVERT" value="5"/> 62 <value name="STENCIL_INCR_WRAP" value="6"/> 63 <value name="STENCIL_DECR_WRAP" value="7"/> 64</enum> 65 66<enum name="adreno_rb_blend_factor"> 67 <value name="FACTOR_ZERO" value="0"/> 68 <value name="FACTOR_ONE" value="1"/> 69 <value name="FACTOR_SRC_COLOR" value="4"/> 70 <value name="FACTOR_ONE_MINUS_SRC_COLOR" value="5"/> 71 <value name="FACTOR_SRC_ALPHA" value="6"/> 72 <value name="FACTOR_ONE_MINUS_SRC_ALPHA" value="7"/> 73 <value name="FACTOR_DST_COLOR" value="8"/> 74 <value name="FACTOR_ONE_MINUS_DST_COLOR" value="9"/> 75 <value name="FACTOR_DST_ALPHA" value="10"/> 76 <value name="FACTOR_ONE_MINUS_DST_ALPHA" value="11"/> 77 <value name="FACTOR_CONSTANT_COLOR" value="12"/> 78 <value name="FACTOR_ONE_MINUS_CONSTANT_COLOR" value="13"/> 79 <value name="FACTOR_CONSTANT_ALPHA" value="14"/> 80 <value name="FACTOR_ONE_MINUS_CONSTANT_ALPHA" value="15"/> 81 <value name="FACTOR_SRC_ALPHA_SATURATE" value="16"/> 82 <value name="FACTOR_SRC1_COLOR" value="20"/> 83 <value name="FACTOR_ONE_MINUS_SRC1_COLOR" value="21"/> 84 <value name="FACTOR_SRC1_ALPHA" value="22"/> 85 <value name="FACTOR_ONE_MINUS_SRC1_ALPHA" value="23"/> 86</enum> 87 88<bitset name="adreno_rb_stencilrefmask" inline="yes"> 89 <bitfield name="STENCILREF" low="0" high="7" type="hex"/> 90 <bitfield name="STENCILMASK" low="8" high="15" type="hex"/> 91 <bitfield name="STENCILWRITEMASK" low="16" high="23" type="hex"/> 92</bitset> 93 94<enum name="adreno_rb_surface_endian"> 95 <value name="ENDIAN_NONE" value="0"/> 96 <value name="ENDIAN_8IN16" value="1"/> 97 <value name="ENDIAN_8IN32" value="2"/> 98 <value name="ENDIAN_16IN32" value="3"/> 99 <value name="ENDIAN_8IN64" value="4"/> 100 <value name="ENDIAN_8IN128" value="5"/> 101</enum> 102 103<enum name="adreno_rb_dither_mode"> 104 <value name="DITHER_DISABLE" value="0"/> 105 <value name="DITHER_ALWAYS" value="1"/> 106 <value name="DITHER_IF_ALPHA_OFF" value="2"/> 107</enum> 108 109<enum name="adreno_rb_depth_format"> 110 <value name="DEPTHX_16" value="0"/> 111 <value name="DEPTHX_24_8" value="1"/> 112 <value name="DEPTHX_32" value="2"/> 113</enum> 114 115<enum name="adreno_rb_copy_control_mode"> 116 <value name="RB_COPY_RESOLVE" value="1"/> 117 <value name="RB_COPY_CLEAR" value="2"/> 118 <value name="RB_COPY_DEPTH_STENCIL" value="5"/> <!-- not sure if this is part of MODE or another bitfield?? --> 119</enum> 120 121<bitset name="adreno_reg_xy" inline="yes"> 122 <bitfield name="WINDOW_OFFSET_DISABLE" pos="31" type="boolean"/> 123 <bitfield name="X" low="0" high="14" type="uint"/> 124 <bitfield name="Y" low="16" high="30" type="uint"/> 125</bitset> 126 127<bitset name="adreno_cp_protect" inline="yes"> 128 <bitfield name="BASE_ADDR" low="0" high="16"/> 129 <bitfield name="MASK_LEN" low="24" high="28"/> 130 <bitfield name="TRAP_WRITE" pos="29"/> 131 <bitfield name="TRAP_READ" pos="30"/> 132</bitset> 133 134<domain name="AXXX" width="32"> 135 <brief>Registers in common between a2xx and a3xx</brief> 136 137 <reg32 offset="0x01c0" name="CP_RB_BASE"/> 138 <reg32 offset="0x01c1" name="CP_RB_CNTL"> 139 <bitfield name="BUFSZ" low="0" high="5"/> 140 <bitfield name="BLKSZ" low="8" high="13"/> 141 <bitfield name="BUF_SWAP" low="16" high="17"/> 142 <bitfield name="POLL_EN" pos="20" type="boolean"/> 143 <bitfield name="NO_UPDATE" pos="27" type="boolean"/> 144 <bitfield name="RPTR_WR_EN" pos="31" type="boolean"/> 145 </reg32> 146 <reg32 offset="0x01c3" name="CP_RB_RPTR_ADDR"> 147 <bitfield name="SWAP" low="0" high="1" type="uint"/> 148 <bitfield name="ADDR" low="2" high="31" shr="2"/> 149 </reg32> 150 <reg32 offset="0x01c4" name="CP_RB_RPTR" type="uint"/> 151 <reg32 offset="0x01c5" name="CP_RB_WPTR" type="uint"/> 152 <reg32 offset="0x01c6" name="CP_RB_WPTR_DELAY"/> 153 <reg32 offset="0x01c7" name="CP_RB_RPTR_WR"/> 154 <reg32 offset="0x01c8" name="CP_RB_WPTR_BASE"/> 155 <reg32 offset="0x01d5" name="CP_QUEUE_THRESHOLDS"> 156 <bitfield name="CSQ_IB1_START" low="0" high="3" type="uint"/> 157 <bitfield name="CSQ_IB2_START" low="8" high="11" type="uint"/> 158 <bitfield name="CSQ_ST_START" low="16" high="19" type="uint"/> 159 </reg32> 160 <reg32 offset="0x01d6" name="CP_MEQ_THRESHOLDS"> 161 <bitfield name="MEQ_END" low="16" high="20" type="uint"/> 162 <bitfield name="ROQ_END" low="24" high="28" type="uint"/> 163 </reg32> 164 <reg32 offset="0x01d7" name="CP_CSQ_AVAIL"> 165 <bitfield name="RING" low="0" high="6" type="uint"/> 166 <bitfield name="IB1" low="8" high="14" type="uint"/> 167 <bitfield name="IB2" low="16" high="22" type="uint"/> 168 </reg32> 169 <reg32 offset="0x01d8" name="CP_STQ_AVAIL"> 170 <bitfield name="ST" low="0" high="6" type="uint"/> 171 </reg32> 172 <reg32 offset="0x01d9" name="CP_MEQ_AVAIL"> 173 <bitfield name="MEQ" low="0" high="4" type="uint"/> 174 </reg32> 175 <reg32 offset="0x01dc" name="SCRATCH_UMSK"> 176 <bitfield name="UMSK" low="0" high="7" type="uint"/> 177 <bitfield name="SWAP" low="16" high="17" type="uint"/> 178 </reg32> 179 <reg32 offset="0x01dd" name="SCRATCH_ADDR"/> 180 <reg32 offset="0x01ea" name="CP_ME_RDADDR"/> 181 182 <reg32 offset="0x01ec" name="CP_STATE_DEBUG_INDEX"/> 183 <reg32 offset="0x01ed" name="CP_STATE_DEBUG_DATA"/> 184 <reg32 offset="0x01f2" name="CP_INT_CNTL"> 185 <bitfield name="SW_INT_MASK" pos="19" type="boolean"/> 186 <bitfield name="T0_PACKET_IN_IB_MASK" pos="23" type="boolean"/> 187 <bitfield name="OPCODE_ERROR_MASK" pos="24" type="boolean"/> 188 <bitfield name="PROTECTED_MODE_ERROR_MASK" pos="25" type="boolean"/> 189 <bitfield name="RESERVED_BIT_ERROR_MASK" pos="26" type="boolean"/> 190 <bitfield name="IB_ERROR_MASK" pos="27" type="boolean"/> 191 <bitfield name="IB2_INT_MASK" pos="29" type="boolean"/> 192 <bitfield name="IB1_INT_MASK" pos="30" type="boolean"/> 193 <bitfield name="RB_INT_MASK" pos="31" type="boolean"/> 194 </reg32> 195 <reg32 offset="0x01f3" name="CP_INT_STATUS"/> 196 <reg32 offset="0x01f4" name="CP_INT_ACK"/> 197 <reg32 offset="0x01f6" name="CP_ME_CNTL"> 198 <bitfield name="BUSY" pos="29" type="boolean"/> 199 <bitfield name="HALT" pos="28" type="boolean"/> 200 </reg32> 201 <reg32 offset="0x01f7" name="CP_ME_STATUS"/> 202 <reg32 offset="0x01f8" name="CP_ME_RAM_WADDR"/> 203 <reg32 offset="0x01f9" name="CP_ME_RAM_RADDR"/> 204 <reg32 offset="0x01fa" name="CP_ME_RAM_DATA"/> 205 <reg32 offset="0x01fc" name="CP_DEBUG"> 206 <bitfield name="PREDICATE_DISABLE" pos="23" type="boolean"/> 207 <bitfield name="PROG_END_PTR_ENABLE" pos="24" type="boolean"/> 208 <bitfield name="MIU_128BIT_WRITE_ENABLE" pos="25" type="boolean"/> 209 <bitfield name="PREFETCH_PASS_NOPS" pos="26" type="boolean"/> 210 <bitfield name="DYNAMIC_CLK_DISABLE" pos="27" type="boolean"/> 211 <bitfield name="PREFETCH_MATCH_DISABLE" pos="28" type="boolean"/> 212 <bitfield name="SIMPLE_ME_FLOW_CONTROL" pos="30" type="boolean"/> 213 <bitfield name="MIU_WRITE_PACK_DISABLE" pos="31" type="boolean"/> 214 </reg32> 215 <reg32 offset="0x01fd" name="CP_CSQ_RB_STAT"> 216 <bitfield name="RPTR" low="0" high="6" type="uint"/> 217 <bitfield name="WPTR" low="16" high="22" type="uint"/> 218 </reg32> 219 <reg32 offset="0x01fe" name="CP_CSQ_IB1_STAT"> 220 <bitfield name="RPTR" low="0" high="6" type="uint"/> 221 <bitfield name="WPTR" low="16" high="22" type="uint"/> 222 </reg32> 223 <reg32 offset="0x01ff" name="CP_CSQ_IB2_STAT"> 224 <bitfield name="RPTR" low="0" high="6" type="uint"/> 225 <bitfield name="WPTR" low="16" high="22" type="uint"/> 226 </reg32> 227 228 <reg32 offset="0x0440" name="CP_NON_PREFETCH_CNTRS"/> 229 <reg32 offset="0x0443" name="CP_STQ_ST_STAT"/> 230 <reg32 offset="0x044d" name="CP_ST_BASE"/> 231 <reg32 offset="0x044e" name="CP_ST_BUFSZ"/> 232 <reg32 offset="0x044f" name="CP_MEQ_STAT"/> 233 <reg32 offset="0x0452" name="CP_MIU_TAG_STAT"/> 234 <reg32 offset="0x0454" name="CP_BIN_MASK_LO"/> 235 <reg32 offset="0x0455" name="CP_BIN_MASK_HI"/> 236 <reg32 offset="0x0456" name="CP_BIN_SELECT_LO"/> 237 <reg32 offset="0x0457" name="CP_BIN_SELECT_HI"/> 238 <reg32 offset="0x0458" name="CP_IB1_BASE"/> 239 <reg32 offset="0x0459" name="CP_IB1_BUFSZ"/> 240 <reg32 offset="0x045a" name="CP_IB2_BASE"/> 241 <reg32 offset="0x045b" name="CP_IB2_BUFSZ"/> 242 <reg32 offset="0x047f" name="CP_STAT"> 243 <bitfield pos="31" name="CP_BUSY"/> 244 <bitfield pos="30" name="VS_EVENT_FIFO_BUSY"/> 245 <bitfield pos="29" name="PS_EVENT_FIFO_BUSY"/> 246 <bitfield pos="28" name="CF_EVENT_FIFO_BUSY"/> 247 <bitfield pos="27" name="RB_EVENT_FIFO_BUSY"/> 248 <bitfield pos="26" name="ME_BUSY"/> 249 <bitfield pos="25" name="MIU_WR_C_BUSY"/> 250 <bitfield pos="23" name="CP_3D_BUSY"/> 251 <bitfield pos="22" name="CP_NRT_BUSY"/> 252 <bitfield pos="21" name="RBIU_SCRATCH_BUSY"/> 253 <bitfield pos="20" name="RCIU_ME_BUSY"/> 254 <bitfield pos="19" name="RCIU_PFP_BUSY"/> 255 <bitfield pos="18" name="MEQ_RING_BUSY"/> 256 <bitfield pos="17" name="PFP_BUSY"/> 257 <bitfield pos="16" name="ST_QUEUE_BUSY"/> 258 <bitfield pos="13" name="INDIRECT2_QUEUE_BUSY"/> 259 <bitfield pos="12" name="INDIRECTS_QUEUE_BUSY"/> 260 <bitfield pos="11" name="RING_QUEUE_BUSY"/> 261 <bitfield pos="10" name="CSF_BUSY"/> 262 <bitfield pos="9" name="CSF_ST_BUSY"/> 263 <bitfield pos="8" name="EVENT_BUSY"/> 264 <bitfield pos="7" name="CSF_INDIRECT2_BUSY"/> 265 <bitfield pos="6" name="CSF_INDIRECTS_BUSY"/> 266 <bitfield pos="5" name="CSF_RING_BUSY"/> 267 <bitfield pos="4" name="RCIU_BUSY"/> 268 <bitfield pos="3" name="RBIU_BUSY"/> 269 <bitfield pos="2" name="MIU_RD_RETURN_BUSY"/> 270 <bitfield pos="1" name="MIU_RD_REQ_BUSY"/> 271 <bitfield pos="0" name="MIU_WR_BUSY"/> 272 </reg32> 273 <reg32 offset="0x0578" name="CP_SCRATCH_REG0" type="uint"/> 274 <reg32 offset="0x0579" name="CP_SCRATCH_REG1" type="uint"/> 275 <reg32 offset="0x057a" name="CP_SCRATCH_REG2" type="uint"/> 276 <reg32 offset="0x057b" name="CP_SCRATCH_REG3" type="uint"/> 277 <reg32 offset="0x057c" name="CP_SCRATCH_REG4" type="uint"/> 278 <reg32 offset="0x057d" name="CP_SCRATCH_REG5" type="uint"/> 279 <reg32 offset="0x057e" name="CP_SCRATCH_REG6" type="uint"/> 280 <reg32 offset="0x057f" name="CP_SCRATCH_REG7" type="uint"/> 281 282 <reg32 offset="0x0600" name="CP_ME_VS_EVENT_SRC"/> 283 <reg32 offset="0x0601" name="CP_ME_VS_EVENT_ADDR"/> 284 <reg32 offset="0x0602" name="CP_ME_VS_EVENT_DATA"/> 285 <reg32 offset="0x0603" name="CP_ME_VS_EVENT_ADDR_SWM"/> 286 <reg32 offset="0x0604" name="CP_ME_VS_EVENT_DATA_SWM"/> 287 <reg32 offset="0x0605" name="CP_ME_PS_EVENT_SRC"/> 288 <reg32 offset="0x0606" name="CP_ME_PS_EVENT_ADDR"/> 289 <reg32 offset="0x0607" name="CP_ME_PS_EVENT_DATA"/> 290 <reg32 offset="0x0608" name="CP_ME_PS_EVENT_ADDR_SWM"/> 291 <reg32 offset="0x0609" name="CP_ME_PS_EVENT_DATA_SWM"/> 292 <reg32 offset="0x060a" name="CP_ME_CF_EVENT_SRC"/> 293 <reg32 offset="0x060b" name="CP_ME_CF_EVENT_ADDR"/> 294 <reg32 offset="0x060c" name="CP_ME_CF_EVENT_DATA" type="uint"/> 295 <reg32 offset="0x060d" name="CP_ME_NRT_ADDR"/> 296 <reg32 offset="0x060e" name="CP_ME_NRT_DATA"/> 297 <reg32 offset="0x0612" name="CP_ME_VS_FETCH_DONE_SRC"/> 298 <reg32 offset="0x0613" name="CP_ME_VS_FETCH_DONE_ADDR"/> 299 <reg32 offset="0x0614" name="CP_ME_VS_FETCH_DONE_DATA"/> 300 301</domain> 302 303<!-- 304 Common between A3xx and A4xx: 305 --> 306 307<enum name="a3xx_rop_code"> 308 <value name="ROP_CLEAR" value="0"/> 309 <value name="ROP_NOR" value="1"/> 310 <value name="ROP_AND_INVERTED" value="2"/> 311 <value name="ROP_COPY_INVERTED" value="3"/> 312 <value name="ROP_AND_REVERSE" value="4"/> 313 <value name="ROP_INVERT" value="5"/> 314 <value name="ROP_XOR" value="6"/> 315 <value name="ROP_NAND" value="7"/> 316 <value name="ROP_AND" value="8"/> 317 <value name="ROP_EQUIV" value="9"/> 318 <value name="ROP_NOOP" value="10"/> 319 <value name="ROP_OR_INVERTED" value="11"/> 320 <value name="ROP_COPY" value="12"/> 321 <value name="ROP_OR_REVERSE" value="13"/> 322 <value name="ROP_OR" value="14"/> 323 <value name="ROP_SET" value="15"/> 324</enum> 325 326<enum name="a3xx_render_mode"> 327 <value name="RB_RENDERING_PASS" value="0"/> 328 <value name="RB_TILING_PASS" value="1"/> 329 <value name="RB_RESOLVE_PASS" value="2"/> 330 <value name="RB_COMPUTE_PASS" value="3"/> 331</enum> 332 333<enum name="a3xx_msaa_samples"> 334 <value name="MSAA_ONE" value="0"/> 335 <value name="MSAA_TWO" value="1"/> 336 <value name="MSAA_FOUR" value="2"/> 337 <value name="MSAA_EIGHT" value="3"/> 338</enum> 339 340<enum name="a3xx_threadmode"> 341 <value value="0" name="MULTI"/> 342 <value value="1" name="SINGLE"/> 343</enum> 344 345<enum name="a3xx_instrbuffermode"> 346 <!-- 347 When shader size goes above ~128 or so, blob switches to '0' 348 and doesn't emit shader in cmdstream. When either is '0' it 349 doesn't get emitted via CP_LOAD_STATE. When only one is 350 '0' the other gets size 256-others_size. So I think that: 351 BUFFER => execute out of state memory 352 CACHE => use available state memory as local cache 353 NOTE that when CACHE mode, also set CACHEINVALID flag! 354 355 TODO check if that 256 size is same for all a3xx 356 --> 357 <value value="0" name="CACHE"/> 358 <value value="1" name="BUFFER"/> 359</enum> 360 361<enum name="a3xx_threadsize"> 362 <value value="0" name="TWO_QUADS"/> 363 <value value="1" name="FOUR_QUADS"/> 364</enum> 365 366<enum name="a3xx_color_swap"> 367 <value name="WZYX" value="0"/> 368 <value name="WXYZ" value="1"/> 369 <value name="ZYXW" value="2"/> 370 <value name="XYZW" value="3"/> 371</enum> 372 373<enum name="a3xx_rb_blend_opcode"> 374 <value name="BLEND_DST_PLUS_SRC" value="0"/> 375 <value name="BLEND_SRC_MINUS_DST" value="1"/> 376 <value name="BLEND_DST_MINUS_SRC" value="2"/> 377 <value name="BLEND_MIN_DST_SRC" value="3"/> 378 <value name="BLEND_MAX_DST_SRC" value="4"/> 379</enum> 380 381<enum name="a4xx_tess_spacing"> 382 <value name="EQUAL_SPACING" value="0"/> 383 <value name="ODD_SPACING" value="2"/> 384 <value name="EVEN_SPACING" value="3"/> 385</enum> 386 387<doc>Address mode for a5xx+</doc> 388<enum name="a5xx_address_mode"> 389 <value name="ADDR_32B" value="0"/> 390 <value name="ADDR_64B" value="1"/> 391</enum> 392 393<doc> 394 Line mode for a5xx+ 395 Note that Bresenham lines are only supported with MSAA disabled. 396</doc> 397<enum name="a5xx_line_mode"> 398 <value value="0x0" name="BRESENHAM"/> 399 <value value="0x1" name="RECTANGULAR"/> 400</enum> 401 402<doc> 403 Blob (v615) seem to only use SAM and I wasn't able to coerce 404 it to produce any other command. 405 Probably valid for a4xx+ but not enabled or tested on anything 406 but a6xx. 407</doc> 408<enum name="a6xx_tex_prefetch_cmd"> 409 <doc> Produces garbage </doc> 410 <value value="0x0" name="TEX_PREFETCH_UNK0"/> 411 <value value="0x1" name="TEX_PREFETCH_SAM"/> 412 <value value="0x2" name="TEX_PREFETCH_GATHER4R"/> 413 <value value="0x3" name="TEX_PREFETCH_GATHER4G"/> 414 <value value="0x4" name="TEX_PREFETCH_GATHER4B"/> 415 <value value="0x5" name="TEX_PREFETCH_GATHER4A"/> 416 <doc> Causes reads from an invalid address </doc> 417 <value value="0x6" name="TEX_PREFETCH_UNK6"/> 418 <doc> Results in color being zero </doc> 419 <value value="0x7" name="TEX_PREFETCH_UNK7"/> 420</enum> 421 422<enum name="adreno_pipe"> 423 <value value="0" name="PIPE_NONE"/> 424 <value value="1" name="PIPE_BR"/> 425 <value value="2" name="PIPE_BV"/> 426 <value value="3" name="PIPE_LPAC"/> 427 <value value="4" name="PIPE_AQE0"/> 428 <value value="5" name="PIPE_AQE1"/> 429 <value value="6" name="PIPE_DDE_BR"/> 430 <value value="7" name="PIPE_DDE_BV"/> 431</enum> 432 433<!-- 434 A fake domain for giving lua scripts access to the shader_stats struct 435 --> 436<domain name="ir3_shader_stats" width="32"> 437 <!-- indx 0 is bindful, indx N+1 is .baseN --> 438 <array offset="0" name="descriptor_stats" stride="8" length="9"> 439 <reg64 offset="0" name="img"/> 440 <reg64 offset="2" name="tex"/> 441 <reg64 offset="4" name="samp"/> 442 <reg64 offset="6" name="ubo"/> 443 </array> 444 <reg32 offset="72" name="has_img"/> 445 <reg32 offset="73" name="has_tex"/> 446 <reg32 offset="74" name="has_samp"/> 447 <reg32 offset="74" name="has_ubo"/> 448 <!-- 449 other following fields can be added as needed, but we 450 might need to take care of padding/alignment. 451 --> 452</domain> 453 454</database> 455