Home
last modified time | relevance | path

Searched +full:riscv +full:- +full:aia (Results 1 – 9 of 9) sorted by relevance

/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Driscv,imsics.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Incoming MSI Controller (IMSIC)
10 - Anup Patel <anup@brainfault.org>
13 The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming
14 MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
15 AIA specification can be found at https://github.com/riscv/riscv-aia.
17 The IMSIC is a per-CPU (or per-HART) device with separate interrupt file
[all …]
H A Driscv,aplic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Advanced Platform Level Interrupt Controller (APLIC)
10 - Anup Patel <anup@brainfault.org>
13 The RISC-V advanced interrupt architecture (AIA) defines an advanced
15 in a RISC-V platform. The RISC-V AIA specification can be found at
16 https://github.com/riscv/riscv-aia.
18 The RISC-V APLIC is implemented as hierarchical APLIC domains where all
[all …]
/linux/arch/riscv/kvm/
H A Daia_device.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/irqchip/riscv-imsic.h>
19 for (; vcpu_lock_idx >= 0; vcpu_lock_idx--) { in unlock_vcpus()
21 mutex_unlock(&tmp_vcpu->mutex); in unlock_vcpus()
27 unlock_vcpus(kvm, atomic_read(&kvm->online_vcpus) - 1); in unlock_all_vcpus()
36 if (!mutex_trylock(&tmp_vcpu->mutex)) { in lock_all_vcpus()
37 unlock_vcpus(kvm, c - 1); in lock_all_vcpus()
49 struct kvm *kvm = dev->kvm; in aia_create()
53 return -EEXIST; in aia_create()
55 ret = -EBUSY; in aia_create()
[all …]
H A Daia.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/irqchip/riscv-imsic.h>
39 raw_spin_lock_irqsave(&hgctrl->lock, flags); in aia_find_hgei()
41 hgei = -1; in aia_find_hgei()
43 if (hgctrl->owners[i] == owner) { in aia_find_hgei()
49 raw_spin_unlock_irqrestore(&hgctrl->lock, flags); in aia_find_hgei()
72 struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr; in kvm_riscv_vcpu_aia_flush_interrupts()
78 if (READ_ONCE(vcpu->arch.irqs_pending_mask[1])) { in kvm_riscv_vcpu_aia_flush_interrupts()
79 mask = xchg_acquire(&vcpu->arch.irqs_pending_mask[1], 0); in kvm_riscv_vcpu_aia_flush_interrupts()
80 val = READ_ONCE(vcpu->arch.irqs_pending[1]) & mask; in kvm_riscv_vcpu_aia_flush_interrupts()
[all …]
/linux/Documentation/devicetree/bindings/riscv/
H A Dextensions.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
[all …]
/linux/drivers/irqchip/
H A Dirq-riscv-aplic-msi.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/irqchip/riscv-aplic.h>
13 #include <linux/irqchip/riscv-imsic.h>
21 #include "irq-riscv-aplic-main.h"
43 * The section "4.9.2 Special consideration for level-sensitive interrupt in aplic_msi_irq_retrigger_level()
44 * sources" of the RISC-V AIA specification says: in aplic_msi_irq_retrigger_level()
52 writel(d->hwirq, priv->regs + APLIC_SETIPNUM_LE); in aplic_msi_irq_retrigger_level()
60 * EOI handling is required only for level-triggered interrupts in aplic_msi_irq_eoi()
73 * Updating sourcecfg register for level-triggered interrupts in aplic_msi_irq_set_type()
84 struct aplic_msicfg *mc = &priv->msicfg; in aplic_msi_write_msg()
[all …]
H A Dirq-riscv-intc.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2017-2018 SiFive
8 #define pr_fmt(fmt) "riscv-intc: " fmt
31 unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; in riscv_intc_irq()
46 * On RISC-V systems local interrupts are masked or unmasked by writing
54 if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) in riscv_intc_irq_mask()
55 csr_clear(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); in riscv_intc_irq_mask()
57 csr_clear(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_mask()
62 if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) in riscv_intc_irq_unmask()
63 csr_set(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); in riscv_intc_irq_unmask()
[all …]
H A Dirq-riscv-imsic-state.c1 // SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "riscv-imsic: " fmt
22 #include "irq-riscv-imsic-state.h"
63 return imsic ? &imsic->global : NULL; in imsic_get_global_config()
74 imask = BIT(id & (__riscv_xlen - 1)); in __imsic_eix_read_clear()
102 * are XLEN-wide and we must not touch IDs which in __imsic_eix_update()
106 for (i = id & (__riscv_xlen - 1); id < last_id && i < __riscv_xlen; i++) { in __imsic_eix_update()
133 lockdep_assert_held(&lpriv->lock); in __imsic_local_sync()
135 for_each_set_bit(i, lpriv->dirty_bitmap, imsic->global.nr_ids + 1) { in __imsic_local_sync()
138 vec = &lpriv->vectors[i]; in __imsic_local_sync()
[all …]
/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
[all …]