| /linux/Documentation/devicetree/bindings/power/reset/ |
| H A D | gpio-restart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpio-restart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO controlled reset
10 - Sebastian Reichel <sre@kernel.org>
15 This binding supports level and edge triggered reset. At driver load time, the driver will
17 'open-source' is not found, the GPIO line will be driven in the inactive state. Otherwise its
21 is configured as an output, and driven active, triggering a level triggered reset condition.
22 This will also cause an inactive->active edge condition, triggering positive edge triggered
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| H A D | gpio-poweroff.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpio-poweroff.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
15 from inactive to active. After a delay (active-delay-ms) it
17 delay (inactive-delay-ms) it is configured as active again.
19 the system is still running after waiting some time (timeout-ms).
22 - $ref: restart-handler.yaml#
26 const: gpio-poweroff
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| H A D | ltc2952-poweroff.txt | 4 been sent, the chip's watchdog has to be reset to gracefully shut down.
9 - compatible: Must contain: "lltc,ltc2952"
10 - watchdog-gpios: phandle + gpio-specifier for the GPIO connected to the
12 - kill-gpios: phandle + gpio-specifier for the GPIO connected to the
16 - trigger-gpios: phandle + gpio-specifier for the GPIO connected to the
20 - trigger-delay-ms The number of milliseconds to wait after trigger line
22 The default is 2500ms.
29 trigger-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
30 trigger-delay-ms = <2000>;
31 watchdog-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
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| /linux/drivers/gpu/drm/i915/ |
| H A D | Kconfig.profile | 2 int "Default timeout for requests (ms)"
16 int "Timeout for unsignaled foreign fences (ms, jiffy granularity)"
28 int "Runtime autosuspend delay for userspace GGTT mmaps (ms)"
35 that complements the runtime-pm autosuspend and provides a lower
36 floor on the autosuspend delay.
38 May be 0 to disable the extra delay and solely use the device level
39 runtime pm autosuspend delay tunable.
42 int "Interval between heartbeat pulses (ms)"
46 check the health of the GPU and undertake regular house-keeping of
56 int "Preempt timeout (ms, jiffy granularity)"
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| /linux/Documentation/devicetree/bindings/input/ |
| H A D | nvidia,tegra20-kbc.txt | 7 - compatible: "nvidia,tegra20-kbc"
8 - reg: Register base address of KBC.
9 - interrupts: Interrupt number for the KBC.
10 - nvidia,kbc-row-pins: The KBC pins which are configured as row. This is an
12 - nvidia,kbc-col-pins: The KBC pins which are configured as column. This is an
14 - linux,keymap: The keymap for keys as described in the binding document
15 devicetree/bindings/input/matrix-keymap.txt.
16 - clocks: Must contain one entry, for the module clock.
17 See ../clocks/clock-bindings.txt for details.
18 - resets: Must contain an entry for each entry in reset-names.
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| H A D | syna,rmi4.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jason A. Donenfeld <Jason@zx2c4.com>
11 - Matthias Schiffer <matthias.schiffer@ew.tq-group.com
12 - Vincent Huang <vincent.huang@tw.synaptics.com>
22 - syna,rmi4-i2c
23 - syna,rmi4-spi
28 '#address-cells':
31 '#size-cells':
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| /linux/Documentation/devicetree/bindings/sound/ |
| H A D | cs35l33.txt | 5 - compatible : "cirrus,cs35l33"
7 - reg : the I2C address of the device for I2C
9 - VA-supply, VP-supply : power supplies for the device,
15 - reset-gpios : gpio used to reset the amplifier
17 - interrupts : IRQ line info CS35L33.
18 (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
21 - cirrus,boost-ctl : Booster voltage use to supply the amp. If the value is
26 - cirrus,ramp-rate : On power up, it affects the time from when the power
27 up sequence begins to the time the audio reaches a full-scale output.
28 On power down, it affects the time from when the power-down sequence
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| H A D | cs35l36.txt | 5 - compatible : "cirrus,cs35l36"
7 - reg : the I2C address of the device for I2C
9 - VA-supply, VP-supply : power supplies for the device,
13 - cirrus,boost-ctl-millivolt : Boost Voltage Value. Configures the boost
18 - cirrus,boost-peak-milliamp : Boost-converter peak current limit in mA.
24 - cirrus,boost-ind-nanohenry : Inductor estimation LBST reference value.
32 - cirrus,multi-amp-mode : Boolean to determine if there are more than
33 one amplifier in the system. If more than one it is best to Hi-Z the ASP
36 - cirrus,boost-ctl-select : Boost converter control source selection.
39 0x00 - Control Port Value
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| /linux/Documentation/devicetree/bindings/mmc/ |
| H A D | mmc-pwrseq-simple.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-simple.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
19 const: mmc-pwrseq-simple
21 reset-gpios:
26 contains a list of GPIO specifiers. The reset GPIOs are asserted
28 They will be de-asserted right after the power has been provided to the
33 description: Handle for the entry in clock-names.
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| /linux/Documentation/devicetree/bindings/display/panel/ |
| H A D | samsung,ld9040.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrzej Hajda <a.hajda@samsung.com>
13 - $ref: panel-common.yaml#
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
23 display-timings: true
25 reset-gpios: true
27 vdd3-supply:
30 vci-supply:
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| /linux/Documentation/devicetree/bindings/mfd/ |
| H A D | rohm,bd71847-pmic.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/rohm,bd71847-pmic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matti Vaittinen <mazziesaccount@gmail.com>
14 single-core, dual-core, and quad-core SoCs such as NXP-i.MX 8M. It is
18 …/www.rohm.com/products/power-management/power-management-ic-for-system/industrial-consumer-applica…
19 …//www.rohm.com/products/power-management/power-management-ic-for-system/industrial-consumer-applic…
24 - rohm,bd71847
25 - rohm,bd71850
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| H A D | st,stmpe.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Linus Walleij <linus.walleij@linaro.org>
18 - $ref: /schemas/spi/spi-peripheral-props.yaml#
23 - st,stmpe601
24 - st,stmpe801
25 - st,stmpe811
26 - st,stmpe1600
27 - st,stmpe1601
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| /linux/drivers/hid/intel-thc-hid/intel-quicki2c/ |
| H A D | quicki2c-dev.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/hid-over-i2c.h>
43 /* Max interrupt delay capability is 2.56ms */
46 /* Default interrupt delay is 1ms, suitable for most devices */
52 * Default value is 5000ms, that means if no touch event in this time, THC will
72 * struct quicki2c_subip_acpi_parameter - QuickI2C ACPI DSD parameters
88 * struct quicki2c_subip_acpi_config - QuickI2C ACPI DSD parameters
110 * @INDE: Interrupt Delay Feature Enable Control
111 * @INDV: Interrupt Delay Value (unit in 10 us)
147 * struct quicki2c_ddata - Driver specific data for quicki2c device
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| /linux/drivers/media/usb/gspca/ |
| H A D | finepix.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
18 /* Default timeout, in ms */
33 /* Delay after which claim the next frame. If the delay is too small,
34 * the camera will return old frames. On the 4800Z, 20ms is bad, 25ms
35 * will fail every 4 or 5 frames, but 30ms is perfect. On the A210,
36 * 30ms is bad while 35ms is perfect. */
50 int order) /* 0: reset, 1: frame request */ in command()
53 {0xc6, 0, 0, 0, 0, 0, 0, 0, 0x20, 0, 0, 0}, /* reset */ in command()
57 memcpy(gspca_dev->usb_buf, order_values[order], 12); in command()
58 return usb_control_msg(gspca_dev->dev, in command()
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| /linux/drivers/fsi/ |
| H A D | fsi-master.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * FSI master definitions. These comprise the core <--> master interface,
4 * to allow the core to interact with the (hardware-specific) masters.
24 #define FSI_MDLYR 0x4 /* R/W: delay */
33 #define FSI_MRESP0 0xd0 /* W: Port reset */
35 #define FSI_MRESB0 0x1d0 /* W: Reset bridge */
47 /* MSB=1, LSB=0 is 0.8 ms */
48 /* MSB=0, LSB=1 is 0.9 ms */
54 /* MRESB: Reset bridge */
55 #define FSI_MRESB_RST_GEN 0x80000000 /* General reset */
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| /linux/drivers/net/phy/ |
| H A D | dp83tg720.c | 1 // SPDX-License-Identifier: GPL-2.0
18 * The DP83TG720 1000BASE-T1 PHY has several limitations that require
19 * software-side mitigations. These workarounds are implemented throughout
23 * 1. Unreliable Link Detection and Synchronized Reset Deadlock
24 * ------------------------------------------------------------
31 * a connection after 100ms. This procedure is adopted as the workaround for the
34 * However, in point-to-point setups where both link partners use the same
35 * driver (e.g. Linux on both sides), a synchronized reset pattern may emerge.
36 * This leads to a deadlock, where both PHYs reset at the same time and
37 * continuously miss each other during auto-negotiation.
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| /linux/drivers/mmc/host/ |
| H A D | sdhci-bcm-kona.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/delay.h>
14 #include <linux/mmc/slot-gpio.h>
16 #include "sdhci-pltfm.h"
52 /* This timeout should be sufficent for core to reset */ in sdhci_bcm_kona_sd_reset()
55 /* reset the host using the top level reset */ in sdhci_bcm_kona_sd_reset()
62 pr_err("Error: sd host is stuck in reset!!!\n"); in sdhci_bcm_kona_sd_reset()
63 return -EFAULT; in sdhci_bcm_kona_sd_reset()
67 /* bring the host out of reset */ in sdhci_bcm_kona_sd_reset()
72 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS) in sdhci_bcm_kona_sd_reset()
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| /linux/arch/arm/boot/dts/st/ |
| H A D | stih418.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih418-clock.dtsi"
7 #include "stih407-family.dtsi"
8 #include "stih410-pinctrl.dtsi"
9 #include <dt-bindings/thermal/thermal.h>
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
18 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
19 cpu-release-addr = <0x94100A4>;
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| /linux/sound/usb/ |
| H A D | usbaudio.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 /* handling of USB vendor/product ID pairs as 32-bit numbers */
56 struct list_head ep_list; /* list of audio-related endpoints */
80 #define USB_AUDIO_IFACE_UNUSED ((void *)-1L)
83 dev_err(&(chip)->dev->dev, fmt, ##args)
85 dev_err_ratelimited(&(chip)->dev->dev, fmt, ##args)
87 dev_warn(&(chip)->dev->dev, fmt, ##args)
89 dev_info(&(chip)->dev->dev, fmt, ##args)
91 dev_dbg(&(chip)->dev->dev, fmt, ##args)
98 #define QUIRK_NODEV_INTERFACE -3 /* return -ENODEV */
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| /linux/drivers/watchdog/ |
| H A D | advantech_ec_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/delay.h>
25 /* EC minimum IO access delay in ms */
58 /* ensure minimum delay between IO accesses*/ in adv_ec_wdt_timing_gate()
62 time_delta = EC_MIN_DELAY - time_delta; in adv_ec_wdt_timing_gate()
90 /* scale time to EC 100 ms base */ in adv_ec_wdt_set_timeout()
93 /* reset enable delay, just in case it was set by BIOS etc. */ in adv_ec_wdt_set_timeout()
102 /* set reset delay */ in adv_ec_wdt_set_timeout()
111 wdd->timeout = t; in adv_ec_wdt_set_timeout()
117 adv_ec_wdt_set_timeout(wdd, wdd->timeout); in adv_ec_wdt_start()
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | intel-gw-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rahul Tanwar <rtanwar@maxlinear.com>
16 const: intel,lgm-pcie
18 - compatible
21 - $ref: /schemas/pci/snps,dw-pcie.yaml#
26 - const: intel,lgm-pcie
27 - const: snps,dw-pcie
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| /linux/arch/arm64/boot/dts/freescale/ |
| H A D | imx93-var-som.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
12 model = "Variscite VAR-SOM-MX93 module";
13 compatible = "variscite,var-som-mx93", "fsl,imx93";
15 mmc_pwrseq: mmc-pwrseq {
16 compatible = "mmc-pwrseq-simple";
17 post-power-on-delay-ms = <100>;
18 power-off-delay-us = <10000>;
19 reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
25 pinctrl-names = "default";
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| /linux/drivers/media/i2c/ |
| H A D | dw9768.c | 1 // SPDX-License-Identifier: GPL-2.0
4 #include <linux/delay.h>
9 #include <media/v4l2-async.h>
10 #include <media/v4l2-ctrls.h>
11 #include <media/v4l2-device.h>
12 #include <media/v4l2-fwnode.h>
13 #include <media/v4l2-subdev.h>
16 #define DW9768_MAX_FOCUS_POS (1024 - 1)
31 * DW9768 requires waiting time of Topr after PD reset takes place.
71 * Tvib = (6.3ms + AACT[5:0] * 0.1ms) * Dividing Rate
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| /linux/drivers/dma/qcom/ |
| H A D | hidma_ll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
13 #include <linux/dma-mapping.h>
14 #include <linux/delay.h>
72 iter -= ring_size; \
120 if (tre_ch >= lldev->nr_tres) { in hidma_ll_free()
121 dev_err(lldev->dev, "invalid TRE number in free:%d", tre_ch); in hidma_ll_free()
125 tre = &lldev->trepool[tre_ch]; in hidma_ll_free()
126 if (atomic_read(&tre->allocated) != true) { in hidma_ll_free()
127 dev_err(lldev->dev, "trying to free an unused TRE:%d", tre_ch); in hidma_ll_free()
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| /linux/drivers/acpi/ |
| H A D | reboot.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/delay.h>
16 /* The reset register can only live on bus 0. */ in acpi_pci_reboot()
21 devfn = PCI_DEVFN((rr->address >> 32) & 0xffff, in acpi_pci_reboot()
22 (rr->address >> 16) & 0xffff); in acpi_pci_reboot()
26 (rr->address & 0xffff), reset_value); in acpi_pci_reboot()
46 /* ACPI reset register was only introduced with v2 of the FADT */ in acpi_reboot()
51 /* Is the reset register supported? The spec says we should be in acpi_reboot()
59 /* The reset register can only exist in I/O, Memory or PCI config space in acpi_reboot()
61 switch (rr->space_id) { in acpi_reboot()
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