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/linux/Documentation/netlink/specs/
H A Ddpll.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
2 ---
8 -
16 -
20 -
23 render-max: true
24 -
26 name: lock-status
31 -
37 -
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H A Dnet_shaper.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
2 ---
3 name: net-shaper
33 @cap-get operation.
36 -
40 render-max: true
42 - name: unspec
44 -
47 -
52 -
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/linux/drivers/gpu/drm/imagination/
H A Dpvr_rogue_fwif_client.h1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
27 * Minimum PB = Base Pages + (NUM_TE_PIPES-1)*16K + (NUM_VCE_PIPES-1)*64K +
39 * Since the max of NUM_TE_PIPES and NUM_VCE_PIPES is 4, we have a hard limit
40 * of 4GB minus the Minimum PB. For convenience we take the smaller power-of-2
60 /* Indicates whether this render produces visibility results. */
66 /* Disable pixel merging for this render. */
70 /* Disallow compute overlapped with this render. */
153 * Holds the geometry/fragment fence value to allow the fragment partial render command
252 /* Stride IN BYTES for Z-Buffer in case of RTAs. */
254 /* Stride IN BYTES for S-Buffer in case of RTAs. */
H A Dpvr_rogue_fwif_sf.h1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
47 * - --- ---- ---- ---- ---- ---- ---- ----
48 * 0-11: id number
49 * 12-15: group id number
50 * 16-19: number of parameters
51 * 20-27: unused
52 * 28-30: active: identify SF packet, otherwise regular int32
80 "Kick 3D: FWCtx 0x%08.8x @ %d, RTD 0x%08x. Partial render:%d, CSW resume:%d, prio:%d" },
96 "Restart TA after partial render" },
98 "Resume TA without partial render" },
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H A Dpvr_rogue_fwif.h1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
42 /* String used in pvrdebug -h output */
140 /* Firmware per-DM HWR states */
147 /* DM need partial render cleanup before resuming processing */
155 /* DM was identified as over-running and causing HWR */
157 /* DM was innocently affected by another DM over-running which caused HWR */
270 /* Identify whether MC config is P-P or P-S */
274 /* per-os firmware shared data */
297 /* Firmware trace time-stamp field breakup */
303 /* Extra debug-info (16 bits) */
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/linux/Documentation/driver-api/mtd/
H A Dspi-intel.rst2 Upgrading BIOS using spi-intel
14 The spi-intel driver makes it possible to read and write the SPI serial
16 any of them set, the whole MTD device is made read-only to prevent
18 contents as read-only but it can be changed from kernel command line,
22 might render the machine unbootable and requires special equipment like
25 Below are the steps how to upgrade MinnowBoard MAX BIOS directly from
28 1) Download and extract the latest Minnowboard MAX BIOS SPI image
31 2) Install mtd-utils package [2]. We need this in order to erase the SPI
33 name "mtd-utils".
67 Erasing 4 Kibyte @ 7ff000 -- 100 % complete
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/linux/drivers/gpu/drm/
H A Ddrm_ioctl.c56 * - GET_UNIQUE ioctl, implemented by drm_getunique is wrapped up in libdrm
58 * - The libdrm drmSetBusid function is backed by the SET_UNIQUE ioctl. All
60 * - The internal set_busid kernel functions and driver callbacks are
63 * - Other ioctls and functions involved are named consistently.
76 * side-effect this fills out the unique name in the master structure.
121 mutex_lock(&dev->master_mutex); in drm_getunique()
122 master = file_priv->master; in drm_getunique()
123 if (u->unique_len >= master->unique_len) { in drm_getunique()
124 if (copy_to_user(u->unique, master->unique, master->unique_len)) { in drm_getunique()
125 mutex_unlock(&dev->master_mutex); in drm_getunique()
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H A Ddrm_drv.c79 * A DRM device can provide several char-dev interfaces on the DRM-Major. Each
81 * of the device-driver, different interfaces are registered.
83 * Minors can be accessed via dev->$minor_name. This pointer is either
85 * valid. This means, DRM minors have the same life-time as the underlying
87 * registered and unregistered dynamically according to device-state.
99 return ERR_PTR(-EOPNOTSUPP); in drm_minor_get_xa()
107 return &dev->primary; in drm_minor_get_slot()
109 return &dev->render; in drm_minor_get_slot()
111 return &dev->accel; in drm_minor_get_slot()
121 WARN_ON(dev != minor->dev); in drm_minor_alloc_release()
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/linux/scripts/
H A Dasn1_compiler.c1 // SPDX-License-Identifier: GPL-2.0-or-later
229 [DIRECTIVE_ENCODING_CONTROL] = "ENCODING-CONTROL",
253 _(MAX),
255 [DIRECTIVE_MINUS_INFINITY] = "MINUS-INFINITY",
265 [DIRECTIVE_PLUS_INFINITY] = "PLUS-INFINITY",
270 [DIRECTIVE_RELATIVE_OID] = "RELATIVE-OID",
325 clen = (dlen < token->size) ? dlen : token->size; in directive_compare()
327 //debug("cmp(%s,%s) = ", token->content, dir); in directive_compare()
329 val = memcmp(token->content, dir, clen); in directive_compare()
335 if (dlen == token->size) { in directive_compare()
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_fb.c1 // SPDX-License-Identifier: MIT
6 #include <linux/dma-fence.h>
7 #include <linux/dma-resv.h>
26 #define check_array_bounds(display, a, i) drm_WARN_ON((display)->drm, (i) >= ARRAY_SIZE(a))
31 * the cache-line pairs. The compression state of the cache-line pair
32 * is specified by 2 bits in the CCS. Each CCS cache-line represents
33 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
34 * cache-lin
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H A Dskl_universal_plane.c1 // SPDX-License-Identifier: MIT
280 const struct drm_framebuffer *fb = plane_state->hw.fb; in glk_plane_ratio()
282 if (fb->format->cpp[0] == 8) { in glk_plane_ratio()
307 const struct drm_framebuffer *fb = plane_state->hw.fb; in skl_plane_ratio()
309 if (fb->format->cpp[0] == 8) { in skl_plane_ratio()
333 int cpp = fb->format->cpp[color_plane]; in skl_plane_max_width()
335 switch (fb->modifier) { in skl_plane_max_width()
341 * - Ytile (already limited to 4k) in skl_plane_max_width()
342 * - FP16 (already limited to 4k) in skl_plane_max_width()
343 * - render compression (already limited to 4k) in skl_plane_max_width()
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/linux/sound/pci/lx6464es/
H A Dlx_defs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* -*- linux-c -*- *
16 * [ 44k - ( 44.1k + 48k ) / 2 ]
75 #define MAX_STREAM_BUFFER 5 /* max amount of stream buffers. */
80 /* #define MASK_GRANULARITY (2*MICROBLAZE_IBL_MAX-1) */
130 PSTATE_PURGE = 2, /* the ES channels are now off, render pipes do
132 PSTATE_ACQUIRE = 3, /* the ES channels are now on, render pipes do
170 SF_XRUN = 0x20000000, /* the stream is un x-run state. */
281 #define ED_REGISTRY_ERROR (ED_GN | 0x28) /* <- NCX */
282 #define ED_INVALID_SERVICE (ED_GN | 0x29) /* <- NCX */
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/linux/drivers/gpu/drm/xe/
H A Dxe_guc_capture.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2021-2024 Intel Corporation
45 * Book-keeping structure used to track read and write pointers
46 * as we extract error capture data from the GuC-log-buffer's
47 * error-capture region as a stream of dwords.
57 * struct __guc_capture_parsed_output - extracted error capture node
59 * A single unit of extracted error-capture output data grouped together
60 * at an engine-instanc
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/linux/drivers/gpu/drm/amd/display/modules/freesync/
H A Dfreesync.c2 * Copyright 2016-2023 Advanced Micro Devices, Inc.
36 /* Number of elements in the render times cache array */
38 /* Threshold to exit/exit BTR (to avoid frequent enter-exits at the lower limit) */
72 core_freesync->dc = dc; in mod_freesync_create()
73 return &core_freesync->public; in mod_freesync_create()
119 * 10000) * stream->timing.h_total, in calc_duration_in_us_from_v_total()
120 stream->timing.pix_clk_100hz)); in calc_duration_in_us_from_v_total()
127 unsigned int max_hw_v_total = stream->ctx->dc->caps.max_v_total; in calc_max_hardware_v_total()
129 if (stream->ctx->dc->caps.vtotal_limited_by_fp2) { in calc_max_hardware_v_total()
130 max_hw_v_total -= stream->timing.v_front_porch + 1; in calc_max_hardware_v_total()
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/linux/drivers/gpu/drm/msm/
H A Dmsm_debugfs.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2016 Red Hat
10 #include <linux/fault-inject.h>
35 struct msm_gpu_show_priv *show_priv = m->private; in msm_gpu_show()
36 struct msm_drm_private *priv = show_priv->dev->dev_private; in msm_gpu_show()
37 struct msm_gpu *gpu = priv->gpu; in msm_gpu_show()
40 ret = mutex_lock_interruptible(&gpu->lock); in msm_gpu_show()
44 drm_printf(&p, "%s Status:\n", gpu->name); in msm_gpu_show()
45 gpu->funcs->show(gpu, show_priv->state, &p); in msm_gpu_show()
47 mutex_unlock(&gpu->lock); in msm_gpu_show()
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/linux/Documentation/gpu/rfc/
H A Dcolor_pipeline.rst1 .. SPDX-License-Identifier: GPL-2.0
10 We would like to support pre-, and post-blending complex color
12 HW-supported HDR use-cases, as well as to provide support to
13 color-managed applications, such as video or image editors.
17 compositor or application to render and compose the content into one
22 implemented in fixed-function HW and therefore much more power efficient than
27 fixed-function blocks and shaders/CPU must be seamless with no visible
34 The most widely supported use-cases regard HDR content, whether video or
38 function, and other metadata, such as max and average light levels) to a driver.
39 Drivers will then program their fixed-function HW accordingly to map from a
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/linux/include/uapi/drm/
H A Damdgpu_drm.h1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
90 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous
97 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data
178 /* Flag that BO should be coherent across devices when using device-level
186 /* Set PTE.D and recompress during GTT->VRAM moves according to TILING flags. */
279 #define AMDGPU_CTX_PRIORITY_UNSET -2048
280 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023
281 #define AMDGPU_CTX_PRIORITY_LOW -512
370 * @doorbell_offset: 32-bit offset of the doorbell in the doorbell bo.
385 * @queue_size: Size of the queue in bytes, this needs to be 256-byte
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H A Dradeon_drm.h1 /* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
66 #define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
72 /* New style per-packet identifiers for use in cmd_buffer ioctl with
183 #define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note:
234 /* these two defines are DOING IT WRONG - however
332 * a 1K-byte boundary.
336 #define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
450 /* Counters for client-side throttling of rendering clients.
640 /* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
641 * - allows multiple primitives and state changes in a single ioctl
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H A Di915_drm.h19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
37 * subject to backwards-compatibility constraints.
43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
46 * track of these events, and if a specific cache-line seems to have a
48 * intel-gpu-tools. The value supplied with the event is always 1.
50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
66 * struct i915_user_extension - Base class for defining a chain of extensions
82 * .. code-block:: C
158 * enum drm_i915_gem_engine_class - uapi engine type enumeration
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/linux/drivers/video/fbdev/
H A Dudlfb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * udlfb.c -- Framebuffer driver for DisplayLink USB controller
10 * usb-skeleton by GregKH.
12 * Device-specific portions based on information from Displaylink, with work
48 * There are many DisplayLink-based graphics products, all with unique PIDs.
49 * So we match on DisplayLink's VID + Vendor-Defined Interface Class (0xff)
114 * ----- -----------------------------
200 while (actual_count--) { in dlfb_lfsr16()
229 xds = var->left_margin + var->hsync_len; in dlfb_set_vid_cmds()
232 xde = xds + var->xres; in dlfb_set_vid_cmds()
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/linux/tools/power/x86/turbostat/
H A Dturbostat.83 turbostat \- Report processor frequency and idle statistics
12 .RB [ "\--interval seconds" ]
15 idle power-state statistics, temperature and power on X86 processors.
19 in one-shot upon its completion.
22 The 5-second interval can be changed using the --interval option.
26 Options can be specified with a single or double '-', and only as much of the option
27 name as necessary to disambiguate it from others is necessary. Note that options are case-sensitiv…
29 \fB--add attributes\fP add column with counter having specified 'attributes'. The 'location' attri…
39 … event for given device from /sys/bus/event_source/devices/<device>/events/<event> eg. c1-residency
40 …perf/cstate_core/c1-residency would then use /sys/bus/event_source/devices/cstate_core/events/c1-r…
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/linux/drivers/net/ethernet/netronome/nfp/
H A Dnfp_net_ctrl.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2 /* Copyright (C) 2015-2018 Netronome Systems, Inc. */
17 /* 64-bit per app capabilities */
23 * THB-350, 32k needs to be reserved.
61 /* Hash type pre-pended when a RSS hash was computed */
80 /* Read/Write config words (0x0000 - 0x002c)
87 * %NFP_NET_CFG_EXN: MSI-X table entry for exceptions
88 * %NFP_NET_CFG_LSC: MSI-X table entry for link state changes
92 * - define Error details in UPDATE
108 #define NFP_NET_CFG_CTRL_RXQINQ (0x1 << 13) /* Enable S-tag strip */
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/linux/drivers/gpu/drm/msm/registers/adreno/
H A Dadreno_pm4.xml1 <?xml version="1.0" encoding="UTF-8"?>
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
9 <value name="VS_DEALLOC" value="0x00" variants="A2XX-A5XX"/>
10 <value name="PS_DEALLOC" value="0x01" variants="A2XX-A5XX"/>
11 <value name="VS_DONE_TS" value="0x02" variants="A2XX-A5XX"/>
12 <value name="PS_DONE_TS" value="0x03" variants="A2XX-A5XX"/>
19 <value name="CACHE_FLUSH" value="0x06" variants="A2XX-A4XX"/>
21 <value name="HLSQ_FLUSH" value="0x07" variants="A3XX-A4XX"/>
24 <value name="WRITE_PRIMITIVE_COUNTS" value="0x09" variants="A6XX-"/>
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/linux/tools/include/uapi/drm/
H A Di915_drm.h19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
37 * subject to backwards-compatibility constraints.
43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
46 * track of these events, and if a specific cache-line seems to have a
48 * intel-gpu-tools. The value supplied with the event is always 1.
50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
66 * struct i915_user_extension - Base class for defining a chain of extensions
82 * .. code-block:: C
158 * enum drm_i915_gem_engine_class - uapi engine type enumeration
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd.c1 // SPDX-License-Identifier: MIT
33 #include <linux/dma-buf.h>
53 amdgpu_amdkfd_total_mem_size = si.freeram - si.freehigh; in amdgpu_amdkfd_init()
77 adev->kfd.dev = kgd2kfd_probe(adev, vf); in amdgpu_amdkfd_device_probe()
81 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
102 if (adev->enable_mes) { in amdgpu_doorbell_get_kfd_info()
109 *aperture_base = adev->doorbell.base; in amdgpu_doorbell_get_kfd_info()
112 } else if (adev->doorbell.size > adev->doorbell.num_kernel_doorbells * in amdgpu_doorbell_get_kfd_info()
114 *aperture_base = adev->doorbell.base; in amdgpu_doorbell_get_kfd_info()
115 *aperture_size = adev->doorbell.size; in amdgpu_doorbell_get_kfd_info()
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