| /freebsd/sys/dev/bhnd/siba/ |
| H A D | siba_subr.c | 1 /*-
2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
55 * Map a siba(4) OCP vendor code to its corresponding JEDEC JEP-106 vendor
89 for (u_int i = 0; i < nitems(dinfo->cfg); i++) { in siba_alloc_dinfo()
90 dinfo->cfg[i] = ((struct siba_cfg_block){ in siba_alloc_dinfo()
93 .cb_rid = -1, in siba_alloc_dinfo()
95 dinfo->cfg_res[i] = NULL; in siba_alloc_dinfo()
98 resource_list_init(&dinfo->resources); in siba_alloc_dinfo()
100 dinfo->pmu_state = SIBA_PMU_NONE; in siba_alloc_dinfo()
102 dinfo->intr = (struct siba_intr) { in siba_alloc_dinfo()
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| H A D | sibavar.h | 1 /*-
2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
122 /* Sonics configuration register blocks */
126 register blocks */
128 #define SIBA_CFG_RID_BASE 100 /**< base resource ID for SIBA_CFG* register allocations */
131 (_dinfo->core_id.core_info.core_idx * SIBA_MAX_CFG))
171 bool mapped; /**< if an irq has been mapped */ member
172 int rid; /**< bus resource id, or -1 if unassigned */
173 rman_res_t irq; /**< the mapped bus irq, if any */
177 * siba(4) per-core identification info.
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| /freebsd/sys/dev/bhnd/bhndb/ |
| H A D | bhndb.h | 1 /*-
50 * bhndb register window types.
69 * bhndb register window definition.
83 /** Core-specific register window (BHNDB_REGWIN_T_CORE). */
85 bhnd_devclass_t class; /**< mapped core's class */
86 u_int unit; /**< mapped core's unit */
87 bhnd_port_type port_type; /**< mapped port type */
88 u_int port; /**< mapped port number */
89 u_int region; /**< mapped region number */
90 bhnd_size_t offset; /**< mapped offset within the region */
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| H A D | bhndb_pci.c | 1 /*-
2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
36 * PCI-specific implementation for the BHNDB bridge driver.
38 * Provides support for bridging from a PCI parent bus to a BHND-compatible
39 * bus (e.g. bcma or siba) via a Broadcom PCI core configured in end-point
42 * This driver handles all initial generic host-level PCI interactions with a
44 * bus has been enumerated, this driver works in tandem with a core-specific
147 bool mapped; /**< true if a valid mapping exists */ member
148 bhnd_addr_t addr; /**< mapped address */
149 bhnd_size_t size; /**< mapped size */
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| H A D | bhndb_pcireg.h | 1 /*-
36 * - PCI (cid=0x804, revision <= 12)
40 * [0x0000+0x1000] dynamic mapped backplane address space (window 0).
47 * - PCI (cid=0x804, revision >= 13)
48 * - PCIE (cid=0x820) with ChipCommon (revision <= 31)
52 * [0x0000+0x1000] dynamic mapped backplane address space (window 0).
59 * - PCIE (cid=0x820) with ChipCommon (revision >= 32)
63 * [0x0000+0x1000] dynamic mapped backplane address space (window 0).
64 * [0x1000+0x1000] dynamic mapped backplane address space (window 1).
70 * - PCIE Gen 2 (cid=0x83c)
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | VirtRegMap.h | 1 //===- llvm/CodeGen/VirtRegMap.h - Virtual Register Map ---------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements a virtual register map. This maps virtual registers to
11 // updated by a register allocator and then used by a machine code rewriter that
12 // adds spill code and rewrites virtual into physical register references.
14 //===----------------------------------------------------------------------===//
37 NO_STACK_SLOT = (1L << 30)-1,
38 MAX_STACK_SLOT = (1L << 18)-1
47 /// Virt2PhysMap - This is a virtual to physical register
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | mdio-mux-mmioreg.txt | 1 Properties for an MDIO bus multiplexer controlled by a memory-mapped device
3 This is a special case of a MDIO bus multiplexer. A memory-mapped device,
4 like an FPGA, is used to control which child bus is connected. The mdio-mux
5 node must be a child of the memory-mapped device. The driver currently only
6 supports devices with 8, 16 or 32-bit registers.
10 - compatible : string, must contain "mdio-mux-mmioreg"
12 - reg : integer, contains the offset of the register that controls the bus
14 register, and must therefore be 1, 2, or 4.
16 - mux-mask : integer, contains an eight-bit mask that specifies which
17 bits in the register control the actual bus multiplexer. The
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| H A D | mdio-mux-mmioreg.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-mmioreg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Properties for an MDIO bus multiplexer controlled by a memory-mapped device
10 - Andrew Lunn <andrew@lunn.ch>
13 This is a special case of a MDIO bus multiplexer. A memory-mapped device,
14 like an FPGA, is used to control which child bus is connected. The mdio-mux
15 node must be a child of the memory-mapped device. The driver currently only
16 supports devices with 8, 16 or 32-bit registers.
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| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | snps,dw-pcie.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
23 - compatible
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| H A D | snps,dw-pcie-ep.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie-ep
23 - compatible
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| /freebsd/sys/contrib/device-tree/Bindings/power/reset/ |
| H A D | syscon-reboot-mode.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/power/reset/syscon-reboot-mode.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
13 This driver gets reboot mode magic value from reboot-mode driver
14 and stores it in a SYSCON mapped register. Then the bootloader
16 value stored. The SYSCON mapped register is retrieved from the
17 parental dt-node plus the offset. So the SYSCON reboot-mode node
18 should be represented as a sub-node of a "syscon", "simple-mfd" node.
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| H A D | syscon-poweroff.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/reset/syscon-poweroff.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic SYSCON mapped register powerof
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| /freebsd/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | gpio-mmio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Bartosz Golaszewski <brgl@bgdev.pl>
14 Some simple GPIO controllers may consist of a single data register or a pair
15 of set/clear-bit registers. Such controllers are common for glue logic in
16 FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped
17 NAND-style parallel busses.
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| H A D | wd,mbl-gpio.txt | 1 Bindings for the Western Digital's MyBook Live memory-mapped GPIO controllers.
3 The Western Digital MyBook Live has two memory-mapped GPIO controllers.
4 Both GPIO controller only have a single 8-bit data register, where GPIO
8 - compatible: should be "wd,mbl-gpio"
9 - reg-names: must contain
10 "dat" - data register
11 - reg: address + size pairs describing the GPIO register sets;
12 order must correspond with the order of entries in reg-names
13 - #gpio-cells: must be set to 2. The first cell is the pin number and
17 - gpio-controller: Marks the device node as a gpio controller.
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| H A D | gpio-mm-lantiq.txt | 1 Lantiq SoC External Bus memory mapped GPIO controller
7 The node describing the memory mapped GPIOs needs to be a child of the node
11 - compatible : Should be "lantiq,gpio-mm-lantiq"
12 - reg : Address and length of the register set for the device
13 - #gpio-cells : Should be two. The first cell is the pin number and
16 - gpio-controller : Marks the device node as a gpio controller.
19 - lantiq,shadow : The default value that we shall assume as already set on the
20 shift register cascade.
25 #address-cells = <2>;
26 #size-cells = <1>;
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| /freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/ |
| H A D | pamu.txt | 5 The PAMU is an I/O MMU that provides device-to-memory access control and
10 - compatible : <string>
11 First entry is a version-specific string, such as
12 "fsl,pamu-v1.0". The second is "fsl,pamu".
13 - ranges : <prop-encoded-array>
14 A standard property. Utilized to describe the memory mapped
16 be set to the total size of the register space of all
20 - interrupts : <prop-encoded-array>
25 - #address-cells: <u32>
27 - #size-cells : <u32>
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | fixed-mmio-clock.txt | 1 Binding for simple memory mapped io fixed-rate clock sources.
2 The driver reads a clock frequency value from a single 32-bit memory mapped
3 I/O register and registers it as a fixed rate clock.
9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - compatible : shall be "fixed-mmio-clock".
13 - #clock-cells : from common clock binding; shall be set to 0.
14 - reg : Address and length of the clock value register set.
17 - clock-output-names : From common clock binding.
21 #clock-cells = <0>;
22 compatible = "fixed-mmio-clock";
|
| H A D | keystone-pll.txt | 3 and PAPLL are controlled by the memory mapped register where as the Main
4 PLL is controlled by a PLL controller registers along with memory mapped
9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - #clock-cells : from common clock binding; shall be set to 0.
13 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
14 - clocks : parent clock phandle
15 - reg - pll control0 and pll multiplier registers
16 - reg-names : control, multiplier and post-divider. The multiplier and
17 post-divider registers are applicable only for main pll clock
18 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
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| /freebsd/share/man/man4/ |
| H A D | proto.4 | 38 .Bd -ragged -offset indent
45 .Bd -literal -offset indent
51 .Bd -ragged -offset indent
62 Programs can open these device special files and perform register-level
72 Especially hardware diagnostics requires a somewhat user-friendly interface
111 .Bd -literal
117 .Ss Memory mapped I/O resources
118 The device special files created for memory mapped I/O resources behave
120 Additionally, device special files for memory mapped I/O resources allow
121 the memory to be mapped into the process' address space using
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| /freebsd/sys/dev/bhnd/bcma/ |
| H A D | bcma_subr.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
51 /* Return the resource ID for a device's agent register allocation */
74 cfg->core_info = (struct bhnd_core_info) { in bcma_alloc_corecfg()
82 STAILQ_INIT(&cfg->master_ports); in bcma_alloc_corecfg()
83 cfg->num_master_ports = 0; in bcma_alloc_corecfg()
85 STAILQ_INIT(&cfg->dev_ports); in bcma_alloc_corecfg()
86 cfg->num_dev_ports = 0; in bcma_alloc_corecfg()
88 STAILQ_INIT(&cfg->bridge_ports); in bcma_alloc_corecfg()
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| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_nb_regs.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
101 /* [0x6c] Read-only that reflects CPU Cluster Local GIC base high address */
103 /* [0x70] Read-only that reflects CPU Cluster Local GIC base low address */
105 /* [0x74] Read-only that reflects the device's IOGIC base high address. */
107 /* [0x78] Read-only that reflects IOGIC base low address */
334 /* [0x0] PMU Global Control Register */
336 /* [0x4] PMU Global Control Register */
341 /* [0x0] Counter Configuration Register */
343 /* [0x4] Counter Control Register */
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| /freebsd/sys/contrib/device-tree/Bindings/dma/ |
| H A D | adi,axi-dmac.txt | 1 Analog Devices AXI-DMAC DMA controller
4 - compatible: Must be "adi,axi-dmac-1.00.a".
5 - reg: Specification for the controllers memory mapped register map.
6 - interrupts: Specification for the controllers interrupt.
7 - clocks: Phandle and specifier to the controllers AXI interface clock
8 - #dma-cells: Must be 1.
10 Required sub-nodes:
11 - adi,channels: This sub-node must contain a sub-node for each DMA channel. For
12 the channel sub-nodes the following bindings apply. They must match the
15 Required properties for adi,channels sub-node:
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| /freebsd/sys/dev/liquidio/base/ |
| H A D | lio_mem_ops.h | 43 * Read a 64-bit value from a BAR1 mapped core memory address.
44 * @param oct - pointer to the octeon device.
45 * @param core_addr - the address to read from.
47 * The range_idx gives the BAR1 index register for the range of address
48 * in which core_addr is mapped.
50 * @return 64-bit value read from Core memory
56 * Read a 32-bit value from a BAR1 mapped core memory address.
57 * @param oct - pointer to the octeon device.
58 * @param core_addr - the address to read from.
60 * @return 32-bit value read from Core memory
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| /freebsd/share/man/man9/ |
| H A D | bhnd.9 | 1 .\" Copyright (c) 2015-2016 Landon Fuller <landonf@FreeBSD.org>
392 .Bd -literal
398 .Bd -literal
406 .Bd -literal
414 .Bd -literal
417 .Bd -literal
427 .Bd -literal
435 .Bd -literal
442 .Bd -literal
512 .Bd -literal
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| /freebsd/sys/contrib/device-tree/Bindings/arm/ |
| H A D | fw-cfg.txt | 3 QEMU's arm-softmmu and aarch64-softmmu emulation / virtualization targets
7 - A write-only, 16-bit wide selector (or control) register,
8 - a read-write, 64-bit wide data register.
10 QEMU exposes the control and data register to ARM guests as memory mapped
14 The authoritative guest-side hardware interface documentation to the fw_cfg
20 - compatible: "qemu,fw-cfg-mmio".
22 - reg: the MMIO region used by the device.
23 * Bytes 0x0 to 0x7 cover the data register.
24 * Bytes 0x8 to 0x9 cover the selector register.
31 #size-cells = <0x2>;
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