1*f173c2b7SSean Bruno /* 2*f173c2b7SSean Bruno * BSD LICENSE 3*f173c2b7SSean Bruno * 4*f173c2b7SSean Bruno * Copyright(c) 2017 Cavium, Inc.. All rights reserved. 5*f173c2b7SSean Bruno * All rights reserved. 6*f173c2b7SSean Bruno * 7*f173c2b7SSean Bruno * Redistribution and use in source and binary forms, with or without 8*f173c2b7SSean Bruno * modification, are permitted provided that the following conditions 9*f173c2b7SSean Bruno * are met: 10*f173c2b7SSean Bruno * 11*f173c2b7SSean Bruno * * Redistributions of source code must retain the above copyright 12*f173c2b7SSean Bruno * notice, this list of conditions and the following disclaimer. 13*f173c2b7SSean Bruno * * Redistributions in binary form must reproduce the above copyright 14*f173c2b7SSean Bruno * notice, this list of conditions and the following disclaimer in 15*f173c2b7SSean Bruno * the documentation and/or other materials provided with the 16*f173c2b7SSean Bruno * distribution. 17*f173c2b7SSean Bruno * * Neither the name of Cavium, Inc. nor the names of its 18*f173c2b7SSean Bruno * contributors may be used to endorse or promote products derived 19*f173c2b7SSean Bruno * from this software without specific prior written permission. 20*f173c2b7SSean Bruno * 21*f173c2b7SSean Bruno * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22*f173c2b7SSean Bruno * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23*f173c2b7SSean Bruno * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24*f173c2b7SSean Bruno * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25*f173c2b7SSean Bruno * OWNER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26*f173c2b7SSean Bruno * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27*f173c2b7SSean Bruno * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28*f173c2b7SSean Bruno * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29*f173c2b7SSean Bruno * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30*f173c2b7SSean Bruno * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31*f173c2b7SSean Bruno * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32*f173c2b7SSean Bruno */ 33*f173c2b7SSean Bruno 34*f173c2b7SSean Bruno /* 35*f173c2b7SSean Bruno * \file lio_mem_ops.h 36*f173c2b7SSean Bruno * \brief Host Driver: Routines used to read/write Octeon memory. 37*f173c2b7SSean Bruno */ 38*f173c2b7SSean Bruno 39*f173c2b7SSean Bruno #ifndef __LIO_MEM_OPS_H__ 40*f173c2b7SSean Bruno #define __LIO_MEM_OPS_H__ 41*f173c2b7SSean Bruno 42*f173c2b7SSean Bruno /* 43*f173c2b7SSean Bruno * Read a 64-bit value from a BAR1 mapped core memory address. 44*f173c2b7SSean Bruno * @param oct - pointer to the octeon device. 45*f173c2b7SSean Bruno * @param core_addr - the address to read from. 46*f173c2b7SSean Bruno * 47*f173c2b7SSean Bruno * The range_idx gives the BAR1 index register for the range of address 48*f173c2b7SSean Bruno * in which core_addr is mapped. 49*f173c2b7SSean Bruno * 50*f173c2b7SSean Bruno * @return 64-bit value read from Core memory 51*f173c2b7SSean Bruno */ 52*f173c2b7SSean Bruno uint64_t lio_read_device_mem64(struct octeon_device *oct, 53*f173c2b7SSean Bruno uint64_t core_addr); 54*f173c2b7SSean Bruno 55*f173c2b7SSean Bruno /* 56*f173c2b7SSean Bruno * Read a 32-bit value from a BAR1 mapped core memory address. 57*f173c2b7SSean Bruno * @param oct - pointer to the octeon device. 58*f173c2b7SSean Bruno * @param core_addr - the address to read from. 59*f173c2b7SSean Bruno * 60*f173c2b7SSean Bruno * @return 32-bit value read from Core memory 61*f173c2b7SSean Bruno */ 62*f173c2b7SSean Bruno uint32_t lio_read_device_mem32(struct octeon_device *oct, 63*f173c2b7SSean Bruno uint64_t core_addr); 64*f173c2b7SSean Bruno 65*f173c2b7SSean Bruno /* 66*f173c2b7SSean Bruno * Write a 32-bit value to a BAR1 mapped core memory address. 67*f173c2b7SSean Bruno * @param oct - pointer to the octeon device. 68*f173c2b7SSean Bruno * @param core_addr - the address to write to. 69*f173c2b7SSean Bruno * @param val - 32-bit value to write. 70*f173c2b7SSean Bruno */ 71*f173c2b7SSean Bruno void lio_write_device_mem32(struct octeon_device *oct, 72*f173c2b7SSean Bruno uint64_t core_addr, uint32_t val); 73*f173c2b7SSean Bruno 74*f173c2b7SSean Bruno /* Read multiple bytes from Octeon memory. */ 75*f173c2b7SSean Bruno void lio_pci_read_core_mem(struct octeon_device *oct, 76*f173c2b7SSean Bruno uint64_t coreaddr, uint8_t *buf, 77*f173c2b7SSean Bruno uint32_t len); 78*f173c2b7SSean Bruno 79*f173c2b7SSean Bruno /* Write multiple bytes into Octeon memory. */ 80*f173c2b7SSean Bruno void lio_pci_write_core_mem(struct octeon_device *oct, 81*f173c2b7SSean Bruno uint64_t coreaddr, uint8_t *buf, 82*f173c2b7SSean Bruno uint32_t len); 83*f173c2b7SSean Bruno 84*f173c2b7SSean Bruno #endif /* __LIO_MEM_OPS_H__ */ 85