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/linux/Documentation/devicetree/bindings/phy/
H A Dfsl,imx8-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Richard Zhu <hongxing.zhu@nxp.com>
13 "#phy-cells":
18 - fsl,imx8mm-pcie-phy
19 - fsl,imx8mp-pcie-phy
27 clock-names:
29 - const: ref
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H A Dfsl,imx8qm-hsio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-hsio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Richard Zhu <hongxing.zhu@nxp.com>
15 - fsl,imx8qm-hsio
16 - fsl,imx8qxp-hsio
19 - description: Base address and length of the PHY block
20 - description: HSIO control and status registers(CSR) of the PHY
21 - description: HSIO CSR of the controller bound to the PHY
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H A Dimg,pistachio-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/img,pistachio-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Bresticker <abrestic@chromium.org>
14 const: img,pistachio-usb-phy
19 clock-names:
21 - const: usb_phy
23 '#phy-cells':
26 phy-supply:
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H A Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
18 - ti,j721s2-wiz-10g
19 - ti,am64-wiz-10g
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H A Dphy-rockchip-naneng-combphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3528-naneng-combphy
16 - rockchip,rk3562-naneng-combphy
17 - rockchip,rk3568-naneng-combphy
18 - rockchip,rk3576-naneng-combphy
19 - rockchip,rk3588-naneng-combphy
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/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn314/
H A Ddcn314_dccg.c1 // SPDX-License-Identifier: MIT
38 (dccg_dcn->regs->reg)
42 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
45 dccg_dcn->base.ctx
47 dccg->ctx->logger
163 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
172 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
181 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
190 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
205 /* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */
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/linux/Documentation/devicetree/bindings/media/i2c/
H A Dtoshiba,tc358746.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marco Felsch <kernel@pengutronix.de>
12 description: |-
13 The Toshiba TC358746 converts a parallel video stream into a MIPI CSI-2
14 stream. The direction can be either parallel-in -> csi-out or csi-in ->
15 parallel-out The chip is programmable through I2C and SPI but the SPI
16 interface is only supported in parallel-in -> csi-out mode.
19 parallel-in -> csi-out path.
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/linux/arch/mips/boot/dts/cavium-octeon/
H A Ddlink_dsr-500n-1000n.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device tree source for D-Link DSR-500N/1000N (common parts).
13 phy8: ethernet-phy@8 {
15 compatible = "ethernet-phy-ieee802.3-c22";
22 fixed-link {
24 full-duplex;
28 fixed-link {
30 full-duplex;
34 phy-handle = <&phy8>;
47 refclk-frequency = <12000000>;
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H A Dubnt_e100.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device tree source for EdgeRouter Lite.
15 phy5: ethernet-phy@5 {
17 compatible = "ethernet-phy-ieee802.3-c22";
19 phy6: ethernet-phy@6 {
21 compatible = "ethernet-phy-ieee802.3-c22";
23 phy7: ethernet-phy@7 {
25 compatible = "ethernet-phy-ieee802.3-c22";
32 phy-handle = <&phy7>;
33 rx-delay = <0>;
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_cdclk.c2 * Copyright © 2006-2017 Intel Corporation
82 * - We have the CDCLK PLL, which generates an output clock based on a
84 * - The CD2X Divider, which divides the output of the PLL based on a
85 * divisor selected from a set of pre-defined choices.
86 * - The CD2X Squasher, which further divides the output based on a
89 * - And, finally, a fixed divider that divides the output frequency by 2.
108 * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive.
109 * - CD2X divider update. Single pipe can be active as the divider update
111 * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active.
112 * - Squash waveform update. Pipes can be active.
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/linux/arch/arm/boot/dts/samsung/
H A Dexynos4412-odroidu3.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel's Exynos4412 based ODROID-U3 board device tree source
7 * Device tree source file for Hardkernel's ODROID-U3 board which is based
11 /dts-v1/;
12 #include <dt-bindings/leds/common.h>
13 #include "exynos4412-odroid-common.dtsi"
14 #include "exynos4412-prime.dtsi"
17 model = "Hardkernel ODROID-U3 board based on Exynos4412";
18 compatible = "hardkernel,odroid-u3", "samsung,exynos4412", "samsung,exynos4";
29 vbus_otg_reg: regulator-1 {
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/linux/sound/soc/codecs/
H A Dcs530x.c1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (C) 2024-2025 Cirrus Logic, Inc. and
26 "vdd-a",
27 "vdd-io",
136 struct regmap *regmap = cs530x->regmap; in cs530x_put_volsw_vu()
154 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1270, 50, 0);
157 "Min Phase Slow Roll-off",
158 "Min Phase Fast Roll-off",
159 "Linear Phase Slow Roll-off",
160 "Linear Phase Fast Roll-off",
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H A Darizona.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arizona.c - Wolfson Arizona class device shared support
67 dev_err(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
69 dev_warn(_fll->arizona->de
1282 int ref, div, refclk; arizona_set_opclk() local
1366 arizona_set_sysclk(struct snd_soc_component * component,int clk_id,int source,unsigned int freq,int dir) arizona_set_sysclk() argument
2330 arizona_apply_fll(struct arizona * arizona,unsigned int base,struct arizona_fll_cfg * cfg,int source,bool sync) arizona_apply_fll() argument
2555 arizona_set_fll_refclk(struct arizona_fll * fll,int source,unsigned int Fref,unsigned int Fout) arizona_set_fll_refclk() argument
2579 arizona_set_fll(struct arizona_fll * fll,int source,unsigned int Fref,unsigned int Fout) arizona_set_fll() argument
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H A Dmadera.c1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright (C) 2015-2019 Cirrus Logic, Inc. and
19 #include <linux/irqchip/irq-madera.h>
23 #include <sound/madera-pdata.h>
25 #include <dt-bindings/sound/madera.h>
144 dev_err(_fll->madera->de
2508 int ref, div, refclk; madera_set_opclk() local
2628 madera_set_outclk(struct snd_soc_component * component,unsigned int source,unsigned int freq) madera_set_outclk() argument
2680 madera_set_sysclk(struct snd_soc_component * component,int clk_id,int source,unsigned int freq,int dir) madera_set_sysclk() argument
3716 madera_write_fll(struct madera * madera,unsigned int base,struct madera_fll_cfg * cfg,int source,bool sync,int gain) madera_write_fll() argument
4123 madera_set_fll_syncclk(struct madera_fll * fll,int source,unsigned int fref,unsigned int fout) madera_set_fll_syncclk() argument
4142 madera_set_fll_refclk(struct madera_fll * fll,int source,unsigned int fref,unsigned int fout) madera_set_fll_refclk() argument
4332 madera_set_fll_ao_refclk(struct madera_fll * fll,int source,unsigned int fin,unsigned int fout) madera_set_fll_ao_refclk() argument
4654 madera_fllhj_set_refclk(struct madera_fll * fll,int source,unsigned int fin,unsigned int fout) madera_fllhj_set_refclk() argument
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/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Ddccg.h43 …PHYSYMCLK_FORCE_SRC_SYMCLK, // Select symclk as source of clock which is output to PHY through …
44 …PHYSYMCLK_FORCE_SRC_PHYD18CLK, // Select phyd18clk as the source of clock which is output to PHY t…
45 …PHYSYMCLK_FORCE_SRC_PHYD32CLK, // Select phyd32clk as the source of clock which is output to PHY t…
49 REFCLK, // Selects REFCLK as source for hdmistreamclk. enumerator
50 DTBCLK0, // Selects DTBCLK0 as source for hdmistreamclk.
51 DPREFCLK, // Selects DPREFCLK as source for hdmistreamclk
227 void (*refclk_setup)(struct dccg *dccg); /* Deprecated - for backward compatibility only */
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
H A Ddcn20_dccg.c36 (dccg_dcn->regs->reg)
40 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
43 dccg_dcn->base.ctx
45 dccg->ctx->logger
51 if (dccg->ref_dppclk && req_dppclk) { in dccg2_update_dpp_dto()
52 int ref_dppclk = dccg->ref_dppclk; in dccg2_update_dpp_dto()
57 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; in dccg2_update_dpp_dto()
74 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg2_update_dpp_dto()
88 // DCN20 has never been validated for non-xtalin as reference in dccg2_get_dccg_ref_freq()
90 // frequency a non-xtalin source is. in dccg2_get_dccg_ref_freq()
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgt215.c45 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
50 return device->crystal; in read_vco()
63 struct nvkm_device *device = clk->base.subdev.device; in read_clk()
66 /* refclk for the 0xe8xx plls is a fixed frequency */ in read_clk()
68 if (device->chipset == 0xaf) { in read_clk()
73 return device->crystal; in read_clk()
88 return device->crystal; in read_clk()
110 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
122 /* no post-divider on these.. in read_pll()
123 * XXX: it looks more like two post-"dividers" that in read_pll()
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H A Dmcp77.c44 struct nvkm_device *device = clk->base.subdev.device; in read_div()
51 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
54 u32 ref = nvkm_clk_read(&clk->base, nv_clk_src_href); in read_pll()
84 struct nvkm_subdev *subdev = &clk->base.subdev; in mcp77_clk_read()
85 struct nvkm_device *device = subdev->device; in mcp77_clk_read()
91 return device->crystal; in mcp77_clk_read()
95 return nvkm_clk_read(&clk->base, nv_clk_src_href) * 4; in mcp77_clk_read()
97 return nvkm_clk_read(&clk->base, nv_clk_src_href) * 2 / 3; in mcp77_clk_read()
100 case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm2d3); in mcp77_clk_read()
102 case 0x00080000: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm4); in mcp77_clk_read()
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/linux/drivers/gpu/drm/bridge/
H A Dtc358767.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TC358767/TC358867/TC9595 DSI/DPI-to-DPI/(e)DP bridge driver
6 * All modes are supported -- DPI->(e)DP / DSI->DPI / DSI->(e)DP .
27 #include <linux/media-bus-format.h>
44 /* DSI D-PHY Layer registers */
77 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
110 #define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
184 #define VID_MN_GEN BIT(6) /* Auto-generate M/N values */
390 struct clk *refclk; member
398 /* HPD pin number (0 or 1) or -ENODEV */
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H A Dti-sn65dsi86.c1 // SPDX-License-Identifier: GPL-2.0
145 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver.
146 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality.
147 * @gpio_aux: AUX-bus sub device for GPIO controller functionality.
148 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality.
149 * @pwm_aux: AUX-bus sub device for PWM controller functionality.
157 * @dsi: Our MIPI DSI source.
158 * @refclk: Our reference clock.
164 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
172 * serves double-duty of keeping track of the direction and
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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6q-bosch-acc.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Support for the i.MX6-based Bosch ACC board.
8 * Copyright (C) 2019-2021 Bosch Thermotechnik GmbH, Matthias Winker <matthias.winker@bosch.com>
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/leds/common.h>
20 compatible = "bosch,imx6q-acc", "fsl,imx6q";
37 backlight_lvds: backlight-lvds {
38 compatible = "pwm-backlight";
40 brightness-levels = <0 61 499 1706 4079 8022 13938 22237 33328 47623 65535>;
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/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8m-pcie.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
20 #include <dt-bindings/phy/phy-imx8-pcie.h>
79 pad_mode = imx8_phy->refclk_pad_mode; in imx8_pcie_phy_power_on()
80 switch (imx8_phy->drvdata->variant) { in imx8_pcie_phy_power_on()
82 reset_control_assert(imx8_phy->reset); in imx8_pcie_phy_power_on()
84 /* Tune PHY de-emphasis setting to pass PCIe compliance. */ in imx8_pcie_phy_power_on()
85 if (imx8_phy->tx_deemph_gen1) in imx8_pcie_phy_power_on()
86 writel(imx8_phy->tx_deemph_gen1, in imx8_pcie_phy_power_on()
87 imx8_phy->base + PCIE_PHY_TRSV_REG5); in imx8_pcie_phy_power_on()
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/linux/arch/arm64/boot/dts/renesas/
H A Dr8a779a0-falcon-cpu.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Falcon CPU board
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/leds/common.h>
16 compatible = "renesas,falcon-cpu", "renesas,r8a779a0";
30 stdout-path = "serial0:115200n8";
34 compatible = "gpio-keys";
36 pinctrl-0 = <&keys_pins>;
37 pinctrl-names = "default";
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-dhcom-pdk2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 * DHCM-iMX8ML8-C160-R409-F1638-SPI16-GE-CAN2-SD-RTC-WBTA-ADC-T-RGB-CSI2-HS-I-01D2
7 * DHCOM PCB number: 660-100 or newer
8 * PDK2 PCB number: 516-400 or newer
11 /dts-v1/;
13 #include <dt-bindings/leds/common.h>
14 #include <dt-bindings/phy/phy-imx8-pcie.h>
15 #include "imx8mp-dhcom-som.dtsi"
19 compatible = "dh,imx8mp-dhcom-pdk2", "dh,imx8mp-dhcom-som",
23 stdout-path = &uart1;
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/linux/drivers/usb/dwc3/
H A Ddwc3-am62.c1 // SPDX-License-Identifier: GPL-2.0
3 * dwc3-am62.c - TI specific Glue layer for AM62 DWC3 USB Controller
5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com
144 return readl((am62->usbss) + offset); in dwc3_ti_readl()
149 writel(value, (am62->usbss) + offset); in dwc3_ti_writel()
154 struct device *dev = am62->dev; in phy_syscon_pll_refclk()
155 struct device_node *node = dev->of_node; in phy_syscon_pll_refclk()
159 syscon = syscon_regmap_lookup_by_phandle_args(node, "ti,syscon-phy-pll-refclk", in phy_syscon_pll_refclk()
160 1, &am62->offset); in phy_syscon_pll_refclk()
162 dev_err(dev, "unable to get ti,syscon-phy-pll-refclk regmap\n"); in phy_syscon_pll_refclk()
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