| /linux/Documentation/infiniband/ |
| H A D | tag_matching.rst | 14 The ordering rules require that when more than one pair of send and receive
16 and the earliest posted-receive is the pair that must be used to satisfy the
23 corresponding matching receive is posted. If a matching receive is posted,
44 There are two types of matching objects used, the posted receive list and the
45 unexpected message list. The application posts receive buffers through calls
46 to the MPI receive routines in the posted receive list and posts send messages
47 using the MPI send routines. The head of the posted receive list may be
50 When send is initiated and arrives at the receive side, if there is no
51 pre-posted receive for this arriving message, it is passed to the software and
54 specified receive buffer. This allows overlapping receive-side MPI tag
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| /linux/sound/soc/fsl/ |
| H A D | fsl_sai.h | 51 #define FSL_SAI_RCSR(ofs) (0x80 + ofs) /* SAI Receive Control */
52 #define FSL_SAI_RCR1(ofs) (0x84 + ofs)/* SAI Receive Configuration 1 */
53 #define FSL_SAI_RCR2(ofs) (0x88 + ofs) /* SAI Receive Configuration 2 */
54 #define FSL_SAI_RCR3(ofs) (0x8c + ofs) /* SAI Receive Configuration 3 */
55 #define FSL_SAI_RCR4(ofs) (0x90 + ofs) /* SAI Receive Configuration 4 */
56 #define FSL_SAI_RCR5(ofs) (0x94 + ofs) /* SAI Receive Configuration 5 */
57 #define FSL_SAI_RDR0 0xa0 /* SAI Receive Data 0 */
58 #define FSL_SAI_RDR1 0xa4 /* SAI Receive Data 1 */
59 #define FSL_SAI_RDR2 0xa8 /* SAI Receive Data 2 */
60 #define FSL_SAI_RDR3 0xac /* SAI Receive Dat
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| /linux/include/linux/spi/ |
| H A D | sh_msiof.h | 11 #define SIRMDR1 0x10 /* Receive Mode Register 1 */
12 #define SIRMDR2 0x14 /* Receive Mode Register 2 */
13 #define SIRMDR3 0x18 /* Receive Mode Register 3 */
15 #define SIRSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
23 #define SIRDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
24 #define SIRDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
25 #define SIRFDR 0x60 /* Receive FIFO Data Register */
62 #define SICTR_RSCKIZ GENMASK(29, 28) /* Receive Clock Polarity Select */
64 #define SICTR_RSCKIZ_POL BIT(28) /* Receive Clock Polarity */
66 #define SICTR_REDG BIT(26) /* Receive Timing (1 = falling edge) */
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| /linux/drivers/net/ethernet/apple/ |
| H A D | bmac.h | 22 # define MIIBuffDisable 0x0008 /* MII receive buffer disable */
31 #define RXFIFOCSR 0x120 /* receive FIFO control */
47 #define RXPNTR 0x1b0 /* receive pointer */
52 # define RxFrameCntExp 0x00000002 /* Receive frame counter expired */
56 # define RxOverFlow 0x00000020 /* Receive FIFO overflow */
68 # define RxNoDescriptors 0x00020000 /* No more receive descriptors */
69 # define RxDMAError 0x00040000 /* Error during receive DMA */
70 # define RxDMALateErr 0x00080000 /* Receive DMA, data late */
71 # define RxParityErr 0x00100000 /* Parity error during receive DMA */
72 # define RxTagError 0x00200000 /* Tag error during receive DMA */
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| H A D | mace.h | 12 REG(rcvfifo); /* receive FIFO */
17 REG(rcvfc); /* receive frame control */
18 REG(rcvfs); /* receive frame status (4 bytes) */
66 #define LLRCV 0x08 /* low latency receive: early DMA request */
76 * Byte 3: receive collision count
78 #define RS_OFLO 0x8000 /* receive FIFO overflowed */
85 #define RCVFC_SH 4 /* receive frame count in FIFO */
100 #define RCVINT 0x02 /* receive interrupt */
126 #define RCVBRST 0x01 /* enable receive burst mode */
150 #define LRT 0x08 /* low receive threshold for long links */
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| /linux/drivers/net/ethernet/actions/ |
| H A D | owl-emac.h | 35 /* Transmit/receive poll demand registers */
41 /* Receive/transmit descriptor list base address registers */
51 #define OWL_EMAC_MSK_MAC_CSR5_RS GENMASK(19, 17) /* Receive process state */
53 #define OWL_EMAC_VAL_MAC_CSR5_RS_FDES 0x01 /* Fetching receive descriptor */
54 #define OWL_EMAC_VAL_MAC_CSR5_RS_CDES 0x05 /* Closing receive descriptor */
58 #define OWL_EMAC_BIT_MAC_CSR5_ERI BIT(14) /* Early receive interrupt */
61 #define OWL_EMAC_BIT_MAC_CSR5_RPS BIT(8) /* Receive process stopped */
62 #define OWL_EMAC_BIT_MAC_CSR5_RU BIT(7) /* Receive buffer unavailable */
63 #define OWL_EMAC_BIT_MAC_CSR5_RI BIT(6) /* Receive interrupt */
73 #define OWL_EMAC_BIT_MAC_CSR6_RA BIT(30) /* Receive all */
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| /linux/drivers/net/ethernet/amd/ |
| H A D | ariadne.h | 78 #define CSR18 0x1200 /* Current Receive Buffer Address */
79 #define CSR19 0x1300 /* Current Receive Buffer Address */
82 #define CSR22 0x1600 /* Next Receive Buffer Address */
83 #define CSR23 0x1700 /* Next Receive Buffer Address */
84 #define CSR24 0x1800 /* - Base Address of Receive Ring */
85 #define CSR25 0x1900 /* - Base Address of Receive Ring */
86 #define CSR26 0x1a00 /* Next Receive Descriptor Address */
87 #define CSR27 0x1b00 /* Next Receive Descriptor Address */
88 #define CSR28 0x1c00 /* Current Receive Descriptor Address */
89 #define CSR29 0x1d00 /* Current Receive Descriptor Address */
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| /linux/drivers/net/ethernet/freescale/enetc/ |
| H A D | enetc4_hw.h | 235 /* Port MAC 0/1 Receive Ethernet Octets Counter */
238 /* Port MAC 0/1 Receive Octets Counter */
241 /* Port MAC 0/1 Receive Alignment Error Counter Register */
244 /* Port MAC 0/1 Receive Valid Pause Frame Counter */
247 /* Port MAC 0/1 Receive Frame Counter */
250 /* Port MAC 0/1 Receive Frame Check Sequence Error Counter */
253 /* Port MAC 0/1 Receive VLAN Frame Counter */
256 /* Port MAC 0/1 Receive Frame Error Counter */
259 /* Port MAC 0/1 Receive Unicast Frame Counter */
262 /* Port MAC 0/1 Receive Multicast Frame Counter */
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| /linux/include/uapi/rdma/ |
| H A D | ib_user_mad.h | 56 * @status - 0 on successful receive, ETIMEDOUT if no response
59 * @timeout_ms - Milliseconds to wait for response (unset on receive)
62 * @qkey - Remote Q_Key to be sent with (unset on receive)
67 * @gid_index - Local GID index to send with (unset on receive)
99 * @status - 0 on successful receive, ETIMEDOUT if no response
102 * @timeout_ms - Milliseconds to wait for response (unset on receive)
105 * @qkey - Remote Q_Key to be sent with (unset on receive)
110 * @gid_index - Local GID index to send with (unset on receive)
173 * @method_mask - The caller will receive unsolicited MADs for any method
175 * @mgmt_class - Indicates which management class of MADs should be receive
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| /linux/Documentation/networking/ |
| H A D | oa-tc6-framework.rst | 59 receive (RX) chunks. Chunks in both transmit and receive directions may
69 In parallel, receive data chunks are received on MISO. Each receive data
71 The data footer indicates if there is receive frame data present within
184 NORX (Bit 29) - No Receive flag. The SPI host may set this bit to prevent
189 any receive frame data within the current chunk.
200 chunk payload. Note that the receive path is unaffected by
254 host will be sent as multiple receive data chunks. Each receive data
257 location of the receive frame data within the 64 bytes data chunk payload.
284 RCA (Bit 28..24) - Receive Chunks Available. The RCA field indicates to
285 the SPI host the minimum number of additional receive
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| H A D | kcm.rst | 9 can efficiently send and receive application protocol messages over TCP using
47 Similarly, in the receive path, messages are constructed on each TCP socket
55 messages on receive as well as other connection specific information for KCM.
63 can be used to send and receive messages from the KCM socket.
98 KCM limits the maximum receive message size to be the size of the receive
105 A timeout may be set for assembling messages on a receive socket. The timeout
106 value is taken from the receive timeout of the attached TCP socket (this is set
189 Disabling receive on KCM socket
193 When receive is disabled, any pending messages in the socket's
194 receive buffer are moved to other sockets. This feature is useful
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| /linux/drivers/net/ethernet/freescale/fman/ |
| H A D | fman_mac.h | 98 /* 10GEC, mEMAC Receive FIFO overflow interrupt */
100 /* 10GEC, mEMAC Receive frame ECC error interrupt */
102 /* 10GEC Receive jabber frame interrupt */
104 /* 10GEC Receive oversized frame interrupt */
106 /* 10GEC Receive runt frame interrupt */
108 /* 10GEC Receive fragment frame interrupt */
110 /* 10GEC Receive payload length error interrupt */
112 /* 10GEC Receive CRC error interrupt */
114 /* 10GEC Receive alignment error interrupt */
116 /* dTSEC Babbling receive error */
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| /linux/drivers/net/ethernet/sun/ |
| H A D | sunhme.h | 37 #define GREG_STAT_RCNTEXP 0x00000002 /* Receive frame counter expired */
41 #define GREG_STAT_RFIFOVF 0x00000020 /* Receive FIFO overflow */
52 #define GREG_STAT_RXTOHOST 0x00010000 /* Moved from receive-FIFO to host memory */
53 #define GREG_STAT_NORXD 0x00020000 /* No more receive descriptors */
54 #define GREG_STAT_RXERR 0x00040000 /* Error during receive dma */
55 #define GREG_STAT_RXLATERR 0x00080000 /* Late error during receive dma */
56 #define GREG_STAT_RXPERR 0x00100000 /* Parity error during receive dma */
57 #define GREG_STAT_RXTERR 0x00200000 /* Tag error during receive dma */
74 #define GREG_IMASK_RCNTEXP 0x00000002 /* Receive frame counter expired */
78 #define GREG_IMASK_RFIFOVF 0x00000020 /* Receive FIFO overflow */
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| /linux/drivers/staging/greybus/ |
| H A D | log.c | 22 struct gb_log_send_log_request *receive; in gb_log_request_handler() local
31 if (op->request->payload_size < sizeof(*receive)) { in gb_log_request_handler()
33 op->request->payload_size, sizeof(*receive)); in gb_log_request_handler()
36 receive = op->request->payload; in gb_log_request_handler()
37 len = le16_to_cpu(receive->len); in gb_log_request_handler()
38 if (len != (op->request->payload_size - sizeof(*receive))) { in gb_log_request_handler()
40 (op->request->payload_size - sizeof(*receive))); in gb_log_request_handler()
54 receive->msg[len - 1] = '\0'; in gb_log_request_handler()
60 dev_dbg(dev, "%s", receive->msg); in gb_log_request_handler()
|
| /linux/Documentation/networking/device_drivers/can/freescale/ |
| H A D | flexcan.rst | 19 and i.MX53 SOCs) only receive RTR frames if the controller is
30 With the "rx-rtr" private flag the ability to receive RTR frames can
31 be waived at the expense of losing the ability to receive RTR
35 Receive RTR frames. (default)
37 The CAN controller can and will receive RTR frames.
39 On some IP cores the controller cannot receive RTR frames in the
45 Waive ability to receive RTR frames. (not supported on all IP cores)
|
| /linux/drivers/net/ethernet/moxa/ |
| H A D | moxart_ether.h | 48 #define RX_DESC0_ODD_NB 0x400000 /* receive odd nibbles */
49 #define RX_DESC0_LRS 0x10000000 /* last receive segment */
50 #define RX_DESC0_FRS 0x20000000 /* first receive segment */
122 #define NORXBUF BIT(1) /* receive buffer unavailable */
127 #define RPKT_SAV BIT(6) /* FIFO receive success */
128 #define RPKT_LOST_INT_STS BIT(7) /* FIFO full, receive failed */
172 #define RX_BROADPKT BIT(17) /* receive broadcast packets */
173 #define RX_MULTIPKT BIT(16) /* receive all multicast packets */
181 #define ENRX_IN_HALFTX BIT(6) /* enable receive in half duplex mode */
186 #define RDMA_EN BIT(1) /* enable receive DMA chan */
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| /linux/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | mpic-msgr.txt | 25 - mpic-msgr-receive-mask: Specifies what registers in the containing block
26 are allowed to receive interrupts. The value is a bit mask where a set
27 bit at bit 'n' indicates that message register 'n' can receive interrupts.
50 // Message registers 0 and 2 in this block can receive interrupts on
53 mpic-msgr-receive-mask = <0x5>;
59 // Message registers 0 and 2 in this block can receive interrupts on
62 mpic-msgr-receive-mask = <0x5>;
|
| /linux/tools/testing/selftests/net/can/ |
| H A D | test_raw_filter.c | 104 /* Receive all frames when filtering for the ID in standard frame format */
160 /* Receive only SFF frames when expecting no EFF flag */
172 /* Receive only EFF frames when filter id and filter mask include EFF flag */
184 /* Receive only SFF frames when expecting no EFF flag, ignoring RTR flag */
196 /* Receive only EFF frames when filter id and filter mask include EFF flag,
210 /* Receive no remote frames when filtering for no RTR flag */
222 /* Receive no remote frames when filtering for no RTR flag, ignoring EFF flag */
234 /* Receive only remote frames when filter includes RTR flag */
246 /* Receive only remote frames when filter includes RTR flag, ignoring EFF
260 /* Receive only SFF data frame when filtering for no flags */
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| /linux/Documentation/networking/device_drivers/ethernet/microsoft/ |
| H A D | netvsc.rst | 23 Receive Side Scaling
25 Hyper-V supports receive side scaling. For TCP & UDP, packets can
51 Generic Receive Offload, aka GRO
57 Large Receive Offload (LRO), or Receive Side Coalescing (RSC)
83 Receive Buffer
85 Packets are received into a receive area which is created when device
86 is probed. The receive area is broken into MTU sized chunks and each may
87 contain one or more packets. The number of receive sections may be changed
|
| /linux/drivers/net/ethernet/freescale/ |
| H A D | gianfar.h | 599 u8 rq; /* Receive Queue index */
613 u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */
614 u32 tr127; /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */
615 u32 tr255; /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */
616 u32 tr511; /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */
617 u32 tr1k; /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */
618 u32 trmax; /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */
619 u32 trmgv; /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
620 u32 rbyt; /* 0x.69c - Receive Byte Counter */
621 u32 rpkt; /* 0x.6a0 - Receive Packet Counter */
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| /linux/drivers/net/ethernet/mellanox/mlxbf_gige/ |
| H A D | mlxbf_gige_rx.c | 3 /* Packet receive logic for Mellanox Gigabit Ethernet driver
40 /* Enable MAC receive filter mask for specified index */ in mlxbf_gige_enable_mac_rx_filter()
52 /* Disable MAC receive filter mask for specified index */ in mlxbf_gige_disable_mac_rx_filter()
112 /* Receive Initialization
115 * 3) Initializes each element of RX WQE array with a receive
118 * 5) Completes other misc receive initialization
140 * Each RX WQE is simply a receive buffer pointer, so walk in mlxbf_gige_rx_init()
186 /* Clear MLXBF_GIGE_INT_MASK 'receive pkt' bit to in mlxbf_gige_rx_init()
187 * indicate readiness to receive interrupts in mlxbf_gige_rx_init()
213 /* Receive Deinitialization
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| /linux/include/linux/ |
| H A D | atmel-ssc.h | 50 /* SSC Receive Clock Mode Register */
69 /* SSC Receive Frame Mode Register */
134 /* SSC Receive Hold Register */
144 /* SSC Receive Sync. Holding Register */
154 /* SSC Receive Compare 0 Register */
159 /* SSC Receive Compare 1 Register */
276 /* SSC PDC Receive Pointer Register */
279 /* SSC PDC Receive Counter Register */
285 /* SSC PDC Receive Next Pointer Register */
288 /* SSC PDC Receive Next Counter Register */
|
| /linux/arch/mips/include/asm/dec/ |
| H A D | ioasic_ints.h | 31 #define IO_INR_SCC0A_RXDMA 29 /* SCC0A receive half page */
32 #define IO_INR_SCC0A_RXERR 28 /* SCC0A receive overrun */
41 #define IO_INR_SCC1A_RXDMA 25 /* SCC1A receive half page */
42 #define IO_INR_SCC1A_RXERR 24 /* SCC1A receive overrun */
51 #define IO_INR_AB_RXDMA 25 /* ACCESS.bus receive half page */
52 #define IO_INR_AB_RXERR 24 /* ACCESS.bus receive overrun */
|
| /linux/drivers/net/ethernet/oki-semi/pch_gbe/ |
| H A D | pch_gbe.h | 93 #define PCH_GBE_INT_RX_DMA_CMPLT 0x00000001 /* Receive DMA Transfer Complete */
94 #define PCH_GBE_INT_RX_VALID 0x00000002 /* MAC Normal Receive Complete */
95 #define PCH_GBE_INT_RX_FRAME_ERR 0x00000004 /* Receive frame error */
96 #define PCH_GBE_INT_RX_FIFO_ERR 0x00000008 /* Receive FIFO Overflow */
97 #define PCH_GBE_INT_RX_DMA_ERR 0x00000010 /* Receive DMA Transfer Error */
98 #define PCH_GBE_INT_RX_DSC_EMP 0x00000020 /* Receive Descriptor Empty */
128 #define PCH_GBE_MRE_MAC_RX_EN 0x00000001 /* MAC Receive Enable */
140 /* Receive Almost Empty Threshold */
145 /* Receive Almost Full Threshold */
160 /* Receive Descriptor bit definitions */
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| /linux/drivers/infiniband/hw/hfi1/ |
| H A D | exp_rcv.c | 20 * hfi1_exp_tid_group_init - initialize rcd expected receive
31 * hfi1_alloc_ctxt_rcv_groups - initialize expected receive groups
61 * hfi1_free_ctxt_rcv_groups - free expected receive groups
64 * The routine dismantles the expect receive linked
65 * list and clears any tids associated with the receive
|