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/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dqcom,spi-qcom-qspi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Quad Serial Peripheral Interface (QSPI)
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 description: The QSPI controller allows SPI protocol communication in single,
17 - $ref: /schemas/spi/spi-controller.yaml#
22 - enum:
23 - qcom,sc7180-qspi
[all …]
/freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga_arria10_socdk_qspi.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
9 &qspi {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 compatible = "micron,mt25qu02g", "jedec,spi-nor";
17 spi-ma
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp-zc1275-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2021, Xilinx, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
18 compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";
23 spi0 = &qspi;
28 stdout-path = "serial0:115200n8";
45 &qspi {
48 compatible = "m25p80", "jedec,spi-nor";
50 spi-tx-bus-width = <1>;
[all …]
H A Dzynqmp-zcu1275-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2021, Xilinx, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
18 compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp";
23 spi0 = &qspi;
28 stdout-path = "serial0:115200n8";
45 &qspi {
48 compatible = "m25p80", "jedec,spi-nor";
50 spi-tx-bus-width = <4>;
[all …]
H A Dzynqmp-zc1254-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
18 compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp";
23 spi0 = &qspi;
28 stdout-path = "serial0:115200n8";
41 &qspi {
44 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
45 #address-cells = <1>;
[all …]
H A Dzynqmp-zc1232-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2021, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
17 compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";
22 spi0 = &qspi;
27 stdout-path = "serial0:115200n8";
40 &qspi {
43 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
44 #address-cells = <1>;
[all …]
H A Dzynqmp-zc1751-xm018-dc4.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm018-dc4
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-cc
[all...]
/freebsd/sys/dts/arm/
H A Dsocfpga_arria10_socdk_sdmmc.dts1 /*-
6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
31 /dts-v1/;
36 compatible = "altr,socfpga-arria10", "altr,socfpga";
44 clock-frequency = <200000000>;
49 compatible = "arm,cortex-a9-global-timer";
52 clock-frequency = <200000000>;
63 clock-frequency = < 50000000 >;
68 num-slots = <1>;
69 cap-sd-highspeed;
[all …]
/freebsd/sys/contrib/device-tree/src/mips/brcm/
H A Dbcm7420.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <93750000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
[all …]
H A Dbcm97358svmb.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include "bcm97xxx-nand-cs1-bch4.dtsi"
18 stdout-path = &uart0;
78 &qspi {
84 spi-max-frequency = <40000000>;
85 spi-cpol;
86 spi-cpha;
87 use-bspi;
88 m25p,fast-read;
[all …]
H A Dbcm97360svmb.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
17 stdout-path = &uart0;
81 &qspi {
87 spi-max-frequency = <40000000>;
88 spi-cpol;
89 spi-cpha;
90 use-bspi;
91 m25p,fast-read;
94 compatible = "fixed-partitions";
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/keystone/
H A Dkeystone-k2g-ice.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
7 /dts-v1/;
9 #include "keystone-k2g.dtsi"
10 #include <dt-bindings/net/ti-dp83867.h>
13 compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone";
21 reserved-memory {
22 #address-cells = <2>;
23 #size-cells = <2>;
26 dsp_common_memory: dsp-common-memory@81f800000 {
[all …]
H A Dkeystone-k2g-evm.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
7 /dts-v1/;
9 #include "keystone-k2g.dtsi"
12 compatible = "ti,k2g-evm", "ti,k2g", "ti,keystone";
20 reserved-memor
[all...]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam437x-idk-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
9 #include <dt-bindings/pinctrl/am43xx.h>
10 #include <dt-bindings/pwm/pwm.h>
11 #include <dt-binding
[all...]
H A Ddra72-evm-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include "dra7-ipu-ds
[all...]
H A Dam574x-idk.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
7 /dts-v1/;
10 #include "dra7-mmc-iodelay.dtsi"
11 #include "dra76x-mmc-iodelay.dtsi"
12 #include "am572x-idk-common.dtsi"
16 compatible = "ti,am5748-idk", "ti,am5748", "ti,dra762", "ti,dra7";
19 &qspi {
20 spi-max-frequency = <96000000>;
22 spi-max-frequency = <96000000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1012a-frwy.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 /dts-v1/;
12 #include "fsl-ls1012a.dtsi"
16 compatible = "fsl,ls1012a-frwy", "fsl,ls1012a";
31 &qspi {
35 compatible = "jedec,spi-nor";
36 #address-cells = <1>;
37 #size-cells = <1>;
38 m25p,fast-read;
39 spi-max-frequency = <50000000>;
[all …]
H A Dfsl-ls1012a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include "fsl-ls1012a.dtsi"
15 compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
29 sd-uhs-sdr104;
30 sd-uhs-sdr50;
31 sd-uhs-sdr25;
32 sd-uhs-sdr12;
37 mmc-hs200-1_8v;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/microchip/
H A Dat91-sam9x60ek.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * at91-sam9x60ek.dts - Device Tree file for Microchip SAM9X60-EK board
9 /dts-v1/;
11 #include <dt-bindings/input/input.h>
14 model = "Microchip SAM9X60-E
[all...]
H A Dat91-sama5d2_icp.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * at91-sama5d2_icp.dts - Device Tree file for SAMA5D2-ICP board
11 /dts-v1/;
13 #include "sama5d2-pinfunc.h"
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/mfd/atmel-flexcom.h>
19 model = "Microchip SAMA5D2-ICP";
20 compatible = "microchip,sama5d2-icp", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
32 stdout-path = "serial0:115200n8";
[all …]
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstm32mp157c-phycore-stm32mp1-3.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved
7 /dts-v1/;
9 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
12 #include "stm32mp15xxac-pinctrl.dtsi"
13 #include "stm32mp157c-phycore-stm32mp15-som.dtsi"
16 model = "PHYTEC phyCORE-STM32MP1-3 Dev Board";
17 compatible = "phytec,phycore-stm32mp1-3",
18 "phytec,phycore-stm32mp157c-som", "st,stm32mp157";
54 &qspi {
/freebsd/sys/contrib/device-tree/src/arm/renesas/
H A Dr8a7792-wheat.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
24 stdout-path = "serial0:115200n8";
32 d1_8v: regulator-1v8 {
33 compatible = "regulator-fixe
[all...]
H A Dr8a7790-stout.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
23 stdout-path = "serial0:115200n8";
32 compatible = "gpio-leds";
47 fixedregulator1v8: regulator-
[all...]
/freebsd/sys/contrib/device-tree/src/arm/mediatek/
H A Dmt7629-rfb.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
8 #include <dt-bindings/input/input.h>
13 compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
20 stdout-path = "serial0:115200n8";
23 gpio-keys {
24 compatible = "gpio-key
[all...]
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm53340-ubnt-unifi-switch8.dts9 /dts-v1/;
11 #include "bcm-hr2.dtsi"
14 compatible = "ubnt,unifi-switch8", "brcm,bcm53342", "brcm,hr2";
33 &qspi {
35 bspi-sel = <0>;
40 #address-cells = <1>;
41 #size-cells = <1>;
42 spi-max-frequency = <12500000>;
43 spi-cpol;
44 spi-cpha;
[all …]

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