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/linux/Documentation/devicetree/bindings/regulator/
H A Dst,stm32mp1-pwr-reg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/st,stm32mp1-pwr-reg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STM32MP1 PWR voltage regulators
10 - Pascal Paillet <p.paillet@foss.st.com>
15 - items:
16 - const: st,stm32mp1,pwr-reg
17 - items:
18 - const: st,stm32mp13-pwr-reg
[all …]
/linux/drivers/input/misc/
H A Dtps65218-pwrbutton.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
7 * Author: Marcin Niestroj <m.niestroj@grinn-global.com>
49 { .compatible = "ti,tps65217-pwrbutton", .data = &tps65217_data },
50 { .compatible = "ti,tps65218-pwrbutton", .data = &tps65218_data },
57 struct tps6521x_pwrbutton *pwr = _pwr; in tps6521x_pb_irq() local
58 const struct tps6521x_data *tps_data = pwr->data; in tps6521x_pb_irq()
59 unsigned int reg; in tps6521x_pb_irq() local
62 error = regmap_read(pwr->regmap, tps_data->reg_status, &reg); in tps6521x_pb_irq()
64 dev_err(pwr->dev, "can't read register: %d\n", error); in tps6521x_pb_irq()
[all …]
H A Dpmic8xxx-pwrkey.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
71 * struct pmic8xxx_pwrkey - pmic8xxx pwrkey information
84 struct input_dev *pwr = _pwr; in pwrkey_press_irq() local
86 input_report_key(pwr, KEY_POWER, 1); in pwrkey_press_irq()
87 input_sync(pwr); in pwrkey_press_irq()
94 struct input_dev *pwr = _pwr; in pwrkey_release_irq() local
96 input_report_key(pwr, KEY_POWER, 0); in pwrkey_release_irq()
97 input_sync(pwr); in pwrkey_release_irq()
107 enable_irq_wake(pwrkey->key_press_irq); in pmic8xxx_pwrkey_suspend()
[all …]
/linux/Documentation/devicetree/bindings/rtc/
H A Disil,isl12026.txt5 at bus address 0x57. The canonical "reg" value will be for the RTC portion.
9 - "compatible": must be "isil,isl12026"
10 - "reg": I2C bus address of the device (always 0x6f)
14 - "isil,pwr-bsw": If present PWR.BSW bit must be set to the specified
17 - "isil,pwr-sbib": If present PWR.SBIB bit must be set to the specified
25 reg = <0x6f>;
26 isil,pwr-bsw = <0>;
27 isil,pwr-sbib = <1>;
/linux/drivers/phy/samsung/
H A Dphy-s5pv210-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SoC USB 1.1/2.0 PHY driver - S5PV210 support
12 #include "phy-samsung-usb2.h"
70 static int s5pv210_rate_to_clk(unsigned long rate, u32 *reg) in s5pv210_rate_to_clk() argument
74 *reg = S5PV210_UPHYCLK_PHYFSEL_12MHZ; in s5pv210_rate_to_clk()
77 *reg = S5PV210_UPHYCLK_PHYFSEL_24MHZ; in s5pv210_rate_to_clk()
80 *reg = S5PV210_UPHYCLK_PHYFSEL_48MHZ; in s5pv210_rate_to_clk()
83 return -EINVAL; in s5pv210_rate_to_clk()
91 struct samsung_usb2_phy_driver *drv = inst->drv; in s5pv210_isol()
94 switch (inst->cfg->id) { in s5pv210_isol()
[all …]
H A Dphy-exynos4210-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 4210 support
13 #include "phy-samsung-usb2.h"
87 /* Mode switching SUB Device <-> Host */
105 static int exynos4210_rate_to_clk(unsigned long rate, u32 *reg) in exynos4210_rate_to_clk() argument
109 *reg = EXYNOS_4210_UPHYCLK_PHYFSEL_12MHZ; in exynos4210_rate_to_clk()
112 *reg = EXYNOS_4210_UPHYCLK_PHYFSEL_24MHZ; in exynos4210_rate_to_clk()
115 *reg = EXYNOS_4210_UPHYCLK_PHYFSEL_48MHZ; in exynos4210_rate_to_clk()
118 return -EINVAL; in exynos4210_rate_to_clk()
126 struct samsung_usb2_phy_driver *drv = inst->drv; in exynos4210_isol()
[all …]
H A Dphy-exynos4x12-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 4x12 support
13 #include "phy-samsung-usb2.h"
114 /* Mode switching SUB Device <-> Host */
132 static int exynos4x12_rate_to_clk(unsigned long rate, u32 *reg) in exynos4x12_rate_to_clk() argument
138 *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_9MHZ6; in exynos4x12_rate_to_clk()
141 *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_10MHZ; in exynos4x12_rate_to_clk()
144 *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_12MHZ; in exynos4x12_rate_to_clk()
147 *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_19MHZ2; in exynos4x12_rate_to_clk()
150 *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_20MHZ; in exynos4x12_rate_to_clk()
[all …]
/linux/Documentation/devicetree/bindings/soc/tegra/
H A Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
19 - nvidia,tegra124-pmc
[all …]
/linux/drivers/rtc/
H A Drtc-isl12026.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/nvmem-provider.h>
42 static int isl12026_read_reg(struct i2c_client *client, int reg) in isl12026_read_reg() argument
44 u8 addr[] = {0, reg}; in isl12026_read_reg()
50 .addr = client->addr, in isl12026_read_reg()
55 .addr = client->addr, in isl12026_read_reg()
62 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); in isl12026_read_reg()
64 dev_err(&client->dev, "read reg error, ret=%d\n", ret); in isl12026_read_reg()
65 ret = ret < 0 ? ret : -EIO; in isl12026_read_reg()
78 .addr = client->addr, in isl12026_arm_write()
[all …]
/linux/drivers/soc/tegra/
H A Dflowctrl.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
74 unsigned int reg; in flowctrl_cpu_suspend_enter() local
77 reg = flowctrl_read_cpu_csr(cpuid); in flowctrl_cpu_suspend_enter()
81 reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP; in flowctrl_cpu_suspend_enter()
83 reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP; in flowctrl_cpu_suspend_enter()
84 /* pwr gating on wfe */ in flowctrl_cpu_suspend_enter()
85 reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid; in flowctrl_cpu_suspend_enter()
91 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; in flowctrl_cpu_suspend_enter()
93 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; in flowctrl_cpu_suspend_enter()
[all …]
/linux/drivers/mmc/host/
H A Dsdhci-pci-gli.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Version: v0.9.0 (2019-08-08)
18 #include "sdhci-cqhci.h"
19 #include "sdhci-pci.h"
21 #include "sdhci-uhs2.h"
468 if (!host->tuning_done) { in __sdhci_execute_tuning_9750()
481 if (!host->tuning_done) { in __sdhci_execute_tuning_9750()
483 mmc_hostname(host->mmc)); in __sdhci_execute_tuning_9750()
484 return -ETIMEDOUT; in __sdhci_execute_tuning_9750()
488 mmc_hostname(host->mmc)); in __sdhci_execute_tuning_9750()
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-synology-ds414.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
12 * were delivered with an older version of u-boot that left internal
17 * installing it from u-boot prompt) or adjust the Devive Tree
21 /dts-v1/;
23 #include <dt-bindings/input/input.h>
24 #include <dt-bindings/gpio/gpio.h>
25 #include "armada-xp-mv78230.dtsi"
29 compatible = "synology,ds414", "marvell,armadaxp-mv78230",
30 "marvell,armadaxp", "marvell,armada-370-xp";
[all …]
H A Darmada-388-gp.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * (RD-88F6820-GP)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 /dts-v1/;
12 #include "armada-388.dtsi"
13 #include <dt-bindings/gpio/gpio.h>
16 model = "Marvell Armada 388 DB-88F6820-GP";
17 compatible = "marvell,a388-gp", "marvell,armada388", "marvell,armada380";
20 stdout-path = "serial0:115200n8";
25 reg = <0x00000000 0x80000000>; /* 2 GB */
[all …]
H A Dkirkwood-synology.dtsi1 // SPDX-License-Identifier: GPL-2.0
12 pinctrl: pin-controller@10000 {
13 pmx_alarmled_12: pmx-alarmled-12 {
18 pmx_fanctrl_15: pmx-fanctrl-15 {
23 pmx_fanctrl_16: pmx-fanctrl-16 {
28 pmx_fanctrl_17: pmx-fanctrl-17 {
33 pmx_fanalarm_18: pmx-fanalarm-18 {
38 pmx_hddled_20: pmx-hddled-20 {
43 pmx_hddled_21: pmx-hddled-21 {
48 pmx_hddled_22: pmx-hddled-22 {
[all …]
H A Darmada-370-dlink-dns327l.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for D-Link DNS-327L
12 /dts-v1/;
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include "armada-370.dtsi"
19 model = "D-Link DNS-327L";
22 "marvell,armada-370-xp";
25 stdout-path = &uart0;
30 reg = <0x00000000 0x20000000>; /* 512 MiB */
[all …]
H A Darmada-370-mirabox.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include "armada-370.dtsi"
14 compatible = "globalscale,mirabox", "marvell,armada370", "marvell,armada-370-xp";
17 stdout-path = "serial0:115200n8";
22 reg = <0x00000000 0x20000000>; /* 512 MB */
30 internal-regs {
35 clock-frequency = <600000000>;
[all …]
/linux/sound/soc/codecs/
H A Dpeb2466.c1 // SPDX-License-Identifier: GPL-2.0
3 // peb2466.c -- Infineon PEB2466 ALSA SoC driver
32 int reg; member
42 u8 spi_tx_buf[2 + 8]; /* Cannot use stack area for SPI (dma-safe memory) */
43 u8 spi_rx_buf[2 + 8]; /* Cannot use stack area for SPI (dma-safe memory) */
136 .tx_buf = &peb2466->spi_tx_buf, in peb2466_write_byte()
140 peb2466->spi_tx_buf[0] = cmd | PEB2466_CMD_W; in peb2466_write_byte()
141 peb2466->spi_tx_buf[1] = val; in peb2466_write_byte()
143 dev_dbg(&peb2466->spi->dev, "write byte (cmd %02x) %02x\n", in peb2466_write_byte()
144 peb2466->spi_tx_buf[0], peb2466->spi_tx_buf[1]); in peb2466_write_byte()
[all …]
/linux/drivers/regulator/
H A Dstm32-pwr.c1 // SPDX-License-Identifier: GPL-2.0
50 val = readl_relaxed(priv->base + REG_PWR_CR3); in stm32_pwr_reg_is_ready()
52 return (val & priv->ready_mask); in stm32_pwr_reg_is_ready()
60 val = readl_relaxed(priv->base + REG_PWR_CR3); in stm32_pwr_reg_is_enabled()
62 return (val & rdev->desc->enable_mask); in stm32_pwr_reg_is_enabled()
71 val = readl_relaxed(priv->base + REG_PWR_CR3); in stm32_pwr_reg_enable()
72 val |= rdev->desc->enable_mask; in stm32_pwr_reg_enable()
73 writel_relaxed(val, priv->base + REG_PWR_CR3); in stm32_pwr_reg_enable()
79 dev_err(&rdev->dev, "regulator enable timed out!\n"); in stm32_pwr_reg_enable()
90 val = readl_relaxed(priv->base + REG_PWR_CR3); in stm32_pwr_reg_disable()
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx53-cx9020.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * based on imx53-qsb.dts
7 /dts-v1/;
15 stdout-path = &uart2;
20 reg = <0x70000000 0x20000000>,
24 display-0 {
25 #address-cells = <1>;
26 #size-cells = <0>;
27 compatible = "fsl,imx-parallel-display";
28 interface-pix-fmt = "rgb24";
[all …]
/linux/arch/arm64/boot/dts/broadcom/stingray/
H A Dstingray-board-base.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 * Copyright(c) 2016-2018 Broadcom
7 #include <dt-bindings/gpio/gpio.h>
18 stdout-path = "serial0:115200n8";
23 reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */
28 phy-mode = "rgmii-id";
29 phy-handle = <&gphy0>;
37 non-removable;
38 full-pwr-cycle;
42 full-pwr-cycle;
[all …]
/linux/Documentation/devicetree/bindings/leds/
H A Dleds-lp55xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/leds-lp55xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacek Anaszewski <jacek.anaszewski@gmail.com>
11 - Pavel Machek <pavel@ucw.cz>
27 - national,lp5521
28 - national,lp5523
29 - ti,lp55231
30 - ti,lp5562
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Drcar-gen4-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2022-2023 Renesas Electronics Corp.
4 ---
5 $id: http://devicetree.org/schemas/pci/rcar-gen4-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car Gen4 PCIe Endpoint
11 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
14 - $ref: snps,dw-pcie-ep.yaml#
19 - enum:
20 - renesas,r8a779f0-pcie-ep # R-Car S4-8
[all …]
H A Drcar-gen4-pci-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2022-2023 Renesas Electronics Corp.
4 ---
5 $id: http://devicetree.org/schemas/pci/rcar-gen4-pci-host.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car Gen4 PCIe Host
11 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
14 - $ref: snps,dw-pcie.yaml#
19 - enum:
20 - renesas,r8a779f0-pcie # R-Car S4-8
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra210-p2180.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/mfd/max77620.h>
18 stdout-path = "serial0:115200n8";
23 reg = <0x0 0x80000000 0x1 0x0>;
27 vdd-supply = <&vdd_gpu>;
33 /delete-property/ dmas;
34 /delete-property/ dma-names;
39 /delete-property/ reg-shift;
41 compatible = "nvidia,tegra30-hsuart";
42 reset-names = "serial";
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2711-rpi-cm4-io.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
3 #include <dt-bindings/leds/common.h>
4 #include "bcm2711-rpi-cm4.dtsi"
5 #include "bcm283x-rpi-led-deprecated.dtsi"
6 #include "bcm283x-rpi-usb-host.dtsi"
29 gpio-line-names = "ID_SDA",
109 reg = <0x51>;
110 quartz-load-femtofarads = <7000>;
116 #address-cells = <1>;
[all …]

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