Home
last modified time | relevance | path

Searched +full:polarity +full:- +full:active +full:- +full:low (Results 1 – 25 of 243) sorted by relevance

12345678910

/linux/include/media/i2c/
H A Dtvp7002.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics
6 * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>
19 * struct tvp7002_config - Platform dependent data
20 *@clk_polarity: Clock polarity
21 * 0 - Data clocked out on rising edge of DATACLK signal
22 * 1 - Data clocked out on falling edge of DATACLK signal
23 *@hs_polarity: HSYNC polarity
24 * 0 - Active low HSYNC output, 1 - Active high HSYNC output
25 *@vs_polarity: VSYNC Polarity
[all …]
/linux/drivers/media/dvb-frontends/
H A Dm88ds3103.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
19 * enum m88ds3103_ts_mode - TS connection mode
47 * struct m88ds3103_platform_data - Platform data for the m88ds3103 driver
52 * @ts_clk_pol: TS clk polarity. 1-active at falling edge; 0-active at rising
56 * @agc_inv: AGC polarity.
59 * @lnb_hv_pol: LNB H/V pin polarity. 0: pin high set to VOLTAGE_18, pin low to
60 * set VOLTAGE_13. 1: pin high set to VOLTAGE_13, pin low to set VOLTAGE_18.
61 * @lnb_en_pol: LNB enable pin polarity. 0: pin high to disable, pin low to
62 * enable. 1: pin high to enable, pin low to disable.
88 * struct m88ds3103_config - m88ds3102 configuration
[all …]
/linux/drivers/media/platform/ti/omap3isp/
H A Domap3isp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Bus Configuration
25 * struct isp_parallel_cfg - Parallel interface configuration
27 * 0 - CAMEXT[13:0] -> CAM[13:0]
28 * 2 - CAMEXT[13:2] -> CAM[11:0]
29 * 4 - CAMEXT[13:4] -> CAM[9:0]
30 * 6 - CAMEXT[13:6] -> CAM[7:0]
31 * @clk_pol: Pixel clock polarity
32 * 0 - Sample on rising edge, 1 - Sample on falling edge
33 * @hs_pol: Horizontal synchronization polarity
[all …]
/linux/Documentation/firmware-guide/acpi/
H A Dgpio-properties.rst1 .. SPDX-License-Identifier: GPL-2.0
31 ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
34 Package () { "reset-gpios", Package () { ^BTH, 1, 1, 0 } },
35 Package () { "shutdown-gpios", Package () { ^BTH, 0, 0, 0 } },
52 If 1, the GPIO is marked as active-low.
55 active-low or active-high, the "active_low" argument can be used here.
56 Setting it to 1 marks the GPIO as active-low.
61 In our Bluetooth example the "reset-gpios" refers to the second GpioIo()
68 and polarity settings. The table below shows the expectations:
70 +-------------+-------------+-----------------------------------------------+
[all …]
/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio.txt5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
32 data-gpios = <&gpio1 12 0>,
39 such as if the consumer desire the line to be active low (inverted) or open
44 recommended to use the two-cell approach.
[all …]
H A Dnvidia,tegra20-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra20-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPIO Controller (Tegra20 - Tegra210)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-gpio
18 - nvidia,tegra30-gpio
[all …]
/linux/Documentation/hwmon/
H A Dds1621.rst47 - Christian W. Zuckschwerdt <zany@triq.net>
48 - valuable contributions by Jan M. Sendler <sendler@sendler.de>
49 - ported to 2.6 by Aurelien Jarno <aurelien@aurel32.net>
53 ------------------
55 * polarity int
56 Output's polarity:
58 * 0 = active high,
59 * 1 = active low
62 -----------
65 both high and low temperature limits which can be user defined (i.e.
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Drichtek,rtmv20-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rtmv20-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
27 wakeup-source: true
32 enable-gpios:
36 richtek,ld-pulse-delay-us:
43 richtek,ld-pulse-width-us:
50 richtek,fsin1-delay-us:
[all …]
H A Dgpio-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/gpio-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liam Girdwood <lgirdwood@gmail.com>
11 - Mark Brown <broonie@kernel.org>
18 - $ref: regulator.yaml#
22 const: regulator-gpio
24 regulator-name: true
26 enable-gpios:
[all …]
/linux/include/dt-bindings/sound/
H A Dcs35l45.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * cs35l45.h -- CS35L45 ALSA SoC audio driver DT bindings header
12 * cirrus,asp-sdout-hiz-ctrl
14 * TX_HIZ_UNUSED: TX pin high-impedance during unused slots.
15 * TX_HIZ_DISABLED: TX pin high-impedance when all channels disabled.
21 * Optional GPIOX Sub-nodes:
22 * The cs35l45 node can have up to three "cirrus,gpio-ctrlX" ('X' = [1,2,3])
23 * sub-nodes for configuring the GPIO pins.
25 * - gpio-dir : GPIO pin direction. Valid only when 'gpio-ctrl'
30 * - gpio-lvl : GPIO level. Valid only when 'gpio-ctrl' is 1 and 'gpio-dir' is 0.
[all …]
/linux/Documentation/fb/
H A Dpxafb.rst10 modprobe pxafb options=vmem:2M,mode:640x480-8,passive
14 video=pxafb:vmem:2M,mode:640x480-8,passive
21 mode:XRESxYRES[-BPP]
53 active | passive => LCCR0_PAS
55 Active (TFT) or Passive (STN) display
67 Horizontal and vertical sync. 0 => active low, 1 => active
74 outputen:POLARITY
76 Output Enable Polarity. 0 => active low, 1 => active high
78 pixclockpol:POLARITY
80 pixel clock polarity
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Dchipidea,usb2-imx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/chipidea,usb2-imx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
15 - enum:
16 - fsl,imx27-usb
17 - items:
18 - enum:
19 - fsl,imx23-usb
[all …]
/linux/drivers/video/fbdev/
H A Dpxa3xx-regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
69 #define LCCR0_PAS (1 << 7) /* Passive/Active display Select */
71 #define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */
73 #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome display */
74 #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome display */
90 #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
91 #define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << FShft (LCCR1_PPL))
94 #define LCCR1_HorSnchWdth(Tpix) (((Tpix) - 1) << FShft (LCCR1_HSW))
96 #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait - 1 */
97 #define LCCR1_EndLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_ELW))
[all …]
/linux/Documentation/driver-api/
H A Dpwm.rst15 ----------------
24 PWM_LOOKUP("tegra-pwm", 0, "pwm-backlight", NULL,
36 ----------
82 PWM arguments are usually platform-specific and allows the PWM user to only
84 period). struct pwm_args contains 2 fields (period and polarity) and should
93 -----------------------------------
102 The number of PWM channels this chip supports (read-only).
105 Exports a PWM channel for use with sysfs (write-only).
108 Unexports a PWM channel from sysfs (write-only).
110 The PWM channels are numbered using a per-chip index from 0 to npwm-1.
[all …]
/linux/drivers/usb/chipidea/
H A Dci_hdrc_imx.h1 /* SPDX-License-Identifier: GPL-2.0+ */
15 /* true if over-current polarity is active low */
18 /* true if dt specifies polarity */
21 unsigned int pwr_pol:1; /* power polarity */
/linux/Documentation/devicetree/bindings/serial/
H A Drs485.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 direction for the built-in half-duplex mode. The properties described
11 hereafter shall be given to a half-duplex capable UART node.
14 - Rob Herring <robh@kernel.org>
17 rs485-rts-delay:
18 description: prop-encoded-array <a b>
19 $ref: /schemas/types.yaml#/definitions/uint32-array
21 - description: Delay between rts signal and beginning of data sent in
[all …]
/linux/Documentation/devicetree/bindings/display/samsung/
H A Dsamsung,exynos5-dp.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos5-dp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
17 const: samsung,exynos5-dp
25 clock-names:
[all …]
/linux/drivers/thermal/
H A Drockchip_thermal.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2016, Fuzhou Rockchip Electronics Co., Ltd
4 * Caesar Wang <wxt@rock-chips.com>
12 #include <linux/nvmem-consumer.h>
34 * The system Temperature Sensors tshut(tshut) polarity
35 * the bit 8 is tshut polarity.
36 * 0: low active, 1: high active
56 * struct chip_tsadc_table - hold information about chip-specific differences
70 * struct rockchip_tsadc_chip - hold the private data of tsadc chip
74 * @tshut_temp: the hardware-controlled shutdown temperature value, with no trim
[all …]
/linux/Documentation/devicetree/bindings/power/supply/
H A Dsummit,smb347-charger.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/supply/summit,smb347-charger.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David Heidelberg <david@ixit.cz>
11 - Dmitry Osipenko <digetx@gmail.com>
16 - summit,smb345
17 - summit,smb347
18 - summit,smb358
26 monitored-battery: true
[all …]
/linux/drivers/counter/
H A D104-quad-8.c1 // SPDX-License-Identifier: GPL-2.0
3 * Counter driver for the ACCES 104-QUAD-8
6 * This driver supports the ACCES 104-QUAD-8 and ACCES 104-QUAD-4.
32 MODULE_PARM_DESC(base, "ACCES 104-QUAD-8 base addresses");
37 MODULE_PARM_DESC(irq, "ACCES 104-QUAD-8 interrupt line numbers");
50 * struct quad8 - device private data structure
142 /* Non-recycle count */
144 /* Modulo-N */
146 /* Non-quadrature */
165 /* FLG1 = CARRY(active low); FLG2 = BORROW(active low) */
[all …]
/linux/drivers/gpio/
H A Dgpiolib-of.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2007-2008 MontaVista Software, Inc.
26 #include "gpiolib-of.h"
29 * This is Linux-specific flags. By default controllers' and Linux' mapping
31 * Linux-specific in their .xlate callback. Though, 1:1 mapping is recommended.
44 * of_gpio_named_count() - Count GPIOs for a device
53 * * %-EINVAL for an incorrectly formed "gpios" property, or
54 * * %-ENOENT for a missing "gpios" property.
69 return of_count_phandle_with_args(np, propname, "#gpio-cells"); in of_gpio_named_count()
73 * of_gpio_spi_cs_get_count() - special GPIO counting for SPI
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dnuvoton,nau8821.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Seven Lee <wtli@nuvoton.com>
13 - $ref: dai-common.yaml#
25 nuvoton,jkdet-enable:
29 nuvoton,jkdet-pull-enable:
30 description: Enable JKDET pin pull. If set - pin pull enabled,
34 nuvoton,jkdet-pull-up:
35 description: Pull-up JKDET pin. If set then JKDET pin is pull up,
[all …]
/linux/Documentation/devicetree/bindings/hwmon/
H A Dadi,ltc2947.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nuno Sá <nuno.sa@analog.com>
15 https://www.analog.com/media/en/technical-documentation/data-sheets/LTC2947.pdf
20 - adi,ltc2947
33 adi,accumulator-ctl-pol:
35 This property controls the polarity of current that is accumulated to
41 $ref: /schemas/types.yaml#/definitions/uint32-array
48 adi,accumulation-deadband-microamp:
[all …]
/linux/drivers/irqchip/
H A Dqcom-pdc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
47 #define pin_to_hwirq(r, p) ((r)->parent_base + (p) - (r)->pin_base)
79 /* Use previous DRV (client) region and shift to bank 3-4 */ in pdc_x1e_irq_enable_write()
84 /* Use our own region and shift to bank 0-2 */ in pdc_x1e_irq_enable_write()
86 bank -= 2; in pdc_x1e_irq_enable_write()
129 __pdc_enable_intr(d->hwirq, on); in pdc_enable_intr()
146 * GIC does not handle falling edge or active low. To allow falling edge and
147 * active low interrupts to be handled at GIC, PDC has an inverter that inverts
148 * falling edge into a rising edge and active low into an active high.
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dbrcm,iproc-gpio.txt5 - compatible:
6 "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7 supports full-featured pinctrl and GPIO functions used in various iProc
10 May contain an SoC-specific compatibility string to accommodate any
11 SoC-specific features
13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14 "brcm,cygnus-crmu-gpio" for Cygnus SoCs
16 "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
19 "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
23 - reg:
[all …]

12345678910