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/freebsd/sys/contrib/device-tree/Bindings/display/imx/
H A Dfsl,imx8qxp-dc-pixel-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qxp Display Controller Pixel Engine
10 All Processing Units that operate in the AXI bus clock domain. Pixel
13 functions. Interconnection of Processing Units is re-configurable.
16 - Liu Ying <victor.liu@nxp.com>
20 const: fsl,imx8qxp-dc-pixel-engine
28 "#address-cells":
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H A Dfsl,imx8qxp-dc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 components that include a blit engine for 2D graphics accelerations, display
17 +---------------------------+------------+------------------+-+-+------+
20 | @@@@@@@@@@@ +----------+------------+------------+ | | | |
22 X <-+->| Sequencer | | @@@@@@@@@@@@@@@@@@@@@@@@@@@@ | V V V |
24 | @@@@@@@@@@@ | | Pixel Engine | | | | |
28 H <-+->| Configure | | V V V V | | Engine | |
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H A Dfsl,imx8qxp-dc-extdst.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-extdst.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The External Destination unit is the interface between the internal pixel
11 processing pipeline of the Pixel Engine, which is 30-bit RGB plus 8-bit Alpha,
12 and a Display Engine.
14 It comprises the following built-in Gamma apply function.
16 +------X-----------------------+
19 | +-------+ |
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H A Dfsl,imx8qxp-dc-scaling-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-scaling-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qxp Display Controller Scaling Engine
11 re-sampling with 1/32 sub pixel precision.
24 +-----------+
27 +-----------+
31 |\ +-----------+
32 ------+ | | |
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H A Dfsl,imx8qxp-dc-matrix.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-matrix.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The unit supports linear color transformation, alpha pre-multiply and
14 - Liu Ying <victor.liu@nxp.com>
18 const: fsl,imx8qxp-dc-matrix
24 reg-names:
26 - const: cfg # matrix in display engine
27 - items: # matrix in pixel engine
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H A Dfsl,imx8qxp-dc-display-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-display-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qxp Display Controller Display Engine
10 All Processing Units that operate in a display clock domain. Pixel pipeline
15 - Liu Ying <victor.liu@nxp.com>
19 const: fsl,imx8qxp-dc-display-engine
24 reg-names:
26 - const: top
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/freebsd/sys/contrib/device-tree/Bindings/display/mediatek/
H A Dmediatek,dpi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - CK Hu <ck.hu@mediatek.com>
11 - Jitao shi <jitao.shi@mediatek.com>
15 subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a
21 - enum:
22 - mediatek,mt2701-dpi
23 - mediatek,mt7623-dpi
24 - mediatek,mt8173-dpi
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H A Dmediatek,dpi.txt5 provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
9 - compatible: "mediatek,<chip>-dpi"
11 - reg: Physical base address and length of the controller's registers
12 - interrupts: The interrupt signal from the function block.
13 - clocks: device clocks
14 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
15 - clock-names: must contain "pixel", "engine", and "pll"
16 - port: Output port node with endpoint definitions as described in
21 - pinctrl-names: Contain "default" and "sleep".
26 compatible = "mediatek,mt8173-dpi";
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H A Dmediatek,padding.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
16 width of a layer to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled,
24 - enum:
25 - mediatek,mt8188-disp-padding
26 - mediatek,mt8195-mdp3-padding
27 - items:
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H A Dmediatek,disp.txt6 and input selectors in the MMSYS_CONFIG register space. Pixel clock and start
17 A display stream starts at a source function block that reads pixel data from
29 - compatible: "mediatek,<chip>-disp-<function>", one of
30 "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc)
31 "mediatek,<chip>-disp-ovl-2l" - overlay (2 layers, blending, csc)
32 "mediatek,<chip>-disp-rdma" - read DMA / line buffer
33 "mediatek,<chip>-disp-wdma" - write DMA
34 "mediatek,<chip>-disp-ccorr" - color correction
35 "mediatek,<chip>-disp-color" - color processor
36 "mediatek,<chip>-disp-dither" - dither
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/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dfsl-pxp.txt1 Freescale Pixel Pipeline
4 The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine
6 pixel conversion via lookup table. Different versions are present on various
10 - compatible: should be "fsl,<soc>-pxp", where SoC can be one of imx23, imx28,
12 - reg: the register base and size for the device registers
13 - interrupts: the PXP interrupt, two interrupts for imx6ull and imx7d.
14 - clock-names: should be "axi"
15 - clocks: the PXP AXI clock
20 compatible = "fsl,imx6ull-pxp";
24 clock-names = "axi";
H A Dfsl,imx6ull-pxp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/fsl,imx6ull-pxp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Pixel Pipeline
10 - Philipp Zabel <p.zabel@pengutronix.de>
11 - Michael Tretter <m.tretter@pengutronix.de>
14 The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine
16 pixel conversion via lookup table. Different versions are present on various
22 - enum:
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H A Dnvidia,tegra-vde.txt1 NVIDIA Tegra Video Decoder Engine
4 - compatible : Must contain one of the following values:
5 - "nvidia,tegra20-vde"
6 - "nvidia,tegra30-vde"
7 - "nvidia,tegra114-vde"
8 - "nvidia,tegra124-vde"
9 - "nvidia,tegra132-vde"
10 - reg : Must contain an entry for each entry in reg-names.
11 - reg-names : Must include the following entries:
12 - sxe
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H A Dnvidia,tegra-vde.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nvidia,tegra-vde.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Video Decoder Engine
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
17 - items:
18 - enum:
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H A Dnxp,dw100.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xavier Roumegue <xavier.roumegue@oss.nxp.com>
12 description: |-
13 The Dewarp Engine provides high-performance dewarp processing for the
15 and wide angle lenses. It is implemented with a line/tile-cache based
18 The engine can be used to perform scaling, cropping and pixel format
24 - nxp,imx8mp-dw100
34 - description: The AXI clock
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H A Dnxp,imx8-isi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx8-isi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
15 sources. The inputs to the ISI go through Pixel Link interfaces, and their
16 number and nature is SoC-dependent. They cover both capture interfaces (MIPI
17 CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support.
22 - fsl,imx8mn-isi
23 - fsl,imx8mp-isi
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H A Dfsl,imx8qxp-isi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/fsl,imx8qxp-isi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 sources. The inputs to the ISI go through Pixel Link interfaces, and their
16 number and nature is SoC-dependent. They cover both capture interfaces (MIPI
17 CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support.
22 - fsl,imx8qxp-isi
30 clock-names:
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H A Dfsl,imx8qm-isi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/fsl,imx8qm-isi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 sources. The inputs to the ISI go through Pixel Link interfaces, and their
16 number and nature is SoC-dependent. They cover both capture interfaces (MIPI
17 CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support.
22 - fsl,imx8qm-isi
30 clock-names:
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/clock/imx8mp-clock.h>
9 /dts-v1/;
13 brightness-levels = <0 8 16 32 64 128 255>;
14 default-brightness-level = <8>;
15 enable-gpios = <&gpio5 23 GPIO_ACTIVE_LOW>;
16 num-interpolated-steps = <2>;
26 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>;
27 assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
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H A Dimx8mp-phyboard-pollux-rdk.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
9 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 #include <dt-bindings/leds/leds-pca9532.h>
11 #include <dt-bindings/pwm/pwm.h>
12 #include <dt-bindings/thermal/thermal.h>
13 #include "imx8mp-phycore-som.dtsi"
16 model = "PHYTEC phyBOARD-Pollux i.MX8MP";
17 compatible = "phytec,imx8mp-phyboard-pollux-rdk",
18 "phytec,imx8mp-phycore-som", "fsl,imx8mp";
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/freebsd/sys/contrib/device-tree/Bindings/display/
H A Darm,malidp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm Mali Display Processor (Mali-DP)
10 - Liviu Dudau <Liviu.Dudau@arm.com>
11 - Andre Przywara <andre.przywara@arm.com>
22 - arm,mali-dp500
23 - arm,mali-dp550
24 - arm,mali-dp650
31 - description:
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H A Darm,malidp.txt1 ARM Mali-DP
9 - compatible: should be one of
10 "arm,mali-dp500"
11 "arm,mali-dp550"
12 "arm,mali-dp650"
14 - reg: Physical base address and size of the block of registers used by
16 - interrupts: Interrupt list, as defined in ../interrupt-controller/interrupts.txt,
18 - interrupt-names: name of the engine inside the processor that will
20 - clocks: A list of phandle + clock-specifier pairs, one for each entry
21 in 'clock-names'
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/freebsd/sys/contrib/device-tree/src/arm/mediatek/
H A Dmt7623n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright © 2017-2020 MediaTek Inc.
10 #include <dt-bindings/memory/mt2701-larb-port.h>
19 compatible = "mediatek,mt7623-g3dsys",
20 "mediatek,mt2701-g3dsys",
23 #clock-cell
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/freebsd/sys/contrib/device-tree/Bindings/display/hisilicon/
H A Dhisi-ade.txt1 Device-Tree bindings for hisilicon ADE display controller driver
3 ADE (Advanced Display Engine) is the display controller which grab image
8 - compatible: value should be "hisilicon,hi6220-ade".
9 - reg: physical base address and length of the ADE controller's registers.
10 - hisilicon,noc-syscon: ADE NOC QoS syscon.
11 - resets: The ADE reset controller node.
12 - interrupt: the ldi vblank interrupt number used.
13 - clocks: a list of phandle + clock-specifier pairs, one for each entry
14 in clock-names.
15 - clock-names: should contain:
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/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_pll.c1 /*-
38 #include <dt-bindings/clock/tegra124-car.h>
88 /* Post divider <-> register value mapping. */
127 PLLC2: Clock source for engine scaling
128 PLLC3: Clock source for engine scaling
253 /* PLLC2: 600 MHz Clock source for engine scaling */
264 /* PLLC3: 600 MHz Clock source for engine scaling */
417 RD4(sc, sc->base_reg, &reg); in pll_enable()
418 if (sc->type != PLL_E) in pll_enable()
421 WR4(sc, sc->base_reg, reg); in pll_enable()
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