1// SPDX-License-Identifier: GPL-2.0 2// 3// Copyright (C) 2015 Freescale Semiconductor, Inc. 4 5#include <dt-bindings/media/video-interfaces.h> 6 7/ { 8 chosen { 9 stdout-path = &uart1; 10 }; 11 12 memory@80000000 { 13 device_type = "memory"; 14 reg = <0x80000000 0x20000000>; 15 }; 16 17 backlight_display: backlight-display { 18 compatible = "pwm-backlight"; 19 pwms = <&pwm1 0 5000000 0>; 20 brightness-levels = <0 4 8 16 32 64 128 255>; 21 default-brightness-level = <6>; 22 status = "okay"; 23 }; 24 25 reg_1v5: regulator-1v5 { 26 compatible = "regulator-fixed"; 27 regulator-name = "1v5"; 28 regulator-min-microvolt = <1500000>; 29 regulator-max-microvolt = <1500000>; 30 }; 31 32 reg_1v8: regulator-1v8 { 33 compatible = "regulator-fixed"; 34 regulator-name = "1v8"; 35 regulator-min-microvolt = <1800000>; 36 regulator-max-microvolt = <1800000>; 37 }; 38 39 reg_2v8: regulator-2v8 { 40 compatible = "regulator-fixed"; 41 regulator-name = "2v8"; 42 regulator-min-microvolt = <2800000>; 43 regulator-max-microvolt = <2800000>; 44 }; 45 46 reg_3v3: regulator-3v3 { 47 compatible = "regulator-fixed"; 48 regulator-name = "3v3"; 49 regulator-min-microvolt = <3300000>; 50 regulator-max-microvolt = <3300000>; 51 }; 52 53 reg_sd1_vmmc: regulator-sd1-vmmc { 54 compatible = "regulator-fixed"; 55 regulator-name = "VSD_3V3"; 56 regulator-min-microvolt = <3300000>; 57 regulator-max-microvolt = <3300000>; 58 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 59 enable-active-high; 60 }; 61 62 reg_peri_3v3: regulator-peri-3v3 { 63 compatible = "regulator-fixed"; 64 pinctrl-names = "default"; 65 pinctrl-0 = <&pinctrl_peri_3v3>; 66 regulator-name = "VPERI_3V3"; 67 regulator-min-microvolt = <3300000>; 68 regulator-max-microvolt = <3300000>; 69 gpio = <&gpio5 2 GPIO_ACTIVE_LOW>; 70 /* 71 * If you want to want to make this dynamic please 72 * check schematics and test all affected peripherals: 73 * 74 * - sensors 75 * - ethernet phy 76 * - can 77 * - bluetooth 78 * - wm8960 audio codec 79 * - ov5640 camera 80 */ 81 regulator-always-on; 82 }; 83 84 reg_can_3v3: regulator-can-3v3 { 85 compatible = "regulator-fixed"; 86 regulator-name = "can-3v3"; 87 regulator-min-microvolt = <3300000>; 88 regulator-max-microvolt = <3300000>; 89 gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; 90 }; 91 92 reg_audio_5v: regulator-audio-pwr { 93 compatible = "regulator-fixed"; 94 regulator-name = "audio-5v"; 95 regulator-min-microvolt = <5000000>; 96 regulator-max-microvolt = <5000000>; 97 regulator-always-on; 98 regulator-boot-on; 99 }; 100 101 reg_audio_3v3: regulator-audio-3v3 { 102 compatible = "regulator-fixed"; 103 regulator-name = "audio-3v3"; 104 regulator-min-microvolt = <3300000>; 105 regulator-max-microvolt = <3300000>; 106 regulator-always-on; 107 regulator-boot-on; 108 }; 109 110 reg_audio_1v8: regulator-audio-1v8 { 111 compatible = "regulator-fixed"; 112 regulator-name = "audio-1v8"; 113 regulator-min-microvolt = <1800000>; 114 regulator-max-microvolt = <1800000>; 115 regulator-always-on; 116 regulator-boot-on; 117 }; 118 119 sound-wm8960 { 120 compatible = "fsl,imx-audio-wm8960"; 121 model = "wm8960-audio"; 122 audio-cpu = <&sai2>; 123 audio-codec = <&codec>; 124 audio-asrc = <&asrc>; 125 hp-det-gpios = <&gpio5 4 0>; 126 audio-routing = 127 "Headphone Jack", "HP_L", 128 "Headphone Jack", "HP_R", 129 "Ext Spk", "SPK_LP", 130 "Ext Spk", "SPK_LN", 131 "Ext Spk", "SPK_RP", 132 "Ext Spk", "SPK_RN", 133 "LINPUT2", "Mic Jack", 134 "LINPUT3", "Mic Jack", 135 "RINPUT1", "AMIC", 136 "RINPUT2", "AMIC", 137 "Mic Jack", "MICB", 138 "AMIC", "MICB"; 139 }; 140 141 spi-4 { 142 compatible = "spi-gpio"; 143 pinctrl-names = "default"; 144 pinctrl-0 = <&pinctrl_spi4>; 145 status = "okay"; 146 sck-gpios = <&gpio5 11 0>; 147 mosi-gpios = <&gpio5 10 0>; 148 cs-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; 149 num-chipselects = <1>; 150 #address-cells = <1>; 151 #size-cells = <0>; 152 153 gpio_spi: gpio@0 { 154 compatible = "fairchild,74hc595"; 155 gpio-controller; 156 #gpio-cells = <2>; 157 reg = <0>; 158 registers-number = <1>; 159 spi-max-frequency = <100000>; 160 enable-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; 161 }; 162 }; 163 164 panel { 165 compatible = "innolux,at043tn24"; 166 backlight = <&backlight_display>; 167 power-supply = <®_3v3>; 168 169 port { 170 panel_in: endpoint { 171 remote-endpoint = <&display_out>; 172 }; 173 }; 174 }; 175}; 176 177&clks { 178 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 179 assigned-clock-rates = <786432000>; 180}; 181 182&i2c2 { 183 clock-frequency = <100000>; 184 pinctrl-names = "default"; 185 pinctrl-0 = <&pinctrl_i2c2>; 186 status = "okay"; 187 188 codec: wm8960@1a { 189 #sound-dai-cells = <0>; 190 compatible = "wlf,wm8960"; 191 reg = <0x1a>; 192 wlf,shared-lrclk; 193 wlf,hp-cfg = <3 2 3>; 194 wlf,gpio-cfg = <1 3>; 195 clocks = <&clks IMX6UL_CLK_SAI2>; 196 clock-names = "mclk"; 197 AVDD-supply = <®_audio_3v3>; 198 DBVDD-supply = <®_audio_1v8>; 199 DCVDD-supply = <®_audio_1v8>; 200 SPKVDD1-supply = <®_audio_5v>; 201 SPKVDD2-supply = <®_audio_5v>; 202 }; 203 204 camera@3c { 205 compatible = "ovti,ov5640"; 206 reg = <0x3c>; 207 pinctrl-names = "default"; 208 pinctrl-0 = <&pinctrl_camera_clock>; 209 clocks = <&clks IMX6UL_CLK_CSI>; 210 clock-names = "xclk"; 211 powerdown-gpios = <&gpio_spi 6 GPIO_ACTIVE_HIGH>; 212 reset-gpios = <&gpio_spi 5 GPIO_ACTIVE_LOW>; 213 AVDD-supply = <®_2v8>; 214 DVDD-supply = <®_1v5>; 215 DOVDD-supply = <®_1v8>; 216 217 port { 218 ov5640_to_parallel: endpoint { 219 remote-endpoint = <¶llel_from_ov5640>; 220 bus-width = <8>; 221 data-shift = <2>; /* lines 9:2 are used */ 222 hsync-active = <0>; 223 vsync-active = <0>; 224 pclk-sample = <1>; 225 }; 226 }; 227 }; 228}; 229 230&csi { 231 pinctrl-names = "default"; 232 pinctrl-0 = <&pinctrl_csi1>; 233 status = "okay"; 234 235 port { 236 parallel_from_ov5640: endpoint { 237 remote-endpoint = <&ov5640_to_parallel>; 238 bus-type = <MEDIA_BUS_TYPE_PARALLEL>; 239 }; 240 }; 241}; 242 243&fec1 { 244 pinctrl-names = "default"; 245 pinctrl-0 = <&pinctrl_enet1>; 246 phy-mode = "rmii"; 247 phy-handle = <ðphy0>; 248 phy-supply = <®_peri_3v3>; 249 status = "okay"; 250}; 251 252&fec2 { 253 pinctrl-names = "default"; 254 pinctrl-0 = <&pinctrl_enet2>; 255 phy-mode = "rmii"; 256 phy-handle = <ðphy1>; 257 phy-supply = <®_peri_3v3>; 258 status = "okay"; 259 260 mdio { 261 #address-cells = <1>; 262 #size-cells = <0>; 263 264 ethphy0: ethernet-phy@2 { 265 compatible = "ethernet-phy-id0022.1560"; 266 reg = <2>; 267 micrel,led-mode = <1>; 268 clocks = <&clks IMX6UL_CLK_ENET_REF>; 269 clock-names = "rmii-ref"; 270 271 }; 272 273 ethphy1: ethernet-phy@1 { 274 compatible = "ethernet-phy-id0022.1560"; 275 reg = <1>; 276 micrel,led-mode = <1>; 277 clocks = <&clks IMX6UL_CLK_ENET2_REF>; 278 clock-names = "rmii-ref"; 279 }; 280 }; 281}; 282 283&can1 { 284 pinctrl-names = "default"; 285 pinctrl-0 = <&pinctrl_flexcan1>; 286 xceiver-supply = <®_can_3v3>; 287 status = "okay"; 288}; 289 290&can2 { 291 pinctrl-names = "default"; 292 pinctrl-0 = <&pinctrl_flexcan2>; 293 xceiver-supply = <®_can_3v3>; 294 status = "okay"; 295}; 296 297&gpio_spi { 298 eth0-phy-hog { 299 gpio-hog; 300 gpios = <1 GPIO_ACTIVE_HIGH>; 301 output-high; 302 line-name = "eth0-phy"; 303 }; 304 305 eth1-phy-hog { 306 gpio-hog; 307 gpios = <2 GPIO_ACTIVE_HIGH>; 308 output-high; 309 line-name = "eth1-phy"; 310 }; 311}; 312 313&i2c1 { 314 clock-frequency = <100000>; 315 pinctrl-names = "default"; 316 pinctrl-0 = <&pinctrl_i2c1>; 317 status = "okay"; 318 319 magnetometer@e { 320 compatible = "fsl,mag3110"; 321 reg = <0x0e>; 322 vdd-supply = <®_peri_3v3>; 323 vddio-supply = <®_peri_3v3>; 324 }; 325}; 326 327&lcdif { 328 assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>; 329 assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>; 330 pinctrl-names = "default"; 331 pinctrl-0 = <&pinctrl_lcdif_dat 332 &pinctrl_lcdif_ctrl>; 333 status = "okay"; 334 335 port { 336 display_out: endpoint { 337 remote-endpoint = <&panel_in>; 338 }; 339 }; 340}; 341 342&pwm1 { 343 pinctrl-names = "default"; 344 pinctrl-0 = <&pinctrl_pwm1>; 345 status = "okay"; 346}; 347 348&qspi { 349 pinctrl-names = "default"; 350 pinctrl-0 = <&pinctrl_qspi>; 351 status = "okay"; 352 353 flash0: flash@0 { 354 #address-cells = <1>; 355 #size-cells = <1>; 356 compatible = "micron,n25q256a", "jedec,spi-nor"; 357 spi-max-frequency = <29000000>; 358 spi-rx-bus-width = <4>; 359 spi-tx-bus-width = <1>; 360 reg = <0>; 361 }; 362}; 363 364&sai2 { 365 pinctrl-names = "default"; 366 pinctrl-0 = <&pinctrl_sai2>; 367 assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, 368 <&clks IMX6UL_CLK_SAI2>; 369 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 370 assigned-clock-rates = <0>, <12288000>; 371 fsl,sai-mclk-direction-output; 372 status = "okay"; 373}; 374 375&snvs_poweroff { 376 status = "okay"; 377}; 378 379&snvs_pwrkey { 380 status = "okay"; 381}; 382 383&tsc { 384 pinctrl-names = "default"; 385 pinctrl-0 = <&pinctrl_tsc>; 386 xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; 387 measure-delay-time = <0xffff>; 388 pre-charge-time = <0xfff>; 389 status = "okay"; 390}; 391 392&uart1 { 393 pinctrl-names = "default"; 394 pinctrl-0 = <&pinctrl_uart1>; 395 status = "okay"; 396}; 397 398&uart2 { 399 pinctrl-names = "default"; 400 pinctrl-0 = <&pinctrl_uart2>; 401 uart-has-rtscts; 402 status = "okay"; 403}; 404 405&usbotg1 { 406 dr_mode = "otg"; 407 pinctrl-names = "default"; 408 pinctrl-0 = <&pinctrl_usb_otg1>; 409 status = "okay"; 410}; 411 412&usbotg2 { 413 dr_mode = "host"; 414 disable-over-current; 415 status = "okay"; 416}; 417 418&usbphy1 { 419 fsl,tx-d-cal = <106>; 420}; 421 422&usbphy2 { 423 fsl,tx-d-cal = <106>; 424}; 425 426&usdhc1 { 427 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 428 pinctrl-0 = <&pinctrl_usdhc1>; 429 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 430 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 431 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; 432 keep-power-in-suspend; 433 wakeup-source; 434 vmmc-supply = <®_sd1_vmmc>; 435 status = "okay"; 436}; 437 438&usdhc2 { 439 pinctrl-names = "default"; 440 pinctrl-0 = <&pinctrl_usdhc2>; 441 no-1-8-v; 442 broken-cd; 443 keep-power-in-suspend; 444 wakeup-source; 445 status = "okay"; 446}; 447 448&wdog1 { 449 pinctrl-names = "default"; 450 pinctrl-0 = <&pinctrl_wdog>; 451 fsl,ext-reset-output; 452}; 453 454&iomuxc { 455 pinctrl_camera_clock: cameraclockgrp { 456 fsl,pins = < 457 MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 458 >; 459 }; 460 461 pinctrl_csi1: csi1grp { 462 fsl,pins = < 463 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 464 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 465 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 466 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 467 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 468 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 469 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 470 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 471 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 472 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 473 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 474 >; 475 }; 476 477 pinctrl_enet1: enet1grp { 478 fsl,pins = < 479 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 480 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 481 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 482 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 483 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 484 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 485 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 486 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 487 >; 488 }; 489 490 pinctrl_enet2: enet2grp { 491 fsl,pins = < 492 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 493 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 494 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 495 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 496 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 497 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 498 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 499 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 500 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 501 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 502 >; 503 }; 504 505 pinctrl_flexcan1: flexcan1grp { 506 fsl,pins = < 507 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 508 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 509 >; 510 }; 511 512 pinctrl_flexcan2: flexcan2grp { 513 fsl,pins = < 514 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 515 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 516 >; 517 }; 518 519 pinctrl_i2c1: i2c1grp { 520 fsl,pins = < 521 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 522 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 523 >; 524 }; 525 526 pinctrl_i2c2: i2c2grp { 527 fsl,pins = < 528 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 529 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 530 >; 531 }; 532 533 pinctrl_lcdif_dat: lcdifdatgrp { 534 fsl,pins = < 535 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 536 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 537 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 538 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 539 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 540 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 541 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 542 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 543 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 544 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 545 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 546 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 547 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 548 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 549 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 550 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 551 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 552 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 553 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 554 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 555 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 556 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 557 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 558 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 559 >; 560 }; 561 562 pinctrl_lcdif_ctrl: lcdifctrlgrp { 563 fsl,pins = < 564 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 565 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 566 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 567 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 568 /* used for lcd reset */ 569 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 570 >; 571 }; 572 573 pinctrl_qspi: qspigrp { 574 fsl,pins = < 575 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 576 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 577 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 578 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 579 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 580 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 581 >; 582 }; 583 584 pinctrl_sai2: sai2grp { 585 fsl,pins = < 586 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 587 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 588 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 589 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 590 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 591 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 592 >; 593 }; 594 595 pinctrl_peri_3v3: peri3v3grp { 596 fsl,pins = < 597 MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 598 >; 599 }; 600 601 pinctrl_pwm1: pwm1grp { 602 fsl,pins = < 603 MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 604 >; 605 }; 606 607 pinctrl_sim2: sim2grp { 608 fsl,pins = < 609 MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 610 MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 611 MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 612 MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 613 MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 614 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 615 >; 616 }; 617 618 pinctrl_spi4: spi4grp { 619 fsl,pins = < 620 MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 621 MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 622 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 623 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 624 >; 625 }; 626 627 pinctrl_tsc: tscgrp { 628 fsl,pins = < 629 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 630 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 631 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 632 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 633 >; 634 }; 635 636 pinctrl_uart1: uart1grp { 637 fsl,pins = < 638 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 639 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 640 >; 641 }; 642 643 pinctrl_uart2: uart2grp { 644 fsl,pins = < 645 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 646 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 647 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 648 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 649 >; 650 }; 651 652 pinctrl_usb_otg1: usbotg1grp { 653 fsl,pins = < 654 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 655 >; 656 }; 657 658 pinctrl_usdhc1: usdhc1grp { 659 fsl,pins = < 660 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 661 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 662 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 663 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 664 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 665 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 666 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ 667 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ 668 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ 669 >; 670 }; 671 672 pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { 673 fsl,pins = < 674 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 675 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 676 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 677 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 678 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 679 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 680 681 >; 682 }; 683 684 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { 685 fsl,pins = < 686 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 687 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 688 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 689 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 690 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 691 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 692 >; 693 }; 694 695 pinctrl_usdhc2: usdhc2grp { 696 fsl,pins = < 697 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 698 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 699 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 700 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 701 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 702 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 703 >; 704 }; 705 706 pinctrl_wdog: wdoggrp { 707 fsl,pins = < 708 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 709 >; 710 }; 711}; 712