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/linux/include/linux/phy/
H A Dphy.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * phy.h -- generic phy header file
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
15 #include <linux/device.h>
19 #include <linux/phy/phy-dp.h>
20 #include <linux/phy/phy-hdmi.h>
21 #include <linux/phy/phy-lvds.h>
22 #include <linux/phy/phy-mipi-dphy.h>
24 struct phy;
57 * union phy_configure_opts - Opaque generic phy configuration
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/linux/drivers/phy/
H A Dphy-core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-core.c -- Generic Phy framework.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
15 #include <linux/device.h>
18 #include <linux/phy/phy.h>
23 static void phy_release(struct device *dev);
25 .name = "phy",
35 static void devm_phy_release(struct device *dev, void *res) in devm_phy_release()
37 struct phy *phy = *(struct phy **)res; in devm_phy_release() local
39 phy_put(dev, phy); in devm_phy_release()
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/linux/Documentation/translations/zh_CN/driver-api/phy/
H A Dphy.rst1 .. SPDX-License-Identifier: GPL-2.0
2 .. include:: ../../disclaimer-zh_CN.rst
4 :Original: Documentation/driver-api/phy/phy.rst
16 本文档解释了 PHY 的通用框架和提供的API，以及使用方法。
21 *PHY* 是物理层的缩写，它被用来把设备连接到一个物理媒介，例如USB控制器
22 有一个提供序列化、反序列化、编码、解码和负责获取所需的数据传输速率的 PHY。
23 注意，有些USB控制器内嵌了 PHY 的功能，其它的则使用了一个外置的PHY，此外
24 使用 PHY 的设备还有无线网、以太网、SATA等（控制器）。
26 创建这个框架的目的是将遍布 Linux 内核的 PHY 驱动程序融入到 drivers/phy，
29 该框架仅适用于使用外部 PHY（PHY 功能未嵌入控制器内）的设备。
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/linux/drivers/scsi/
H A Dscsi_transport_sas.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2005-2006 Dell Inc.
13 * introduces two additional intermediate objects: The SAS PHY
14 * as represented by struct sas_phy defines an "outgoing" PHY on
15 * a SAS HBA or Expander, and the SAS remote PHY represented by
16 * struct sas_rphy defines an "incoming" PHY on a SAS Expander or
17 * end device. Note that this is purely a software concept, the
18 * underlying hardware for a PHY and a remote PHY is the exactly
53 #define to_sas_host_attrs(host) ((struct sas_host_attrs *)(host)->shost_data)
102 return -EINVAL; \
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/linux/drivers/usb/core/
H A Dphy.c1 // SPDX-License-Identifier: GPL-2.0+
4 * multiple (actual) PHY devices. This is comes handy when initializing
10 #include <linux/device.h>
12 #include <linux/phy/phy.h>
15 #include "phy.h"
18 struct phy *phy; member
22 /* Allocate the roothub_entry by specific name of phy */
23 static int usb_phy_roothub_add_phy_by_name(struct device *dev, const char *name, in usb_phy_roothub_add_phy_by_name()
27 struct phy *phy; in usb_phy_roothub_add_phy_by_name() local
29 phy = devm_of_phy_get(dev, dev->of_node, name); in usb_phy_roothub_add_phy_by_name()
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/linux/drivers/staging/greybus/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
8 Select this option if you have a device that follows the
12 will be called gb-audio.ko
18 Select this option if you have a Toshiba APB device that has I2S
19 ports and acts as a Greybus "Dummy codec". This device is a
20 bridge from an APB-I2S port to a Unipro network.
23 will be called gb-audio-codec.ko
29 Select this option if you have a device that follows the
33 will be called gb-bootrom.ko
39 Select this option if you have a device that follows the
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/linux/drivers/dma/
H A Dmmp_pdma.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/dma-mapping.h>
15 #include <linux/device.h>
37 #define DCSR_NODESC BIT(30) /* No-Descriptor Fetch (read / write) */
39 #define DCSR_REQPEND BIT(8) /* Request Pending (read-only) */
40 #define DCSR_STOPSTATE BIT(3) /* Stop State (read-only) */
67 #define DCMD_ENDIAN BIT(18) /* Device Endian-ness. */
74 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
84 * The following 32-bit words are only used in the 64-bit, ie.
89 u32 ddadrh; /* High 32-bit of DDADR */
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/linux/drivers/scsi/smartpqi/
H A Dsmartpqi_sas_transport.c1 // SPDX-License-Identifier: GPL-2.0
3 * driver for Microchip PQI-based storage controllers
4 * Copyright (c) 2019-2023 Microchip Technology Inc. and its subsidiaries
5 * Copyright (c) 2016-2018 Microsemi Corporation
6 * Copyright (c) 2016 PMC-Sierra, Inc.
13 #include <linux/bsg-lib.h>
23 struct sas_phy *phy; in pqi_alloc_sas_phy() local
29 phy = sas_phy_alloc(pqi_sas_port->parent_node->parent_dev, in pqi_alloc_sas_phy()
30 pqi_sas_port->next_phy_index); in pqi_alloc_sas_phy()
31 if (!phy) { in pqi_alloc_sas_phy()
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/linux/rust/kernel/net/
H A Dphy.rs1 // SPDX-License-Identifier: GPL-2.0
5 //! Network PHY device.
7 //! C headers: [`include/linux/phy.h`](srctree/include/linux/phy.h).
14 /// PHY state machine states.
18 /// Some of PHY drivers access to the state of PHY'
74 pub struct Device(Opaque<bindings::phy_device>); global() struct
76 impl Device { global() implementation
284 impl AsRef<kernel::device::Device> for Device { global() implementation
285 as_ref(&self) -> &kernel::device::Device as_ref() argument
624 read_mmd(_dev: &mut Device, _devnum: u8, _regnum: u16) -> Result<u16> read_mmd() argument
629 write_mmd(_dev: &mut Device, _devnum: u8, _regnum: u16, _val: u16) -> Result write_mmd() argument
634 link_change_notify(_dev: &mut Device) link_change_notify() argument
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/linux/drivers/net/phy/
H A Dphy_device.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Also contains generic PHY driver
29 #include <linux/phy.h>
33 #include <linux/pse-pd/pse.h>
44 #include "phylib-internal.h"
45 #include "phy-caps.h"
47 MODULE_DESCRIPTION("PHY library");
51 #define PHY_ANY_ID "MATCH ANY PHY"
65 .name = "Generic Clause 45 PHY",
214 put_device(&phydev->mdio.dev); in phy_device_free()
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/linux/Documentation/ABI/testing/
H A Dsysfs-class-net-phydev1 What: /sys/class/mdio_bus/<bus>/<device>/attached_dev
6 Symbolic link to the network device this PHY device is
9 What: /sys/class/mdio_bus/<bus>/<device>/phy_has_fixups
14 This attribute contains the boolean value whether a given PHY
15 device has had any "fixup" workaround running on it, encoded as
17 PHY configurations.
19 What: /sys/class/mdio_bus/<bus>/<device>/phy_id
24 This attribute contains the 32-bit PHY Identifier as reported
25 by the device during bus enumeration, encoded in hexadecimal.
26 This ID is used to match the device with the appropriate
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/linux/drivers/phy/broadcom/
H A Dphy-bcm-cygnus-pcie.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/phy/phy.h>
24 * struct cygnus_pcie_phy - Cygnus PCIe PHY device
25 * @core: pointer to the Cygnus PCIe PHY core control
26 * @id: internal ID to identify the Cygnus PCIe PHY
27 * @phy: pointer to the kernel PHY device
32 struct phy *phy; member
36 * struct cygnus_pcie_phy_core - Cygnus PCIe PHY core control
37 * @dev: pointer to device
40 * @phys: pointer to Cygnus PHY device
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H A Dphy-bcm-sr-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Broadcom
12 #include <linux/phy/phy.h>
18 #define SR_PAXC_PHY_IDX (SR_NR_PCIE_PHYS - 1)
40 * struct sr_pcie_phy - Stingray PCIe PHY
42 * @core: pointer to the Stingray PCIe PHY core control
43 * @index: PHY index
44 * @phy: pointer to the kernel PHY device
49 struct phy *phy; member
53 * struct sr_pcie_phy_core - Stingray PCIe PHY core control
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/linux/Documentation/devicetree/bindings/phy/
H A Dphy-bindings.txt1 This document explains only the device tree data binding. For general
2 information about PHY subsystem refer to Documentation/driver-api/phy/phy.rst
4 PHY device node
8 #phy-cells: Number of cells in a PHY specifier; The meaning of all those
9 cells is defined by the binding for the phy node. The PHY
11 PHY.
14 phy-supply: Phandle to a regulator that provides power to the PHY. This
15 regulator will be managed during the PHY power on/off sequence.
19 phys: phy {
24 #phy-cells = <1>;
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H A Dmarvell,armada-cp110-utmi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/marvell,armada-cp110-utmi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Marvell Armada CP110/CP115 UTMI PHY
11 - Konstantin Porotchkin <kostap@marvell.com>
14 On Armada 7k/8k and CN913x, there are two host and one device USB controllers.
15 Each of two exiting UTMI PHYs could be connected to either USB host or USB device
17 The USB device controller can only be connected to a single UTMI PHY port
18 0.H----- USB HOST0
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H A Dti,da830-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/ti,da830-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI DA8xx/OMAP-L1xx/AM18xx USB PHY
10 - David Lechner <david@lechnology.com>
13 This device controls the PHY for both the USB 1.1 OHCI and USB 2.0 OTG
16 It also requires a "syscon" node with compatible = "ti,da830-cfgchip", "syscon"
22 - const: ti,da830-usb-phy
24 '#phy-cells':
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/linux/Documentation/devicetree/bindings/net/
H A Dibm,emac.txt8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
23 - mal-device : phandle of the associated McMAL node
24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
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H A Dcpsw.txt1 TI SoC Ethernet Switch Controller Device Tree Bindings
2 ------------------------------------------------------
5 - compatible : Should be one of the below:-
7 "ti,am335x-cpsw" for AM335x controllers
8 "ti,am4372-cpsw" for AM437x controllers
9 "ti,dra7-cpsw" for DRA7x controllers
10 - reg : physical base address and size of the cpsw
12 - interrupts : property with a value describing the interrupt
14 - cpdma_channels : Specifies number of channels in CPDMA
15 - ale_entries : Specifies No of entries ALE can hold
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/linux/drivers/phy/ralink/
H A Dphy-ralink-usb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include <linux/phy/phy.h>
56 struct phy *phy; member
61 static void u2_phy_w32(struct ralink_usb_phy *phy, u32 val, u32 reg) in u2_phy_w32() argument
63 writel(val, phy->base + reg); in u2_phy_w32()
66 static u32 u2_phy_r32(struct ralink_usb_phy *phy, u32 reg) in u2_phy_r32() argument
68 return readl(phy->base + reg); in u2_phy_r32()
71 static void ralink_usb_phy_init(struct ralink_usb_phy *phy) in ralink_usb_phy_init() argument
73 u2_phy_r32(phy, OFS_U2_PHY_AC2); in ralink_usb_phy_init()
74 u2_phy_r32(phy, OFS_U2_PHY_ACR0); in ralink_usb_phy_init()
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H A Dphy-mt7621-pci.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Mediatek MT7621 PCI PHY Driver
7 #include <dt-bindings/phy/phy.h>
13 #include <linux/phy/phy.h>
66 * struct mt7621_pci_phy - Mt7621 Pcie PHY core
67 * @dev: pointer to device
69 * @phy: pointer to the kernel PHY device
72 * @has_dual_port: if the phy has dual ports.
77 struct device *dev;
79 struct phy *phy; member
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/linux/Documentation/devicetree/bindings/usb/
H A Domap-usb.txt4 - compatible : Should be "ti,omap4-musb" or "ti,omap3-musb"
5 - ti,hwmods : must be "usb_otg_hs"
6 - multipoint : Should be "1" indicating the musb controller supports
7 multipoint. This is a MUSB configuration-specific setting.
8 - num-eps : Specifies the number of endpoints. This is also a
9 MUSB configuration-specific setting. Should be set to "16"
10 - ram-bits : Specifies the ram address size. Should be set to "12"
11 - interface-type : This is a board specific setting to describe the type of
12 interface between the controller and the phy. It should be "0" or "1"
14 - mode : Should be "3" to represent OTG. "1" signifies HOST and "2"
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/linux/Documentation/firmware-guide/acpi/dsd/
H A Dphy.rst1 .. SPDX-License-Identifier: GPL-2.0
7 The PHYs on an MDIO bus [phy] are probed and registered using
14 for connecting PHYs on the MDIO bus [dsd-properties-rules] to the MAC layer.
16 These properties are defined in accordance with the "Device
17 Properties UUID For _DSD" [dsd-guide] document and the
18 daffd814-6eba-4d8c-8a91-bc9bbf4aa301 UUID must be used in the Device
21 phy-handle
22 ----------
23 For each MAC node, a device property "phy-handle" is used to reference
24 the PHY that is registered on an MDIO bus. This is mandatory for
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/linux/drivers/phy/ti/
H A Dphy-ti-pipe3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-ti-pipe3 - PIPE3 PHY driver.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
13 #include <linux/phy/phy.h>
20 #include <linux/phy/omap_control_phy.h>
168 struct device *dev;
169 struct device *control_dev;
216 /* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */
242 /* DRA75x TRM Table 26-9 Preferred SATA_PHY_RX SCP Register Settings */
267 /* DRA75x TRM Table 26-62 Preferred PCIe_PHY_RX SCP Register Settings */
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/linux/drivers/pci/controller/dwc/
H A Dpcie-kirin.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <linux/phy/phy.h>
27 #include "pcie-designware.h"
29 #define to_kirin_pcie(x) dev_get_drvdata((x)->dev)
58 * in-board Ethernet adapter and the other two connected to M.2 and mini
75 struct phy *phy; member
81 /* Per-slot PERST# */
86 /* Per-slot clkreq */
93 * Kirin 960 PHY. Can't be split into a PHY driver without changing the
99 /* PHY info located in APB */
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/linux/drivers/pci/controller/cadence/
H A Dpcie-cadence.c1 // SPDX-License-Identifier: GPL-2.0
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
10 #include "pcie-cadence.h"
51 u64 sz = 1ULL << fls64(size - 1); in cdns_pcie_set_outbound_region()
84 * then the driver must provide the bus, resp. device, number in in cdns_pcie_set_outbound_region()
86 * number, the device number is always 0 in Root Complex mode. in cdns_pcie_set_outbound_region()
90 * device numbers. in cdns_pcie_set_outbound_region()
92 if (pcie->is_rc) { in cdns_pcie_set_outbound_region()
93 /* The device and function numbers are always 0. */ in cdns_pcie_set_outbound_region()
99 * Use captured values for bus and device numbers but still in cdns_pcie_set_outbound_region()
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