| /linux/tools/perf/pmu-events/arch/x86/goldmontplus/ |
| H A D | cache.json | 20 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
33 …from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cac…
72 …processor) in the system, one of those caching agents indicated that they had a dirty copy of the …
176 "BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)",
187 "BriefDescription": "Load uops retired that split a cache-line (Precise event capable)",
198 "BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)",
239 …ads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data for…
245 …ads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data for…
250 …s (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.",
256 …d & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Require…
[all …]
|
| H A D | pipeline.json | 116 …branch instructions retired, where the target address taken was not what the processor predicted.",
126 … supposed to be taken and when it was not supposed to be taken (but the processor predicted the op…
136 …t call or near indirect jmp, where the target address taken was not what the processor predicted.",
146 …branch instructions retired, where the return address taken was not what the processor predicted.",
156 …Met) branch instructions retired that were supposed to be taken but the processor predicted that i…
229 "BriefDescription": "Instructions retired - using Reduced Skid PEBS feature",
238 "BriefDescription": "Unfilled issue slots per cycle",
242 … slots per core cycle that were not consumed by the backend due to either a full resource in the …
246 "BriefDescription": "Unfilled issue slots per cycle to recover",
250 …slots per core cycle that were not consumed by the backend because allocation is stalled waiting f…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/elkhartlake/ |
| H A D | ehl-metrics.json | 4 "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
9 "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
14 … "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
19 … "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)",
24 "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
34 "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
|
| /linux/Documentation/devicetree/bindings/remoteproc/ |
| H A D | ti,keystone-rproc.txt | 5 sub-systems that are used to offload some of the processor-intensive tasks or
8 These processor sub-systems usually contain additional sub-modules like L1
10 a dedicated local power/sleep controller etc. The DSP processor core in
11 Keystone 2 SoCs is usually a TMS320C66x CorePac processor.
15 Each DSP Core sub-system is represented as a single DT node, and should also
17 or optional properties that enable the OS running on the host processor (ARM
18 CorePac) to perform the device management of the remote processor and to
19 communicate with the remote processor.
22 --------------------
25 - compatible: Should be one of the following,
[all …]
|
| H A D | ti,omap-remoteproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
[all …]
|
| H A D | ti,k3-dsp-rproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-dsp-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems
14 that are used to offload some of the processor-intensive tasks or algorithms,
17 These processor sub-systems usually contain additional sub-modules like
19 controller, a dedicated local power/sleep controller etc. The DSP processor
20 cores in the K3 SoCs are usually either a TMS320C66x CorePac processor or a
[all …]
|
| H A D | xlnx,zynqmp-r5fss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx R5F processor subsystem
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
[all …]
|
| /linux/tools/power/x86/x86_energy_perf_policy/ |
| H A D | x86_energy_perf_policy.8 | 1 .\" This page Copyright (C) 2010 - 2015 Len Brown <len.brown@intel.com>
5 x86_energy_perf_policy \- Manage Energy vs. Performance Policy via x86 Model Specific Registers
10 .RB "scope: \-\-cpu\ cpu-list | \-\-pkg\ pkg-list"
12 .RB "cpu-list, pkg-list: # | #,# | #-# | all"
14 .RB "field: \-\-all | \-\-epb | \-\-hwp-epp | \-\-hwp-min | \-\-hwp-max | \-\-hwp-desired"
16 .RB "other: (\-\-force | \-\-hwp-enable | \-\-turbo-enable) value)"
18 .RB "value: # | default | performance | balance-performance | balance-power | power"
21 displays and updates energy-performance policy settings specific to
23 updates, no matter if the Linux cpufreq sub-system is enabled or not.
27 such as how aggressively the hardware enters and exits CPU idle states (C-states)
[all …]
|
| /linux/drivers/media/platform/mediatek/mdp/ |
| H A D | mtk_mdp_core.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2015-2016 MediaTek Inc.
12 #include <media/v4l2-ctrls.h>
13 #include <media/v4l2-device.h>
14 #include <media/v4l2-mem2mem.h>
15 #include <media/videobuf2-core.h>
16 #include <media/videobuf2-dma-contig.h>
22 #define MTK_MDP_MODULE_NAME "mtk-mdp"
34 * struct mtk_mdp_pix_align - alignment of image
48 * struct mtk_mdp_fmt - the driver's internal color format data
[all …]
|
| /linux/Documentation/admin-guide/pm/ |
| H A D | intel_pstate.rst | 1 .. SPDX-License-Identifier: GPL-2.0
22 Documentation/admin-guide/pm/cpufreq.rst if you have not done that yet.]
24 For the processors supported by ``intel_pstate``, the P-state concept is broader
27 information about that). For this reason, the representation of P-states used
32 ``intel_pstate`` maps its internal representation of P-states to frequencies too
38 Since the hardware P-state selection interface used by ``intel_pstate`` is
43 time the corresponding CPU is taken offline and need to be re-initialized when
47 only way to pass early-configuration-time parameters to it is via the kernel
63 the processor.
66 -----------
[all …]
|
| H A D | intel_idle.rst | 1 .. SPDX-License-Identifier: GPL-2.0
20 a particular processor model in it depends on whether or not it recognizes that
21 processor model and may also depend on information coming from the platform
24 Documentation/admin-guide/pm/cpuidle.rst if you have not done that yet.]
26 ``intel_idle`` uses the ``MWAIT`` instruction to inform the processor that the
28 processor's functional blocks into low-power states. That instruction takes two
30 first of which, referred to as a *hint*, can be used by the processor to
38 only way to pass early-configuration-time parameters to it is via the kernel
55 C-state requests from the OS (e.g., C6 requests) to C1. The idea is that
56 firmware monitors CPU wake-up rate, and if it is higher than a
[all …]
|
| /linux/arch/arm/include/asm/ |
| H A D | proc-fns.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/include/asm/proc-fns.h
5 * Copyright (C) 1997-1999 Russell King
13 #include <asm/glue-proc.h>
21 * Don't change this structure - ASM code relies on it.
23 struct processor { struct
33 * Set up any processor specifics argument
37 * Check for processor bugs argument
41 * Disable any processor specifics argument
49 * Idle the processor argument
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/goldmont/ |
| H A D | pipeline.json | 116 …branch instructions retired, where the target address taken was not what the processor predicted.",
126 … supposed to be taken and when it was not supposed to be taken (but the processor predicted the op…
136 …t call or near indirect jmp, where the target address taken was not what the processor predicted.",
146 …branch instructions retired, where the return address taken was not what the processor predicted.",
156 …Met) branch instructions retired that were supposed to be taken but the processor predicted that i…
228 "BriefDescription": "Unfilled issue slots per cycle",
232 … slots per core cycle that were not consumed by the backend due to either a full resource in the …
236 "BriefDescription": "Unfilled issue slots per cycle to recover",
240 …slots per core cycle that were not consumed by the backend because allocation is stalled waiting f…
245 … "BriefDescription": "Unfilled issue slots per cycle because of a full resource in the backend",
[all …]
|
| /linux/arch/powerpc/include/asm/ |
| H A D | paca.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This control block defines the PACA which defines the processor
4 * specific data for each logical processor on the system.
21 #include <asm/exception-64e.h>
23 #include <asm/exception-64s.h>
34 #include <asm-generic/mmiowb_types.h>
49 #define get_slb_shadow() (get_paca()->slb_shadow_ptr)
59 * processor.
66 * read-only (after boot) fields in the first cacheline to
81 u16 paca_index; /* Logical processor number */
[all …]
|
| /linux/Documentation/arch/x86/ |
| H A D | intel-hfi.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Hardware-Feedback Interface for scheduling on Intel Hardware
8 --------
11 IA-32 Architectures Software Developer's Manual (Intel SDM) Volume 3 Section
19 -------------------------------
23 capability is given as a unit-less quantity in the range [0-255]. Higher values
30 at which these capabilities are updated is specific to each processor model. On
39 capabilities of a given logical processor becomes zero, it is an indication that
41 that processor for performance or energy efficiency reasons, respectively.
44 --------------------------------
[all …]
|
| /linux/tools/perf/pmu-events/arch/powerpc/power9/ |
| H A D | translation.json | 5 "BriefDescription": "Processor cycles"
15 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor…
20 "BriefDescription": "Double-Precion or Quad-Precision instruction completed"
50 "BriefDescription": "LSU Finished a PPC instruction (up to 4 per cycle)"
70 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local …
80 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot…
95 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
125 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to an…
130 "BriefDescription": "Demand LD - L2 Miss (not L2 hit)"
140 …"BriefDescription": "The number a times the core transitioned from a stall to ICT-empty for this t…
[all …]
|
| /linux/tools/perf/pmu-events/arch/powerpc/power8/ |
| H A D | other.json | 11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to …
17 …cles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 belong to lpar1, threads 4-5 belong …
113 …to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that re…
161 …ed. I-form branches do not set this event. In addition, B-form branches which do not use the BHT d…
167 …ed. I-form branches do not set this event. In addition, B-form branches which do not use the BHT d…
197 …ional Branch Completed on BR0 that had its target address predicted. Only XL-form branches set thi…
203 …ional Branch Completed on BR1 that had its target address predicted. Only XL-form branches set thi…
215 …t used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch …
221 …t used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch …
359 "BriefDescription": "IFU Finished a (non-branch) instruction",
[all …]
|
| /linux/arch/x86/mm/ |
| H A D | cpu_entry_area.c | 1 // SPDX-License-Identifier: GPL-2.0
39 max_cea = (CPU_ENTRY_AREA_MAP_SIZE - PAGE_SIZE) / CPU_ENTRY_AREA_SIZE; in init_cea_offsets()
88 * non-present PTEs, so be careful not to set it in that in cea_set_pte()
101 for ( ; pages; pages--, cea_vaddr+= PAGE_SIZE, ptr += PAGE_SIZE) in cea_map_percpu_pages()
114 cea = &get_cpu_entry_area(cpu)->cpu_debug_store; in percpu_setup_debug_store()
120 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers; in percpu_setup_debug_store()
122 * Force the population of PMDs for not yet allocated per cpu in percpu_setup_debug_store()
126 for (; npages; npages--, cea += PAGE_SIZE) in percpu_setup_debug_store()
134 npages = sizeof(estacks->name## _stack) / PAGE_SIZE; \
135 cea_map_percpu_pages(cea->estacks.name## _stack, \
[all …]
|
| /linux/tools/power/cpupower/po/ |
| H A D | it.po | 2 # Copyright (C) 2004-2009
9 "Project-Id-Version: cpufrequtils 0.3\n"
10 "Report-Msgid-Bugs-To: \n"
11 "POT-Creation-Date: 2011-03-08 17:03+0100\n"
12 "PO-Revision-Date: 2009-08-15 12:00+0900\n"
13 "Last-Translator: Mattia Dongili <malattia@gmail.com>\n"
14 "Language-Team: NONE\n"
16 "MIME-Version: 1.0\n"
17 "Content-Type: text/plain; charset=UTF-8\n"
18 "Content-Transfer-Encoding: 8bit\n"
[all …]
|
| /linux/tools/power/x86/turbostat/ |
| H A D | turbostat.8 | 3 turbostat \- Report processor frequency and idle statistics
12 .RB [ "\--interval seconds" ]
14 \fBturbostat \fP reports processor topology, frequency,
15 idle power-state statistics, temperature and power on X86 processors.
19 in one-shot upon its completion.
22 The 5-second interval can be changed using the --interval option.
26 Options can be specified with a single or double '-', and only as much of the option
27 name as necessary to disambiguate it from others is necessary. Note that options are case-sensitiv…
29 \fB--add attributes\fP add column with counter having specified 'attributes'. The 'location' attri…
39 … event for given device from /sys/bus/event_source/devices/<device>/events/<event> eg. c1-residency
[all …]
|
| /linux/arch/parisc/kernel/ |
| H A D | processor.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Initial setup-routines for HP 9000 based hardware.
6 * Modifications for PA-RISC (C) 1999-2008 Helge Deller <deller@gmx.de>
12 * Initial PA-RISC Version: 04-23-1999 by Helge Deller
26 #include <asm/processor.h>
32 #include <asm/parisc-device.h>
44 ** PARISC CPU driver - claim "device" and initialize CPU data structures.
46 ** Consolidate per CPU initialization into (mostly) one module.
50 ** The callback *should* do per-instance initialization of
51 ** everything including the monarch. "Per CPU" init code in
[all …]
|
| /linux/arch/arc/mm/ |
| H A D | highmem.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <asm/processor.h>
19 * for book-keeping
23 * fixmaps (compile time addr etc). Their book-keeping is done per cpu.
25 * Both these facts combined (preemption disabled and per-cpu allocation)
32 * - the kernel vaddr space from 0x7z to 0x8z (currently used by vmalloc/module)
35 * - Both fixmap/pkmap use a dedicated page table each, hooked up to swapper PGD
39 * - The fixed KMAP slots for kmap_local/atomic() require KM_MAX_IDX slots per
42 * - pkmap being preemptible, in theory could do with more than 256 concurrent
66 /* Due to recursive include hell, we can't do this in processor.h */ in kmap_init()
|
| /linux/arch/mips/include/asm/sn/ |
| H A D | nmi.h | 8 * Copyright (C) 1992 - 1997 Silicon Graphics, Inc.
17 * and is used to communicate between the master processor and the slave
21 * corresponding to a target processor that is in a slave loop, then sends
22 * an interrupt to the slave processor. The slave calls the desired
27 * There is an array of launch structures, one per CPU on the node. One
28 * interrupt level is used per CPU.
|
| H A D | launch.h | 6 * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
17 * and is used to communicate between the master processor and the slave
21 * corresponding to a target processor that is in a slave loop, then sends
22 * an interrupt to the slave processor. The slave calls the desired
26 * There is an array of launch structures, one per CPU on the node. One
27 * interrupt level is used per local CPU.
|
| /linux/Documentation/admin-guide/acpi/ |
| H A D | cppc_sysfs.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Collaborative Processor Performance Control (CPPC)
13 performance of a logical processor on a contiguous and abstract performance
15 to request performance levels and to measure per-cpu delivered performance.
27 $ ls -lR /sys/devices/system/cpu/cpu0/acpi_cppc/
30 -r--r--r-- 1 root root 65536 Mar 5 19:38 feedback_ctrs
31 -r--r--r-- 1 root root 65536 Mar 5 19:38 highest_perf
32 -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_freq
33 -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_nonlinear_perf
34 -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_perf
[all …]
|