xref: /linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml (revision d3b402c5a2d47f51eb0581da1a7b142f82cb10d1) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description:
13  The QMP PHY controller supports physical layer functionality for a number of
14  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
15
16properties:
17  compatible:
18    enum:
19      - qcom,glymur-qmp-gen4x2-pcie-phy
20      - qcom,glymur-qmp-gen5x4-pcie-phy
21      - qcom,kaanapali-qmp-gen3x2-pcie-phy
22      - qcom,qcs615-qmp-gen3x1-pcie-phy
23      - qcom,qcs8300-qmp-gen4x2-pcie-phy
24      - qcom,sa8775p-qmp-gen4x2-pcie-phy
25      - qcom,sa8775p-qmp-gen4x4-pcie-phy
26      - qcom,sar2130p-qmp-gen3x2-pcie-phy
27      - qcom,sc8180x-qmp-pcie-phy
28      - qcom,sc8280xp-qmp-gen3x1-pcie-phy
29      - qcom,sc8280xp-qmp-gen3x2-pcie-phy
30      - qcom,sc8280xp-qmp-gen3x4-pcie-phy
31      - qcom,sdm845-qhp-pcie-phy
32      - qcom,sdm845-qmp-pcie-phy
33      - qcom,sdx55-qmp-pcie-phy
34      - qcom,sdx65-qmp-gen4x2-pcie-phy
35      - qcom,sm8150-qmp-gen3x1-pcie-phy
36      - qcom,sm8150-qmp-gen3x2-pcie-phy
37      - qcom,sm8250-qmp-gen3x1-pcie-phy
38      - qcom,sm8250-qmp-gen3x2-pcie-phy
39      - qcom,sm8250-qmp-modem-pcie-phy
40      - qcom,sm8350-qmp-gen3x1-pcie-phy
41      - qcom,sm8350-qmp-gen3x2-pcie-phy
42      - qcom,sm8450-qmp-gen3x1-pcie-phy
43      - qcom,sm8450-qmp-gen4x2-pcie-phy
44      - qcom,sm8550-qmp-gen3x2-pcie-phy
45      - qcom,sm8550-qmp-gen4x2-pcie-phy
46      - qcom,sm8650-qmp-gen3x2-pcie-phy
47      - qcom,sm8650-qmp-gen4x2-pcie-phy
48      - qcom,sm8750-qmp-gen3x2-pcie-phy
49      - qcom,x1e80100-qmp-gen3x2-pcie-phy
50      - qcom,x1e80100-qmp-gen4x2-pcie-phy
51      - qcom,x1e80100-qmp-gen4x4-pcie-phy
52      - qcom,x1e80100-qmp-gen4x8-pcie-phy
53      - qcom,x1p42100-qmp-gen4x4-pcie-phy
54
55  reg:
56    minItems: 1
57    maxItems: 2
58
59  clocks:
60    minItems: 5
61    maxItems: 6
62
63  clock-names:
64    minItems: 5
65    items:
66      - const: aux
67      - const: cfg_ahb
68      - const: ref
69      - enum: [rchng, refgen]
70      - const: pipe
71      - const: pipediv2
72
73  power-domains:
74    maxItems: 1
75
76  resets:
77    minItems: 1
78    maxItems: 2
79
80  reset-names:
81    minItems: 1
82    items:
83      - const: phy
84      - const: phy_nocsr
85
86  vdda-phy-supply: true
87
88  vdda-pll-supply: true
89
90  vdda-qref-supply: true
91
92  qcom,4ln-config-sel:
93    description: PCIe 4-lane configuration
94    $ref: /schemas/types.yaml#/definitions/phandle-array
95    items:
96      - items:
97          - description: phandle of TCSR syscon
98          - description: offset of PCIe 4-lane configuration register
99          - description: offset of configuration bit for this PHY
100
101  "#clock-cells": true
102
103  clock-output-names:
104    maxItems: 1
105
106  "#phy-cells":
107    const: 0
108
109required:
110  - compatible
111  - reg
112  - clocks
113  - clock-names
114  - resets
115  - reset-names
116  - vdda-phy-supply
117  - vdda-pll-supply
118  - "#clock-cells"
119  - clock-output-names
120  - "#phy-cells"
121
122additionalProperties: false
123
124allOf:
125  - if:
126      properties:
127        compatible:
128          contains:
129            enum:
130              - qcom,sc8280xp-qmp-gen3x4-pcie-phy
131              - qcom,x1e80100-qmp-gen4x4-pcie-phy
132              - qcom,x1p42100-qmp-gen4x4-pcie-phy
133    then:
134      properties:
135        reg:
136          items:
137            - description: port a
138            - description: port b
139      required:
140        - qcom,4ln-config-sel
141    else:
142      properties:
143        reg:
144          maxItems: 1
145
146  - if:
147      properties:
148        compatible:
149          contains:
150            enum:
151              - qcom,kaanapali-qmp-gen3x2-pcie-phy
152              - qcom,qcs615-qmp-gen3x1-pcie-phy
153              - qcom,sar2130p-qmp-gen3x2-pcie-phy
154              - qcom,sc8180x-qmp-pcie-phy
155              - qcom,sdm845-qhp-pcie-phy
156              - qcom,sdm845-qmp-pcie-phy
157              - qcom,sdx55-qmp-pcie-phy
158              - qcom,sm8150-qmp-gen3x1-pcie-phy
159              - qcom,sm8150-qmp-gen3x2-pcie-phy
160              - qcom,sm8250-qmp-gen3x1-pcie-phy
161              - qcom,sm8250-qmp-gen3x2-pcie-phy
162              - qcom,sm8250-qmp-modem-pcie-phy
163              - qcom,sm8350-qmp-gen3x1-pcie-phy
164              - qcom,sm8350-qmp-gen3x2-pcie-phy
165              - qcom,sm8450-qmp-gen3x1-pcie-phy
166              - qcom,sm8450-qmp-gen3x2-pcie-phy
167              - qcom,sm8550-qmp-gen3x2-pcie-phy
168              - qcom,sm8550-qmp-gen4x2-pcie-phy
169              - qcom,sm8650-qmp-gen3x2-pcie-phy
170              - qcom,sm8650-qmp-gen4x2-pcie-phy
171              - qcom,sm8750-qmp-gen3x2-pcie-phy
172    then:
173      properties:
174        clocks:
175          maxItems: 5
176        clock-names:
177          maxItems: 5
178
179  - if:
180      properties:
181        compatible:
182          contains:
183            enum:
184              - qcom,glymur-qmp-gen4x2-pcie-phy
185              - qcom,glymur-qmp-gen5x4-pcie-phy
186              - qcom,qcs8300-qmp-gen4x2-pcie-phy
187              - qcom,sa8775p-qmp-gen4x2-pcie-phy
188              - qcom,sa8775p-qmp-gen4x4-pcie-phy
189              - qcom,sc8280xp-qmp-gen3x1-pcie-phy
190              - qcom,sc8280xp-qmp-gen3x2-pcie-phy
191              - qcom,sc8280xp-qmp-gen3x4-pcie-phy
192              - qcom,x1e80100-qmp-gen3x2-pcie-phy
193              - qcom,x1e80100-qmp-gen4x2-pcie-phy
194              - qcom,x1e80100-qmp-gen4x4-pcie-phy
195              - qcom,x1e80100-qmp-gen4x8-pcie-phy
196              - qcom,x1p42100-qmp-gen4x4-pcie-phy
197    then:
198      properties:
199        clocks:
200          minItems: 6
201        clock-names:
202          minItems: 6
203
204  - if:
205      properties:
206        compatible:
207          contains:
208            enum:
209              - qcom,glymur-qmp-gen4x2-pcie-phy
210              - qcom,glymur-qmp-gen5x4-pcie-phy
211              - qcom,kaanapali-qmp-gen3x2-pcie-phy
212              - qcom,sm8550-qmp-gen4x2-pcie-phy
213              - qcom,sm8650-qmp-gen4x2-pcie-phy
214              - qcom,x1e80100-qmp-gen3x2-pcie-phy
215              - qcom,x1e80100-qmp-gen4x2-pcie-phy
216              - qcom,x1e80100-qmp-gen4x4-pcie-phy
217              - qcom,x1e80100-qmp-gen4x8-pcie-phy
218              - qcom,x1p42100-qmp-gen4x4-pcie-phy
219    then:
220      properties:
221        resets:
222          minItems: 2
223        reset-names:
224          minItems: 2
225    else:
226      properties:
227        resets:
228          maxItems: 1
229        reset-names:
230          maxItems: 1
231
232  - if:
233      properties:
234        compatible:
235          contains:
236            enum:
237              - qcom,sm8450-qmp-gen4x2-pcie-phy
238              - qcom,sm8550-qmp-gen4x2-pcie-phy
239              - qcom,sm8650-qmp-gen4x2-pcie-phy
240    then:
241      properties:
242        "#clock-cells":
243          const: 1
244    else:
245      properties:
246        "#clock-cells":
247          const: 0
248
249examples:
250  - |
251    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
252
253    pcie2b_phy: phy@1c18000 {
254      compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
255      reg = <0x01c18000 0x2000>;
256
257      clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
258               <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
259               <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
260               <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
261               <&gcc GCC_PCIE_2B_PIPE_CLK>,
262               <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
263      clock-names = "aux", "cfg_ahb", "ref", "rchng",
264                    "pipe", "pipediv2";
265
266      power-domains = <&gcc PCIE_2B_GDSC>;
267
268      resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
269      reset-names = "phy";
270
271      vdda-phy-supply = <&vreg_l6d>;
272      vdda-pll-supply = <&vreg_l4d>;
273
274      #clock-cells = <0>;
275      clock-output-names = "pcie_2b_pipe_clk";
276
277      #phy-cells = <0>;
278    };
279
280    pcie2a_phy: phy@1c24000 {
281      compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
282      reg = <0x01c24000 0x2000>, <0x01c26000 0x2000>;
283
284      clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
285               <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
286               <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
287               <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
288               <&gcc GCC_PCIE_2A_PIPE_CLK>,
289               <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
290      clock-names = "aux", "cfg_ahb", "ref", "rchng",
291                    "pipe", "pipediv2";
292
293      power-domains = <&gcc PCIE_2A_GDSC>;
294
295      resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
296      reset-names = "phy";
297
298      vdda-phy-supply = <&vreg_l6d>;
299      vdda-pll-supply = <&vreg_l4d>;
300
301      qcom,4ln-config-sel = <&tcsr 0xa044 0>;
302
303      #clock-cells = <0>;
304      clock-output-names = "pcie_2a_pipe_clk";
305
306      #phy-cells = <0>;
307    };
308