xref: /linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml (revision 1d1ba4d390141d602dbce8f5f0ac19a384d10a64) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description:
13  The QMP PHY controller supports physical layer functionality for a number of
14  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
15
16properties:
17  compatible:
18    enum:
19      - qcom,qcs615-qmp-gen3x1-pcie-phy
20      - qcom,qcs8300-qmp-gen4x2-pcie-phy
21      - qcom,sa8775p-qmp-gen4x2-pcie-phy
22      - qcom,sa8775p-qmp-gen4x4-pcie-phy
23      - qcom,sar2130p-qmp-gen3x2-pcie-phy
24      - qcom,sc8180x-qmp-pcie-phy
25      - qcom,sc8280xp-qmp-gen3x1-pcie-phy
26      - qcom,sc8280xp-qmp-gen3x2-pcie-phy
27      - qcom,sc8280xp-qmp-gen3x4-pcie-phy
28      - qcom,sdm845-qhp-pcie-phy
29      - qcom,sdm845-qmp-pcie-phy
30      - qcom,sdx55-qmp-pcie-phy
31      - qcom,sdx65-qmp-gen4x2-pcie-phy
32      - qcom,sm8150-qmp-gen3x1-pcie-phy
33      - qcom,sm8150-qmp-gen3x2-pcie-phy
34      - qcom,sm8250-qmp-gen3x1-pcie-phy
35      - qcom,sm8250-qmp-gen3x2-pcie-phy
36      - qcom,sm8250-qmp-modem-pcie-phy
37      - qcom,sm8350-qmp-gen3x1-pcie-phy
38      - qcom,sm8350-qmp-gen3x2-pcie-phy
39      - qcom,sm8450-qmp-gen3x1-pcie-phy
40      - qcom,sm8450-qmp-gen4x2-pcie-phy
41      - qcom,sm8550-qmp-gen3x2-pcie-phy
42      - qcom,sm8550-qmp-gen4x2-pcie-phy
43      - qcom,sm8650-qmp-gen3x2-pcie-phy
44      - qcom,sm8650-qmp-gen4x2-pcie-phy
45      - qcom,sm8750-qmp-gen3x2-pcie-phy
46      - qcom,x1e80100-qmp-gen3x2-pcie-phy
47      - qcom,x1e80100-qmp-gen4x2-pcie-phy
48      - qcom,x1e80100-qmp-gen4x4-pcie-phy
49      - qcom,x1e80100-qmp-gen4x8-pcie-phy
50      - qcom,x1p42100-qmp-gen4x4-pcie-phy
51
52  reg:
53    minItems: 1
54    maxItems: 2
55
56  clocks:
57    minItems: 5
58    maxItems: 7
59
60  clock-names:
61    minItems: 5
62    items:
63      - const: aux
64      - const: cfg_ahb
65      - const: ref
66      - enum: [rchng, refgen]
67      - const: pipe
68      - const: pipediv2
69      - const: phy_aux
70
71  power-domains:
72    maxItems: 1
73
74  resets:
75    minItems: 1
76    maxItems: 2
77
78  reset-names:
79    minItems: 1
80    items:
81      - const: phy
82      - const: phy_nocsr
83
84  vdda-phy-supply: true
85
86  vdda-pll-supply: true
87
88  vdda-qref-supply: true
89
90  qcom,4ln-config-sel:
91    description: PCIe 4-lane configuration
92    $ref: /schemas/types.yaml#/definitions/phandle-array
93    items:
94      - items:
95          - description: phandle of TCSR syscon
96          - description: offset of PCIe 4-lane configuration register
97          - description: offset of configuration bit for this PHY
98
99  "#clock-cells": true
100
101  clock-output-names:
102    maxItems: 1
103
104  "#phy-cells":
105    const: 0
106
107required:
108  - compatible
109  - reg
110  - clocks
111  - clock-names
112  - resets
113  - reset-names
114  - vdda-phy-supply
115  - vdda-pll-supply
116  - "#clock-cells"
117  - clock-output-names
118  - "#phy-cells"
119
120additionalProperties: false
121
122allOf:
123  - if:
124      properties:
125        compatible:
126          contains:
127            enum:
128              - qcom,sc8280xp-qmp-gen3x4-pcie-phy
129              - qcom,x1e80100-qmp-gen4x4-pcie-phy
130              - qcom,x1p42100-qmp-gen4x4-pcie-phy
131    then:
132      properties:
133        reg:
134          items:
135            - description: port a
136            - description: port b
137      required:
138        - qcom,4ln-config-sel
139    else:
140      properties:
141        reg:
142          maxItems: 1
143
144  - if:
145      properties:
146        compatible:
147          contains:
148            enum:
149              - qcom,qcs615-qmp-gen3x1-pcie-phy
150              - qcom,sar2130p-qmp-gen3x2-pcie-phy
151              - qcom,sc8180x-qmp-pcie-phy
152              - qcom,sdm845-qhp-pcie-phy
153              - qcom,sdm845-qmp-pcie-phy
154              - qcom,sdx55-qmp-pcie-phy
155              - qcom,sm8150-qmp-gen3x1-pcie-phy
156              - qcom,sm8150-qmp-gen3x2-pcie-phy
157              - qcom,sm8250-qmp-gen3x1-pcie-phy
158              - qcom,sm8250-qmp-gen3x2-pcie-phy
159              - qcom,sm8250-qmp-modem-pcie-phy
160              - qcom,sm8350-qmp-gen3x1-pcie-phy
161              - qcom,sm8350-qmp-gen3x2-pcie-phy
162              - qcom,sm8450-qmp-gen3x1-pcie-phy
163              - qcom,sm8450-qmp-gen3x2-pcie-phy
164              - qcom,sm8550-qmp-gen3x2-pcie-phy
165              - qcom,sm8550-qmp-gen4x2-pcie-phy
166              - qcom,sm8650-qmp-gen3x2-pcie-phy
167              - qcom,sm8650-qmp-gen4x2-pcie-phy
168              - qcom,sm8750-qmp-gen3x2-pcie-phy
169    then:
170      properties:
171        clocks:
172          maxItems: 5
173        clock-names:
174          maxItems: 5
175
176  - if:
177      properties:
178        compatible:
179          contains:
180            enum:
181              - qcom,sa8775p-qmp-gen4x2-pcie-phy
182              - qcom,sa8775p-qmp-gen4x4-pcie-phy
183              - qcom,sc8280xp-qmp-gen3x1-pcie-phy
184              - qcom,sc8280xp-qmp-gen3x2-pcie-phy
185              - qcom,sc8280xp-qmp-gen3x4-pcie-phy
186              - qcom,x1e80100-qmp-gen3x2-pcie-phy
187              - qcom,x1e80100-qmp-gen4x2-pcie-phy
188              - qcom,x1e80100-qmp-gen4x4-pcie-phy
189              - qcom,x1e80100-qmp-gen4x8-pcie-phy
190              - qcom,x1p42100-qmp-gen4x4-pcie-phy
191    then:
192      properties:
193        clocks:
194          minItems: 6
195        clock-names:
196          minItems: 6
197
198  - if:
199      properties:
200        compatible:
201          contains:
202            enum:
203              - qcom,qcs8300-qmp-gen4x2-pcie-phy
204    then:
205      properties:
206        clocks:
207          minItems: 7
208        clock-names:
209          minItems: 7
210
211  - if:
212      properties:
213        compatible:
214          contains:
215            enum:
216              - qcom,sm8550-qmp-gen4x2-pcie-phy
217              - qcom,sm8650-qmp-gen4x2-pcie-phy
218              - qcom,x1e80100-qmp-gen4x2-pcie-phy
219              - qcom,x1e80100-qmp-gen4x4-pcie-phy
220              - qcom,x1e80100-qmp-gen4x8-pcie-phy
221    then:
222      properties:
223        resets:
224          minItems: 2
225        reset-names:
226          minItems: 2
227
228  - if:
229      properties:
230        compatible:
231          contains:
232            enum:
233              - qcom,sm8450-qmp-gen4x2-pcie-phy
234              - qcom,sm8550-qmp-gen4x2-pcie-phy
235              - qcom,sm8650-qmp-gen4x2-pcie-phy
236    then:
237      properties:
238        "#clock-cells":
239          const: 1
240    else:
241      properties:
242        "#clock-cells":
243          const: 0
244
245examples:
246  - |
247    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
248
249    pcie2b_phy: phy@1c18000 {
250      compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
251      reg = <0x01c18000 0x2000>;
252
253      clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
254               <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
255               <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
256               <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
257               <&gcc GCC_PCIE_2B_PIPE_CLK>,
258               <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
259      clock-names = "aux", "cfg_ahb", "ref", "rchng",
260                    "pipe", "pipediv2";
261
262      power-domains = <&gcc PCIE_2B_GDSC>;
263
264      resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
265      reset-names = "phy";
266
267      vdda-phy-supply = <&vreg_l6d>;
268      vdda-pll-supply = <&vreg_l4d>;
269
270      #clock-cells = <0>;
271      clock-output-names = "pcie_2b_pipe_clk";
272
273      #phy-cells = <0>;
274    };
275
276    pcie2a_phy: phy@1c24000 {
277      compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
278      reg = <0x01c24000 0x2000>, <0x01c26000 0x2000>;
279
280      clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
281               <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
282               <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
283               <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
284               <&gcc GCC_PCIE_2A_PIPE_CLK>,
285               <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
286      clock-names = "aux", "cfg_ahb", "ref", "rchng",
287                    "pipe", "pipediv2";
288
289      power-domains = <&gcc PCIE_2A_GDSC>;
290
291      resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
292      reset-names = "phy";
293
294      vdda-phy-supply = <&vreg_l6d>;
295      vdda-pll-supply = <&vreg_l4d>;
296
297      qcom,4ln-config-sel = <&tcsr 0xa044 0>;
298
299      #clock-cells = <0>;
300      clock-output-names = "pcie_2a_pipe_clk";
301
302      #phy-cells = <0>;
303    };
304